Ultra-Low-Power Processors

CMOS Scaling Trends

and Beyond

Scaling transistors and following Moore’s law have served the

industry well for more than 50 years in providing integrated circuits
that are denser, cheaper, higher performance, and lower power.
This article describes trends in CMOS scaling over the past decade
and discusses some of the new device options and technology
directions being explored to continue scaling into the future.

G
Mark T. Bohr, ordon Moore famously predicted in his 1965 paper that the number of com-
Ian A. Young ponents per chip would continue to increase by a factor of two every year.1
Intel The goals of following Moore’s law are to decrease the cost per component and
reduce the power consumed per component. In 1975, Moore updated his earlier
prediction by forecasting that components per chip would increase by a factor of two every
two years, and that this would come from the combination of scaling component size and
increasing chip area.2 Back in 1965, the industry was producing chips using a minimum fea-
ture size of approximately 50 mm totaling about 50 components. Today’s leading chips use
a minimum feature size of approximately 10 nm and incorporate several billion transistors.
Robert Dennard and colleagues described in 1974 a scaling methodology for
metal-oxide-semiconductor field-effect transistors (MOSFETs) that would deliver consis-
tent improvements in transistor area, performance, and power reduction.3 The methodology
called for the scaling of transistor gate length, gate width, gate oxide thickness, and supply
voltage all by the same scale factor, and increasing channel doping by the inverse of the same
scale factor (see Figure 1). The result would be transistors with smaller area, higher drive cur-
rent (higher performance), and lower parasitic capacitance (lower active power). This method
for scaling MOSFET transistors is generally referred to as “classic” or “traditional” scaling and
was very successfully used by the industry up until the 130-nm generation in the early 2000s.
For the past 20 years, we have been developing new generations of process technologies
on a two-year cadence, and each generation scaled the minimum feature size by approxi-
mately 0.7 times to deliver an area scaling improvement of about 0.5 times (see Figure 2).
Thus, we have been doubling transistor density every two years. But recent technology gen-
erations (such as 14 nm and 10 nm) have taken longer to develop than the normal two-year
cadence, owing to increased process complexity and an increased number of photomasking
steps. Nonetheless, Intel’s 14-nm and 10-nm technologies have provided better-than-normal
transistor density improvements that keep us on pace with increasing transistor density at a
rate of doubling about every two years.

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 Transistor Innovations Device or circuit parameter Scaling factor
As mentioned earlier, traditional MOSFET Device dimension tox, L, W 1/κ Voltage, V Wiring
scaling worked well up until the 130-nm gener- Doping concentration Na κ
ation in the early 2000s. By that generation, the Voltage V 1/κ
Gate W
n+ n+
SiO2 gate oxide thickness had scaled to about Current I 1/κ source
†OX
drain
1.2 nm, and electron tunneling through such a Capacitance eA /t 1/κ
XD

thin dielectric was becoming a significant por- L

Delay time/circuit VC/I 1/κ
tion of total transistor leakage current. We had p Substrate, doping NA
Power dissipation/circuit VI 1/κ2
reached the limit for scaling transistors using
traditional methods, and we needed to start Power density VI/A 1

introducing innovations in transistor materials Figure 1. Traditional MOSFET scaling as described by Robert Dennard.
and structure to continue scaling.
One of the first significant innovations
10 10,000
was the introduction of strained silicon tran-
sistors on Intel’s 90-nm technology in 2003.4
This innovation used tensile stain in n-channel
1 1,000
MOS (NMOS) transistor channels to increase
electron mobility and compressive strain in
p-channel MOS (PMOS) channels to increase
Micron

nm
0.1 100
hole mobility (see Figure 3). Tensile strain was ~0.7x every
induced by adding a high-stress film above 2 years
the NMOS transistor. Compressive strain was
0.01 10
induced by replacing the PMOS source-drain
regions with epitaxial SiGe depositions. The
resultant increases in electron and hole mobil-
0.001 1
ity provided increased transistor drive currents 1970 1980 1990 2000 2010 2020 2030
without having to further scale the SiO2 gate
Figure 2. Minimum feature size scaling trend for Intel logic technologies.
oxide thickness. This strained silicon technique
has been adopted by all major semiconductor
companies and continues to be used on the lat-
est 10-nm technologies. on Intel’s 22-nm technology in 2011.6 Tradi-
The need to improve the transistor gate tional planar MOSFETs had been able to scale
dielectric to continue scaling could not be transistor gate length down to about 32 nm to
avoided, and Intel’s 45-nm technology in deliver good performance and density while also
2007 first introduced high-k metal gate tran- maintaining low off-state leakage. But scaling
sistors.5 The traditional SiO2 gate oxide was the gate length below 32 nm was problematic
replaced by a hafnium-based high-k dielectric. without sacrificing either performance or leak-
The high-k dielectric both reduced gate oxide age. A solution was to convert from a planar
leakage current and improved transistor drive transistor structure to a 3D FinFET structure in
current. The traditional doped-polysilicon gate which the gate electrode had better electrostatic
electrode was replaced by metal electrodes with control of the transistor channel formed in a tall
separate materials for NMOS and PMOS to narrow silicon fin (see Figure 5). This improved
provide optimal transistor threshold voltages. electrostatic control provided scaled transistors
The combination of high-k dielectric and metal with steeper sub-threshold slope (see Figure
gate electrodes (see Figure 4) was a revolution- 6a). Steeper sub-threshold slope either provided
ary process change that provided significant transistors with lower off-state leakage or allowed
improvements in transistor performance while threshold voltage to be reduced, which enabled
also reducing transistor leakage current. High-k improved performance at low operating voltage
metal gate transistors are now universally used (see Figure 6b). Operating integrated circuits
on advanced logic technologies. at a lower voltage is highly desired in order to
The next major transistor innovation was reduce active power consumption. All advanced
the introduction of FinFET (tri-gate) transistors logic technologies now use FinFET transistors

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 Ultra-Low-Power Processors

High- NMOS PMOS

stress
film

SiGe SiGe

(a) (b)

Figure 3. Channel strain techniques used on 90-nm generation transistors. (a) NMOS transistor
using SiN cap layer; tensile channel strain. (b) PMOS transistor using SiGe source-drain; compressive
channel strain.

NiSi

Metal
PolySi

SiO2 High-κ
SiGe SiGe SiGe
SiGe

Silicon Silicon
(a) (b)
Figure 4. Comparison of transistor structures. (a) 65-nm generation transistor using SiO2 dielectric;
polysilicon gate electrode. (b) 45-nm generation transistor using hafnium-based dielectric; metal
gate electrode.

for their good density and superior low-voltage 70-nm transistor gate pitch, 42-nm fin pitch,
performance compared to planar transistors. As 52-nm interconnect pitch, double patterning
Figure 7 shows, when traditional MOSFET scal- techniques, and a 6-T SRAM bitcell area of
ing ran out of steam in the early 2000s, innova- 0.0588 mm2.7 This technology took longer to
tions such as strained silicon, high-k metal gate, develop and get ready for volume manufactur-
and FinFETs were needed, and we must now ing due to the increased process complexity
continually invent new transistor materials and and mask count: about 2.5 years instead of the
structures to continue scaling. normal 2-year cadence. But this technology
also provided better-than-normal area scal-
Recent Logic Technologies ing. Instead of the 0.5 times area scaling that
Intel’s 14-nm logic technology started vol- new technology generations normally provide,
ume production early in 2014. This was Intel’s 14-nm technology provided about 0.37
Intel’s second-generation FinFET technol- times logic area scaling compared to the previ-
ogy, and it used advanced features such as ous 22-nm technology (see Figure 8).

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 Gate Gate

Drain

Source

Oxide Oxide

Silicon Silicon
substrate substrate

(a) (b)
Figure 5. Comparison of transistor structures. (a) Planar transistor. (b) FinFET transistor.

10 2.0
Transistor gate delay (normalized)

1 1.8
Channel current (normalized)

1.6
0.1 37%
faster 32-nm planar
Planar 1.4
0.01 FinFET
1.2
0.001 18%
1.0
faster
0.0001 22-nm
Reduced 0.8 FinFET
leakage current
1E-05 0.6
0.0 0.2 0.4 0.6 0.8 1.0 0.5 0.6 0.7 0.8 0.9 1.0 1.1
(a) Gate voltage (V) (b) Operating voltage (V)

Figure 6. Comparison of planar versus FinFET transistor electrical characteristics. (a) Channel
current versus gate voltage. (b) Transistor gate delay versus operating voltage.

90 nm 65 nm 45 nm 32 nm 22 nm 14 nm
2003 2005 2007 2009 2011 2014

Metal

SiGe SiGe
High-j SiGe
SiGe

Silicon

Strained silicon

High-j metal gate

FinFET

Figure 7. Six generations of Intel transistor innovations used to continue scaling.

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 Ultra-Low-Power Processors

1
technologies have been scaling transistor area,
45 nm 0.49x
and Figure 9b shows the trend of increasing
wafer cost due to increased process complexity.
32 nm 0.45x Figure 9c shows how the cost per transistor con-
tinues to come down due to better-than-normal
Logic area (relative)

22 nm area scaling. Figure 10 shows Intel’s trends for

0.37x
improving transistor performance (Figure 10a)
0.1
0.5
and reducing dynamic capacitance to lower
x active power (Figure 10b). Figure 10c shows
14 nm 2 y eve
ea ry 0.37x
rs how performance improvement divided by
active power consumption (performance per
10 nm watt) continues to improve with each gener-
ation. Different products on a given technol-
ogy can choose to tune the transistor or design
0.01
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 to deliver better performance or lower power,
HVM wafer start date depending on what the application values most.
Figure 8. Intel’s trend for scaling logic circuit area over the past five Figure 10 also shows the strategy of developing
generations. performance-enhanced versions of each gener-
ation (for example, 101 and 1011) to deliver
improved performance per watt and extend the
Intel’s newest 10-nm logic technology is life of these technologies.
scheduled to start product shipments before
the end of 2017. This 10-nm technology intro- Future Device Options
duces some advanced process features such as MOSFET transistor researchers are exploring
54-nm transistor gate pitch, 34-nm fin pitch, device structure and channel material changes
36-nm interconnect pitch, quad patterning to enable further generations of MOSFET scal-
techniques, and a 6-T SRAM bitcell area of ing. The MOSFET implemented with stacks of
0.0312 mm2. This technology also introduces multiple horizontal nanowires (see Figure 11b)
some important density-improvement tech- is one option that, due to its superior electro-
niques: single dummy gates adjacent to logic statics, could enable further gate-length scaling
cells and the ability to make transistor gate con- beyond what the FinFET (see Figure 11a) can
nections directly over active gates. Again, this achieve. MOSFETs with III-V semiconductor
technology took more than two years to develop channel materials are a promising option for real-
and get ready for volume manufacturing due izing a higher-mobility channel than silicon (see
to increased process complexity and mask Figure 12). This higher mobility can be used
count, but it also delivers better-than-normal either to provide higher drive current and higher
area scaling. The innovative features on this performance or to allow the MOSFET to be
technology deliver about 0.37 times logic area operated at lower voltage for lower active power.8
scaling compared to the previous 14-nm gen- Lowering the supply voltage of CMOS
eration. As Figure 8 shows, Intel’s 14-nm and logic below about 0.5 V leads to a dilemma
10-nm generations each took more than two between logic having high performance and
years to develop, but they also took bigger steps high static leakage current versus logic with
in terms of scaling logic area. As a result, Intel lower performance and low leakage current.
logic technologies continue to deliver improved This is due to the choice of MOSFET thresh-
area scaling at the rate of about 0.5 times every old voltage and its electron “thermal tail” deter-
two years. mined sub-threshold gate voltage swing of
It’s apparent that after more than 50 years 60 mV/decade. One alternative transistor option
we’re continuing to scale transistor area, but are that operates differently than a MOSFET (and
we delivering the other promises of Moore’s law as such could be classified as a beyond-CMOS
and Dennard’s scaling methodology: lower cost device) is the Tunneling Field Effect Transistor
per transistor, higher performance, and lower (TFET).9 The TFET can achieve subthresh-
active power? Figure 9a shows how Intel logic old swing smaller than 60 mV/decade (that

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 mm2/transistor $/mm2 $/transistor
(normalized) (normalized) (normalized)
Log scale

Log scale

Log scale
45 nm

32 nm

22 nm

7 nm
10 nm
14 nm

45 nm

45 nm
32 nm

32 nm
22 nm

22 nm
7 nm

7 nm
10 nm

10 nm
14 nm

14 nm
(a) (b) (c)
Figure 9. Trends for improving logic transistor area and cost per transistor. (a) Area per transistor. (b) Wafer cost. (c) Cost per
transistor.

32 nm
22 nm
14+ 14++
Transistor performance (log scale)

Dynamic capacitance (log scale)

Performance per W (log scale)

14 nm 10++
10++
10+ 10++ 10+

Higher 10 nm Better 10 nm
performance 14++ 10+ performance/W 14++
Lower
14+
14+ power
10 nm
14 nm

14 nm
22 nm
22 nm
32 nm 32 nm
2009 2011 2013 2015 2017 2019 2021 2009 2011 2013 2015 2017 2019 2021 2009 2011 2013 2015 2017 2019 2021
(a) (b) (c)
Figure 10. Trends for improving transistor performance and reducing active power. (a) Transistor performance. (b) Dynamic
capacitance. (c) Performance per watt.

is, steeper current turn-on) and can therefore research efforts are exploring logic technologies
operate at a lower power supply voltage than a going beyond CMOS,10 with an objective to
MOSFET. Figure 13 shows drain current ver- complement CMOS rather than to replace it.
sus gate voltage simulation results for nanowire The goal of Beyond-CMOS research is to iden-
TFETs implemented with different III-V semi- tify and enable an integrated circuit technology
conductor materials. that will be more energy efficient than CMOS.
While the success of information technol- If this happens, it will support the continuation
ogy progress in the past 50 years was based on of Moore’s law.
Moore’s law1,2 scaling and mostly one underlying Beyond-CMOS research efforts have been
technology—CMOS transistors—present-day underway for 10 years, being funded in the US

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 Ultra-Low-Power Processors

Drain Drain
Gate Gate

Source Source

Oxide Oxide

Silicon Silicon
substrate substrate

(a) (b)
Figure 11. Comparison of transistor structures. (a) FinFET transistor. (b) Nanowire transistor.

1.0E-05
VDS=0.5V, VG Swing = 0.5V
105
InSb In0.7Ga0.3AS,
12Å EOT, 1.6XREXT
InGaAs
Electron mobility (cm2/Vs)

1.0E-06 Planar Si,

104 8Å EOT, REXT
IOFF (A/µm)

>30X
improvement 1.0E-07 +80%
103 +55%

Simulated:
Si In0.7Ga0.3AS,
8Å EOT, REXT
102 1.0E-08
5x1011 1012 1013 2x1013 0.2 0.3 0.4 0.5 0.6 0.7
(a) Sheet carrier density (cm-2) (b) ION (mA/µm)

Figure 12. Comparison of III-V and silicon transistor electrical characteristics. (a) Electron mobility
versus carrier density. (b) Off-current versus on-current.

S D InAs NMOSFET
Over GaSb/InAs Si NMOS~PMOS
Ef the 1.E+02 TFET
G Ef
S D barrier N-
Vg P-
1.E+01 GeSn Het-j
MOSFET N++ N++
N and P-TFET
ID (uA/um)

Filled 1.E+00
states
dec

Solid lines: N-TFET

1.E-01
c

Dashed lines: P-TFET

mV/

de
V/

S D
m

Filters 5nm-NW
<40

1.E-02
63

Fermi tail
G Vds =0.3V
S D Ef Through Ioff =0.1nA/um
Ef the 1.E-03
TFET P++ N++
barrier
Filled Vg 1.E-04
states 0.0 0.1 0.2 0.3 0.4 0.5
Vg (V)
(a) (b)
Figure 13. Comparison of Tunneling FET and MOSFET transistors. (a) Transistor structures and channel current modulation
techniques. (b) Drive current versus gate voltage electrical characteristics.

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 104 Co HP CMOS High-performance CMOS
n ASL LV CMOS Low-voltage CMOS
sta CSL
ntE
ne VdWFET Van der Waals FET
rgy
*D STO HomJTFET Homojunction III-V TFET
103 ela
y HetJTFET Heterojunction III-V TFET
GnrTFET Graphene nanoribbon TFET
SpinFET FEFET ThinFET 2D hetero interlayer TFET
HP CMOS
Energy (fJ)

GaNFET GaN TFET

GpnJ NML TMDTFET Trans metal dichalchogenide
102 NCFET
VdWFET GpnJ Graphene pn junction
LV CMOS STT/DW
HetJTFET TMDTFET FEFET Ferroelectric FET
GnrTFET NCFET Negative capacitance FET
101 ThinFET SWD
HomJTFET SMG SpinFET Spin FET
GaNTFET
ASL All spin logic
CSL Charge spin logic
STT/DW Spin torque domain wall
100 SMG Spin majority gate
102 103 104 105 106 STO Spin torque oscillator
SWD Spin wave device
Delay (ps)
NML Nanomagnetic logic

Figure 14. Simulated switching energy and delay for a 32-bit arithmetic logic unit circuit for CMOS
and for various beyond-CMOS device options.

in large part via the Semiconductor Research implement computing technologies. It enabled
Corporation (SRC).11 The expectation of this the setting of expectations for power and perfor-
industry–university research consortium 10 years mance and revealed some pathways for improve-
ago was that this field would produce a comput- ment. Experimental demonstrations have not
ing technology that is better than CMOS for the yet achieved the theoretical modeling projections
majority of its applications. Reality showed that, put forward in the benchmarking. One reason is
among many impressive proposals and demon- that each computing technology requires solving
strations, none of them beat CMOS. However, numerous fabrication challenges.14
they do possess many valuable features, such as The various materials implementations of the
low-power operation and non-volatility. Thus, TFET (see Figure 13) have shown that they have
the current vision is that beyond-CMOS circuits improved energy-delay product (and therefore
will replace CMOS in some critically important power and performance) over the future CMOS
computation or information processing applica- technology node that they are benchmarked
tions. They would be monolithically integrated against (see Figure 14): the International Tech-
with CMOS on the same chip or packaged nology Roadmap for Semiconductors prediction in
together in a multichip module. 2011 of the 2018 CMOS node. With a poten-
Another expectation was that beyond- tial three-times improvement in energy-delay
CMOS circuits would not require any product over CMOS, this is starting to be an
MOSFETs as part of their operation and could interesting device option, and it does not require
maybe even eliminate any charge currents in the a drastic change in circuit design for logic while
quest for energy efficiency. This did not come it offers some additional circuit functionality.
true: a thorough circuit analysis reveals that a The spintronic devices in Figure 14 oper-
MOSFET transistor is needed to supply power ate with a wide range of switching energy and
and for clocking and control of the logic cir- at slower switching speed compared to CMOS.
cuit operation. However, this does not preclude The spintronic devices that match the best
pursuing the key direction of beyond-CMOS CMOS switching energy use magnetoelectric
research, which is to discover and invent com- materials to do the switching of nanomagnets.
putation that can operate at significantly lower Although they are slower than CMOS, they
supply voltages than CMOS to enable dramatic have the added benefit of being non-volatile.
improvements in energy efficiency. Non-volatility in the logic device has the
To this end, beyond-CMOS benchmark- potential to provide energy efficiency benefits
ing12,13 (see Figure 14) was helpful in evaluating by taking advantage of it in the computing
the potential of various materials and devices to microarchitecture.

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 Ultra-Low-Power Processors

A historic similarity for beyond-CMOS References

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 J. Nanoparticle Research, vol. 10, 2008, CMOS Computing,” to be published in
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Devices and Circuits, vol. 1, 2015, pp. 3–11.
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Technical Digest, 2015, p. 32.5.1–32.5.4. research interests include novel embedded
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CMOS,” Proc. 43rd ACM/IEEE Design nanomagnetic devices for energy-efficient inte-
Automation Conf., 2006, pp. 807–808. grated circuits beyond-CMOS. Young received
16. I.A. Young and D.E. Nikonov, “Prin- a PhD in electrical engineering from the Uni-
cipals and Trends in Quantum Nano- versity of California at Berkeley. Contact him at
Electronics and Nano-Magnetics for Beyond [email protected].

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Neumann, IEEE Annals of the History of
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