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VLSI Physical Design - Model Questions

The document outlines various questions related to VLSI design, covering topics such as partitioning algorithms, floorplanning, routing, VLSI simulation, and high-level synthesis. It includes both 5-mark and 15-mark questions, requiring discussions, demonstrations, and pseudocode for different algorithms and techniques. The questions aim to assess understanding of concepts like Min-cut algorithm, simulated annealing, FPGA architecture, and low-power design considerations.

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Amit Das
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41 views3 pages

VLSI Physical Design - Model Questions

The document outlines various questions related to VLSI design, covering topics such as partitioning algorithms, floorplanning, routing, VLSI simulation, and high-level synthesis. It includes both 5-mark and 15-mark questions, requiring discussions, demonstrations, and pseudocode for different algorithms and techniques. The questions aim to assess understanding of concepts like Min-cut algorithm, simulated annealing, FPGA architecture, and low-power design considerations.

Uploaded by

Amit Das
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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5 Marks Questions:

Module: 2: Compaction, Partioning & Placement


1. What are different classes of partitioning algorithms. Discuss random selection based
partitioning algorithm. [5]
2. Discuss about the cluster growth technique in partitioning. [5]
3. What is Purturb function and what are its constraints? (Placement) [5]
4. Write the Pseudocode for Cluster Growth Technique in partitioning [5]
5. A circuit has one gate four I/O pads. The 4 pads are placed at 4 corners of a 3x3 grid.
Wvdd=8, Wout=10, Win=3 & Wgnd=3. Find the zero-force target location of the gate
inside the grid. (placemet)
-----------------------------------------
Module: 3: Floorplanning & Routing
6. Discuss the slicing and non-slicing floorplanning with necessary diagrams and Polish
expression. [5]
7. How does a floorplan can be represented by Polar graph? [5]
8. How the Hierarchical top-down approach is used to solve global routing problem?
9. How the Hierarchical bottom-up approach is used to solve global routing problem?
10. Define the problem statement of detailed routing. What is horizontal constrain and
vertical constraint graph?

Module: 1: Introduction
1. Discuss different design styles in VLSI physical design.
2. State and explains briefly the different steps of VLSI design cycle.
3. Draw and explain the architecture of an FPGA?
4. Draw the structure of SRAM-based FPGA

Module: 4: VLSI Simulation


1. What are the considerations for low-power gate level design? What are various
approaches used for it?
2. Demonstrate how the signal probabilities of 2 inputs basic logic gates are measured?
3. Demonstrate the Phase assignment approach for gate level modelling.

Module: 5: High level synthesis


1. What do you mean by High level synthesis (HLS) and what are its steps? [5]
2. Demonstrate the preprocessing stage of High level synthesis (HLS) with an example.
3. Demonstrate the scheduling stage of High level synthesis (HLS) with an example.

======================================================
15 Marks Questions:

Module: 2: Compaction, Partioning & Placement

1. What do you mean by Min-cut algorithm? Explain Karnighan-Lin algorithm in this


context. What are the drawbacks of K-L algorithm? Explain the extension of the K-L
algorithm. [1+6+2+6=15]
2. Mention different classes of Placement algorithms. State the features of Simulated
Annealing algorithm. Write the Pseudocode of Simulated Annealing. Briefly explain
Timberwolf Algorithm. [2+4+5+4]
3. What is the phylosophy behind Force directed placement algorithm and how it is
analohgus to Hook’s law? Discuss the heuristic of Force directed algorithm for
constructive placement. [8+7]
4. Discuss about the partitioning-based placement algorithms. [15]
5. Discuss about one simulated based placement algorithm. (Force directed) [15]
------------------------------------------------------
Module: 3: Floorplanning & Routing

6. Discuss about the Simulated annealing optimization in Floorplaning problem [15]


7. Discuss about the Left edge algorithm and the extension of LEA for channel routing.[15]
8. Discuss about the Dual graph-based approach in floorplanning and its drawbacks. Explain
the Top-down Hierarchical approach for floorplanning. [8+7=15]
9. Demonstrate the graph models are used in solving global routing problems. [15]
10. Thoroughly discuss about the Net merge channel router. [15]
--------------------------------------------
Module: 1: Introduction

11. What do you mean by graph traversal? Explain with an example the difference between
Breadth first and Depth first search algorithms. Explain the adjacency matix and
adjacency list with examples to represent a graph. [2+8+5=15]
12. Explain FPGA architecture and its applications. Demonstrate the FPGA based design
workflow. Compare the FPGA with other technologies in the context of VLSI physical
design. [5+5+5=15]
13. Discuss the computational complexity of any algorithm and what the aymptotic notations
are used to define it? Give two examples to show that how the algorithmic approach can
reduce the complexity? [7+8]
14. Discuss Dijkstra's Shortest-path Algorithm. Ilustrate Prim's Algorithmfor Minimum
Spanning Trees. [7+8=15]
-------------------------------------
Module: 4: VLSI Simulation

15. Explain the Technology mapping approach for gate level modelling. Explain how the pin
swapping of any gate can minimize the power dissipation of a system? [8+7]
16. Discuss the following approaches in the context of low-power gate modelling: (a) Phase
assignment (b) Glitching power handling (c) Clock gating.
17. What are the steps for logic synthesis? Explain logic translation, optimization and
technology mapping for logic synthesis.
----------------------------------------
Module: 5: High level synthesis

18. Explain thoroughly the different steps of High level synthesis of a second order
differential equation solver.
19. Discuss the ASAP and ALAP algorithms of scheduling and analyse their performance.
20. Demonstrate Integer linear programming for constraint scheduling. Demonstrate List
scheduling algorithm for constraint scheduling. [8+7]

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