Scribd
Upload
2 views26 pages

Micro Session3 Done

The document provides an overview of microcontroller operations, focusing on indirect addressing, data move instructions, and the status register. It explains how indirect addressing works with File Select Registers (FSR) and details the effects of various arithmetic and logic operations on the status flags. Additionally, it includes multiple examples demonstrating the impact of these operations on the STATUS register's bits.

Uploaded by

georgesatieh4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
2 views26 pages

Micro Session3 Done

The document provides an overview of microcontroller operations, focusing on indirect addressing, data move instructions, and the status register. It explains how indirect addressing works with File Select Registers (FSR) and details the effects of various arithmetic and logic operations on the status flags. Additionally, it includes multiple examples demonstrating the impact of these operations on the STATUS register's bits.

Uploaded by

georgesatieh4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 26

Microcontrollers

Clara Zaiter
[email protected]

ULFG2 Sem 7 - 2024


Outline
• Indirect addressing (not covered in previous session)
• Data Move instructions
• Operations on WREG and Register f
• Operations on WREG and literal k
• Status Register bits
• Effect of instructions on STATUS register through examples
Indirect addressing
When using indirect addressing, the programmer makes a roundabout reference to
the address via the File Select Register (FSR)

• INDF0 means INDirect addressing via FSR0

• FSR0, which is a 16-bit register (FSR0 = FSR0H:FSR0L), is hence employed to store the 12-bit
address of a register.

• We have 3 of these pointers: FSR0, FSR1 and FSR2.


Indirect addressing
• Indirect addressing in PIC18 processors allows pointer arithmetic within the same
instruction and without incurring additional instruction cycles.
Indirect addressing
Indirect addressing
This powerful instruction moves the contents of the register pointed to by FSR0 to the register ad-
dressed by FSR1

To load a pointer with a certain address, the load fsr (lfsr) instruction is used
Data Move instructions
Operations on WREG and Register f
Example
Operations on WREG and Literal K
Truth tables
Status Register
This register reflects the status of the ALU after an arithmetic or a logical operation
is executed.

➢Arithmetic instructions perform addition, subtraction, multiplication, negation,


increment, etc.

➢Logic operations are responsible for OR, XOR, AND, 1’s complement, etc.
Status Register bits
➢Zero bit Z
▪ This flag is set if the 8-bit result of an arithmetic or logic operation is zero; otherwise, it is
cleared.

➢Carry bit C
▪ This flag is set by the ALU when the result of an addition operation (i.e. addwf or addlw) is greater than 255;
if not, the C bit is cleared.

▪ In the context of subtract operations (subwf and sublw), this flag is also called BORROW (active low).

▪ The carry bit is also affected by rotate-through-carry instructions (rrcf and rlcf). When an 8-bit register is
rotated the carry bit is fed into one end of the register and the bit that is shifted out at the opposite end goes
into the carry.
Status Register bits
➢Negate bit N
▪ This flag is set to point out that the result of the instruction is negative (most significant bit of
the result is set); otherwise, it is cleared.

➢Digit Carry bit DC


▪ This flag is set is set when an add operation generates a carry-out from bit 3 to bit 4 in the addition.

➢Overflow bit OV
▪ This flag is set when the addition of two 8-bit binary numbers of the same sign generates a result of the
opposite sign; otherwise, OV is cleared.
Effect of arithmetic/logic instructions on the STATUS register
Example 1:

Initial Value: RegA = 0x02

movlw 0xFE
addwf RegA, W

=> Loads 0xFE into WREG, adds WREG to RegA, and stores the result in WREG.

Result: WREG = 0x00, RegA = 0x02


Status Flags: (N, OV, Z, DC, C) = (0, 0, 1, 1, 1)
Effect of arithmetic/logic instructions on the STATUS register
Example 2:

Initial Value: RegA = 0xA0

movlw 0x0F
andwf RegA, F

=> Loads 0x0F into WREG, performs a bitwise AND with RegA, and stores the result
in RegA.

Result: WREG = 0x0F, RegA = 0x00


Status Flags: (N, OV, Z, DC, C) = (0, x, 1, x, x)
Effect of arithmetic/logic instructions on the STATUS register
Example 3:

Initial Value: RegA = 0xFF

comf RegA, F

=> Complements all bits in RegA (bitwise NOT) and stores the result back in RegA.

Result: RegA = 0x00


Status Flags: (N, OV, Z, DC, C) = (0, x, 1, x, x)
Effect of arithmetic/logic instructions on the STATUS register
Example 4:

movlw 6
sublw 5

=> Loads 0x06 into WREG and subtracts WREG from 5, with the result stored in
WREG.

Result: WREG = 0xFF


Status Flags: (N, OV, Z, DC, C) = (1, 0, 0, 0, 0)
Effect of arithmetic/logic instructions on the STATUS register
Example 5:

Initial Value: RegA = 0x01

decf RegA, F

=> Decrements RegA by 1 and stores the result back in RegA.

Result: RegA = 0x00


Status Flags: (N, OV, Z, DC, C) = (0,0,1,1,1)
Effect of arithmetic/logic instructions on the STATUS register
Example 6:

Initial Value: RegA = 0xFF

incf RegA, W

=> Increments RegA by 1 and stores the result in WREG.

Result: WREG = 0x00, RegA = 0xFF


Status Flags: (N, OV, Z, DC, C) = (0, 0, 1, 1, 1)
Effect of arithmetic/logic instructions on the STATUS register
Example 7:

Initial Value: RegA = 0xD1

bcf STATUS, C
rlcf RegA, W

 Clears the Carry bit, then rotates RegA to the left, with the result stored in
WREG.

Result: WREG = 0xA2, RegA = 0xD1


Status Flags: (N, OV, Z, DC, C) = (1, x, 0, x, 1)
Effect of arithmetic/logic instructions on the STATUS register
Example 8:

Initial Value: RegA = 0xC4

bcf STATUS, C
rlncf RegA, F

 Clears the Carry bit, then rotates RegA to the left without carry, with the result
stored back in RegA.

Result: WREG = 0xC4, RegA = 0x89


Status Flags: (N, OV, Z, DC, C) = (1, x, 0, x, x)
Effect of arithmetic/logic instructions on the STATUS register
Example 9:

Initial Value: RegA = 0xCA

movlw 0x0F
xorwf RegA, W

 Loads 0x0F into WREG, performs a bitwise XOR with RegA, and stores the result
in WREG.

Result: WREG = 0xC5, RegA = 0xCA


Status Flags: (N, OV, Z, DC, C) = (1, x, 0, x, x)
Effect of arithmetic/logic instructions on the STATUS register
Example 10:

Initial Value: RegA = 0xAB

movlw 0x55
iorwf RegA, W

 Loads 0x55 into WREG, performs a bitwise OR with RegA, and stores the result in
WREG.

Result: WREG = 0xFF, RegA = 0xAB


Status Flags: (N, OV, Z, DC, C) = (1, x, 0, x, x)
Effect of arithmetic/logic instructions on the STATUS register
Example 11:

Initial Value: RegA = 0x01, RegB = 0xCA

setf RegA
movff RegA, RegB
negf RegA

 Sets all bits of RegA (making it 0xFF), moves RegA to RegB, then negates RegA (2’s
complement).

Result: RegA = 0x01, RegB = 0xFF


Status Flags: (N, OV, Z, DC, C) = (0, 0, 0, 0, 0)
Effect of arithmetic/logic instructions on the STATUS register
Example 12:

Initial Value: RegA = 0xC3

movlw B'11000011’
setf RegA
comf RegA, F

 Loads binary 11000011 into WREG, sets all bits in RegA to 1 and complements RegA.

Result: WREG = 0xC3, RegA = 0x00


Status Flags: (N, OV, Z, DC, C) = (0, x, 1, x, x)

You might also like