VHDL CODE FOR MULTIPLEXER WITH BEHAVIORAL-MODEL DESIGN

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX_4X1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 down to 0);
Y : out STD_LOGIC
);
end MUX_4X1;
architecture MUX_BEH of MUX_4X1 is
begin

PROCESS(A,B,C,D,S)
BEGIN
CASE S IS
WHEN "00" => Y<= A;
WHEN "01" => Y<= B;
WHEN "10" => Y<= C;
WHEN "11" => Y<= D;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
end MUX_BEH;
--1-bit comparator using behavioral style.
entity comp is
port ( a: in bit_vector(0 to 1);e: out bit_vector(2 downto 0));
end entity;

architecture comp_beha of comp is

begin
process(a)
variable temp : bit;
begin
case a is
when "00" => e <="100";

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 when "01" => e <="010";
when "10" => e <="001";
when "11" => e <="100";
when others => null;
end case;
end process;
end architecture;

--4-bit comparator using behavioral style model.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity \4_comp\ is
port(
a : in STD_LOGIC_VECTOR(0 to 3);
b : in STD_LOGIC_VECTOR(0 to 3);
agtb : out STD_LOGIC;
altb : out STD_LOGIC;
aeqb : out STD_LOGIC
);
end \4_comp\;
architecture \4_comp_beh\ of \4_comp\ is
begin
process(a,b)
begin
if(a>b) then
agtb<= '1';
aeqb<='0';
altb<= '0';
elsif(a<b) then
agtb<= '0';
aeqb<='0';
altb<= '1';
elsif(a=b)then
agtb<= '0';
aeqb<='1';
altb<= '0';
end if;

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 end process;
end \4_comp_beh\;
--vhdl code for halfadder using Behavioral style model.
entity ha is
port( a, b: in bit; sum,carry: out bit);
end entity;
architecture ha1 of ha is
begin
process (a,b)
begin
if (a ='0' and b='0') then
sum <= '0';
carry<='0';
elsif( a='0' and b='1')then
sum<= '1';
carry<='0';
elsif( a='1' and b='0')then
sum<= '1';
carry<='0';
elsif( a='1' and b='1')then
sum<= '0';
carry<='1';
end if;
end process;
end architecture;

--vhdl code for half subtractor using Behavioral style model.

entity ha is
port( a, b: in bit; sum,borrow: out bit);
end entity;
architecture ha1 of ha is
begin
process (a,b)
begin
if (a ='0' and b='0') then
sum <= '0';
borrow<='0';
elsif( a='0' and b='1')then
sum<= '1';
borrow<='1';

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 elsif( a='1' and b='0')then
sum<= '1';
borrow<='0';
elsif( a='1' and b='1')then
sum<= '0';
borrow<='0';
end if;
end process;
end architecture;

--vhdl code for full-adder using Behavioral style model.

entity fa is
port( a, b: in bit;carry: inout bit; sum: out bit);
end entity;
architecture fa1 of fa is
begin
process (a,b,carry)
begin
if (a ='0' and b='0'and carry='0') then
sum <= '0';
carry<='0';
elsif(a ='0' and b='1'and carry='0') then
sum <= '1';
carry<='0';
elsif( a='1' and b='0'and carry = '0')then
sum <= '1';
carry <='0';
elsif( a='1' and b='1'and carry= '0')then
sum <= '0';
carry <='1';
elsif( a='0' and b='0'and carry= '1')then
sum <= '1';
carry <='0';
elsif( a='0' and b='1'and carry= '1')then
sum <= '0';
carry <='1';
elsif( a='1' and b='0'and carry= '1')then
sum <= '0';
carry <='1';
elsif( a='1' and b='1'and carry= '1')then

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 sum <= '1';
carry <='1';
end if;
end process;
end architecture;
--vhdl code for B2G code converter using behavioral model.
entity b2g is
port(
b : in STD_LOGIC_VECTOR(3 downto 0);
g : out STD_LOGIC_VECTOR(3 downto 0)
);
end b2g;

architecture b2g_beh of b2g is

begin
process (b)
begin
case b is
when "0000"=> g<="0000";
when "0001"=> g<="0001";
when "0010"=> g<="0011";
when "0011"=> g<="0010";
when "0100"=> g<="0110";
when "0101"=> g<="0111";
when "0110"=> g<="0101";
when "0111"=> g<="0100";
when "1000"=> g<="1100";
when "1001"=> g<="1101";
when "1010"=> g<="1111";
when "1011"=> g<="1110";
when "1100"=> g<="1010";
when "1101"=> g<="1011";
when "1110"=> g<="1001";
when "1111"=> g<="1000";
when others=> null;
end case;
end process;
end b2g_beh;

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--vhdl code for G2B code converter using behavioral model.
entity g2b is
port(
g : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end g2b;

architecture g2b_beh of g2b is

begin
process (g)
begin
case b is
when "0000"=> b<="0000";
when "0001"=> b<="0001";
when "0011"=> b<="0010";
when "0010"=> b<="0011";
when "0110"=> b<="0100";
when "0111"=> b<="0101";
when "0101"=> b<="0110";
when "0100"=> b<="0111";
when "1100"=> b<="1000";
when "1101"=> b<="1001";
when "1111"=> b<="1010";
when "1110"=> b<="1011";
when "1010"=> b<="1100";
when "1011"=> b<="1101";
when "1001"=> b<="1110";
when "1000"=> b<="1111";
when others=> null;
end case;
end process;
end g2b_beh;

--vhdl code for Bcd2 7-segment code converter using behavioral model.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

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entity bcd_seven is
port(
bcd : in STD_LOGIC_VECTOR(3 downto 0);
segment : out STD_LOGIC_VECTOR(6 downto 0)
);
end bcd_seven;

architecture bcd_beh of bcd_seven is

begin
process(bcd)
begin
case bcd is
when "0000"=>segment<="1111110";
when "0001"=>segment<="0110000";
when "0010"=>segment<="1101101";
when "0011"=>segment<="1111001";
when "0100"=>segment<="0110011";
when "0101"=>segment<="1011011";
when "0110"=>segment<="0011111";
when "0111"=>segment<="1110000";
when "1000"=>segment<="1111111";
when "1001"=>segment<="1110011";
when others => null;
end case;
end process;
end bcd_beh;

--vhdl code for Bcd-2-excess3 code converter using behavioral model.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity bcd_excess is
port(
b : in STD_LOGIC_VECTOR(3 downto 0);
excess3 : out STD_LOGIC_VECTOR(3 downto 0)
);
end bcd_excess;

architecture bcd_excess_beh of bcd_excess is

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begin
process (b)
begin
case b is
when "0000"=>excess3<="0011";
when "0001"=>excess3<="0100";
when "0010"=>excess3<="0101";
when "0011"=>excess3<="011";
when "0100"=>excess3<="0111";
when "0101"=>excess3<="1000";
when "0110"=>excess3<="1001";
when "0111"=>excess3<="1010";
when "1000"=>excess3<="1011";
when "1001"=>excess3<="1100";
when "1010"=>excess3<="1110";
when others => null;
end case;
end process;

end bcd_excess_beh;

--VHDL Code for decoder 2X4 using behavioral model.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(
en : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
z : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder;
architecture decoder_beh of decoder is
begin
process(s0,s1,en)
variable s0bar,s1bar: std_logic;
begin
s0bar:= not s0;
s1bar:= not s1;
if (en='1')then

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 z(3)<= s0bar and s1bar;
z(2)<=s0bar and s1;
z(1)<= s0 and s1bar;
z(0)<= s0 and s1;
else
z<="0000";
end if;
end process;

end decoder_beh;
--VHDL Code for encoder 8X3 using behavioral model.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder is
port(
d : in STD_LOGIC_VECTOR(0 to 7);
a : out STD_LOGIC_vector(0 to 2 )
);
end encoder;

architecture encoder_beh of encoder is

begin
process (d)
begin
case d is
when "10000000"=> a<= "000";
when "01000000"=> a<="001";
when "00100000"=> a<="010";
when "00010000"=> a<="011";
when "00001000"=> a<="100";
when "00000100"=> a<="101";
when "00000010"=> a<="110";
when "00000001"=> a<="111";
when others => null;
end case;
end process;

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end encoder_beh;

--VHDL Code for parity generator using behavioral model.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parity is
port(
d : in STD_LOGIC_VECTOR(3 downto 0);
par_even : out STD_LOGIC;
par_odd : out STD_LOGIC);
end parity;
architecture parity of parity is
begin
p1:process(d)
begin
case d is
when "0000"=> par_even<='0';par_odd<='1';
when "0001"=> par_even<='1'; par_odd<='0';
when "0010"=> par_even<='1'; par_odd<='0';
when "0011"=> par_even<='0'; par_odd<='1';
when "0100"=> par_even<='1'; par_odd<='0';
when "0101"=> par_even<='0'; par_odd<='1';
when "0110"=> par_even<='0'; par_odd<='1';
when "0111"=> par_even<='1'; par_odd<='0';
when "1000"=> par_even<='1'; par_odd<='0';
when "1001"=> par_even<='0'; par_odd<='1';
when "1010"=> par_even<='0'; par_odd<='1';
when "1011"=> par_even<='1'; par_odd<='0';
when "1100"=> par_even<='0'; par_odd<='1';
when "1101"=> par_even<='1'; par_odd<='0';
when "1110"=> par_even<='1'; par_odd<='0';
when "1111"=> par_even<='0'; par_odd<='1';
when others=> null;
end case;
end process;

end parity;

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