Digital Design &

Computer Architecture
Sarah Harris & David Harris

Chapter 2:
Combinational Logic
Design
Modified by Younghwan Yoo, 2023
Chapter 2 :: Topics
• Combinational Circuits
• Boolean Equations
• Boolean Algebra
• From Logic to Gates
• X’s and Z’s, Oh My
• Karnaugh Maps
• Combinational Building Blocks
• Timing

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 Chapter 2: Combinational Logic

Combinational Circuits
Introduction
A logic circuit is composed of:
• Inputs
• Outputs
• Functional specification
• Timing specification

functional spec
inputs outputs
timing spec

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Circuits
• Nodes
– Inputs: A, B, C
– Outputs: Y, Z A E1
n1

– Internal: n1 B E3 Y

• Circuit elements C E2 Z

– E1, E2, E3
– Each itself a circuit

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Types of Logic Circuits
• Combinational logic
– Memoryless
– Outputs determined by current values of inputs
• Sequential logic
– Has memory
– Outputs determined by previous and current values
of inputs

functional spec
inputs outputs
timing spec

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Rules of Combinational Composition
• Every element is combinational
• Every node is either an input or connects
to exactly one output
• The circuit contains no cyclic paths
• Example:

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Chapter 2: Combinational Logic

Boolean Equations
Boolean Equations
• Functional specification of outputs in terms
of inputs
• Example: S = F(A, B, Cin)
Cout = F(A, B, Cin)

A
C S
B L
Cout
Cin
S = A  B  Cin
Cout = AB + ACin + BCin

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Some Definitions
• Complement: variable with a bar over it
A, B, C
• Literal: variable or its complement
A, A, B, B, C, C
• Implicant: product of literals
ABC, AC, BC
• Minterm: product that includes all input variables
ABC, ABC, ABC
• Maxterm: sum that includes all input variables
(A+B+C), (A+B+C), (A+B+C)

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Sum-of-Products (SOP) Form
• All Boolean equations can be written in SOP form
• Each row has a minterm
• A minterm is a product (AND) of literals
• Each minterm is TRUE for that row (and only that row)
• Form function by ORing minterms where output is 1
• Thus, a sum (OR) of products (AND terms)
minterm
A B Y minterm name
0 0 0 A B m0
0 1 1 A B m1
1 0 0 A B m2
1 1 1 A B m3
Y = F(A, B) =

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Sum-of-Products (SOP) Form
• All Boolean equations can be written in SOP form
• Each row has a minterm
• A minterm is a product (AND) of literals
• Each minterm is TRUE for that row (and only that row)
• Form function by ORing minterms where output is 1
• Thus, a sum (OR) of products (AND terms)
minterm
A B Y minterm name
0 0 0 A B m0
0 1 1 A B m1
1 0 0 A B m2
1 1 1 A B m3
Y = F(A, B) = AB + AB = Σ(m1, m3) = Σ(1, 3)
Long-hand Short-hand
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Product-of-Sums (POS) Form
• All Boolean equations can be written in POS form
• Each row has a maxterm
• A maxterm is a sum (OR) of literals
• Each maxterm is FALSE for that row (and only that row)
• Form function by ANDing maxterms where output is 0
• Thus, a product (AND) of sums (OR terms)
maxterm
A B Y maxterm name
0 0 0 A + B M0
0 1 1 A + B M1
1 0 0 A + B M2
1 1 1 A + B M3
Y = F(A, B) = (A + B)●(A + B) = Π(0, 2)
Long-hand Short-hand
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Boolean Equations Example
• You are going to the cafeteria for lunch
– You won’t eat lunch (E = 0)
• If it’s not clean (C = 0) or
• If they only serve meatloaf (M = 1)
• Write a truth table for determining if you
will eat lunch (E).
C M E
0 0 0
0 1 0
1 0 1
1 1 0

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SOP & POS Form
SOP – sum-of-products
C M E minterm
0 0 0 C M
0 1 0 C M
1 0 1 C M
1 1 0 C M

POS – product-of-sums
C M E maxterm
0 0 0 C + M
0 1 0 C + M
1 0 1 C + M
1 1 0 C + M

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SOP & POS Form
SOP – sum-of-products
C M E minterm
0 0 0 C M
0 1 0 C M E = CM
1 0 1 C M = Σ(2)
1 1 0 C M

POS – product-of-sums
C M E maxterm
0 0 0 C + M
0 1 0 C + M E = (C + M)(C + M)(C + M)
1 0 1 C + M = Π(0, 1, 3)
1 1 0 C + M

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Forming Boolean Expressions
Example 1:
We will go to the Park (P is the output) if it’s not
Raining (R) and we have Sandwiches (S).

Boolean Equation:
P = RS

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Forming Boolean Expressions
Example 2:
You will be considered a Winner (W is the output)
if we send you a Million dollars (M) or a small
Notepad (N).
Boolean Equation:
W=M+N

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Forming Boolean Expressions
Example 3:
You can Eat delicious food (E is the output) if you
Make it yourself (M) or you have a personal Chef (C)
and she/he is talented (T) but not eXpensive (X).

Boolean Equation:
E = M + CTX

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Forming Boolean Expressions
Example 4:
You can Enter the building if you have a Hat and
Shoes on or if you have a Hat on.

Boolean Equation:
E = HS + H

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Forming Boolean Expressions
Example 5:
You can Enter the building if you have a Hat and
Shoes on or if you have a Hat and no Shoes on.

Boolean Equation:
E = HS + HS

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Chapter 2: Combinational Logic

Boolean Algebra:
Axioms
Boolean Algebra
• Axioms and theorems to simplify Boolean
equations
• Like regular algebra, but simpler: variables
have only two values (1 or 0)
• Duality in axioms and theorems:
– ANDs and ORs, 0’s and 1’s interchanged

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Boolean Axioms
Number Axiom Name
A1 B = 0 if B ≠ 1 Binary Field
A2 0=1 NOT
A3 0•0=0 AND/OR
A4 1•1=1 AND/OR
A5 0•1=1•0=0 AND/OR

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Boolean Axioms
Number Axiom Dual Name
A1 B = 0 if B ≠ 1 B = 1 if B ≠ 0 Binary Field
A2 0=1 1=0 NOT
A3 0•0=0 1+1=1 AND/OR
A4 1•1=1 0+0=0 AND/OR
A5 0•1=1•0=0 1+0=0+1=1 AND/OR

Dual: Replace: • with +

0 with 1
1 with 0
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Chapter 2: Combinational Logic

Boolean Algebra:
Theorems of
One Variable
Boolean Theorems of One Variable
Number Theorem Name
T1 B•1=B Identity
T2 B•0=0 Null Element
T3 B•B=B Idempotency
T4 B=B Involution
T5 B•B=0 Complements

Dual: Replace: • with +

0 with 1
1 with 0
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Boolean Theorems of One Variable
Number Theorem Dual Name
T1 B•1=B B+0=B Identity
T2 B•0=0 B+1=1 Null Element
T3 B•B=B B+B=B Idempotency
T4 B=B Involution
T5 B•B=0 B+B=1 Complements

Dual: Replace: • with +

0 with 1
1 with 0
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T1: Identity Theorem
• B 1=B
• B+0=B

B
1 = B

B
0 = B

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T2: Null Element Theorem
• B 0=0
• B+1=1

B
0 = 0
null
element
B
1 = 1

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T3: Idempotency Theorem
• B B=B
• B+B=B
B
B = B

B
B = B

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T4: Involution Theorem
• B=B

B = B

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T5: Complement Theorem
• B B=0
• B+B=1

B
B = 0

B
B = 1

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Recap: Basic Boolean Theorems
Number Theorem Dual Name
T1 B•1=B B+0=B Identity
T2 B•0=0 B+1=1 Null Element
T3 B•B=B B+B=B Idempotency
T4 B=B Involution
T5 B•B=0 B+B=1 Complements

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Chapter 2: Combinational Logic

Boolean Algebra:
Theorems of
Several Variables
 Boolean Theorems of Several Vars
# Theorem Dual Name
T6 B•C = C•B B+C = C+B Commutativity
T7 (B•C) • D = B • (C•D) (B + C) + D = B + (C + D) Associativity
T8 B • (C + D) = (B•C) + (B•D) B + (C•D) = (B+C)•(B+D) Distributivity
T9 B • (B+C) = B B + (B•C) = B Covering
T10 (B•C) + (B•C) = B (B+C) • (B+C) = B Combining
T11 (B•C) + (B•D) + (C•D) = (B+C) • (B+D) • (C+D) = Consensus
(B•C) + (B•D) (B+C) • (B+D)

Warning: T8’ differs from traditional algebra:

OR (+) distributes over AND (•)

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How to Prove
• Method 1: Perfect induction
• Method 2: Use other theorems and axioms
to simplify the equation
– Make one side of the equation look like
the other

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Proof by Perfect Induction
• Also called: proof by exhaustion
• Check every possible input value
• If the two expressions produce the same
value for every possible input combination,
the expressions are equal

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T9: Covering

Number Theorem Name

T9 B• (B+C) = B Covering

Prove true by:

• Method 1: Perfect induction
• Method 2: Using other theorems and axioms

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T9: Covering

Number Theorem Name

T9 B• (B+C) = B Covering

Method 1: Perfect Induction

B C (B+C) B(B+C)
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1

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T9: Covering

Number Theorem Name

T9 B• (B+C) = B Covering

Method 2: Prove true using other axioms and

theorems.
B•(B+C) = B•B + B•C T8: Distributivity
= B + B•C T3: Idempotency
= B•1 + B•C T1: Identity
= B•(1 + C) T8: Distributivity
= B•(1) T2: Null element
=B T1: Identity
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T10: Combining

Number Theorem Name

T10 (B•C) + (B•C) = B Combining

Prove true using other axioms and theorems:

B•C + B•C = B•(C+C) T8: Distributivity
= B•(1) T5’: Complements
=B T1: Identity

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De Morgan’s Theorem: Dual

# Theorem Dual Name

T12 B•C•D… = B+C+D… B+C+D…= B•C•D… De Morgan’s
Theorem

The complement of the product is the

sum of the complements.

Dual:
The complement of the sum is the
product of the complements.

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 Recap: Theorems of Several Vars
# Theorem Dual Name
T6 B•C = C•B B+C = C+B Commutativity
T7 (B•C) • D = B • (C•D) (B + C) + D = B + (C + D) Associativity
T8 B • (C + D) = (B•C) + (B•D) B + (C•D) = (B+C)•(B+D) Distributivity
T9 B • (B+C) = B B + (B•C) = B Covering
T10 (B•C) + (B•C) = B (B+C) • (B+C) = B Combining
T11 (B•C) + (B•D) + (C•D) = (B+C) • (B+D) • (C+D) = Consensus
(B•C) + (B•D) (B+C) • (B+D)
T12 B•C•D… = B+C+D… B+C+D…= B•C•D… De Morgan’s

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 Chapter 2: Combinational Logic

Boolean Algebra:
Simplifying Equations
Simplifying an Equation
Simplifying may mean minimal sum of products form:
• SOP form that has the fewest number of implicants, where
each implicant has the fewest literals
– Implicant: product of literals
ABC, AC, BC
– Literal: variable or its complement
A, A, B, B, C, C
Simplifying could also mean fewest number of gates, lowest cost,
lowest power, etc. For example, Y = A XOR B is likely simpler than
minimal Sum of Products Y = AB + AB. These depend on details of
the technology.

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Simplifying Boolean Equations
Example 1:
Y = AB + AB Recommended Method

Y=B T10: Combining

A
Y B Y
B
or
Y = B(A + A) T8: Distributivity
= B(1) T5’: Complements
=B T1: Identity
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Simplifying Boolean Equations
Example 2:
Y = ABC + ABC + ABC
= ABC + ABC + ABC + ABC T3’: Idempotency
= (ABC+ABC) + (ABC+ABC) T7’: Associativity
= AC + BC T10: Combining

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 Chapter 2: Combinational Logic

Extra Examples
Boolean Algebra:
Simplifying Equations
Simplification Methods
• Distributivity (T8, T8’) B (C+D) = BC + BD
B + CD = (B+ C)(B+D)

• Covering (T9’) A + AP = A

• Combining (T10) PA + PA = P

• Expansion P = PA + PA
A = A + AP

• Idempotency (duplication) A = A + A

• “Simplification” theorem A + AP = A + P
A + AP = A + P

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Proving the “Simplification” Theorem
“Simplification” theorem
A + AP = A + P
Method 1: A + AP = A + AP + AP T9’ Covering
= A + (AP + AP) T7 Associativity
=A+ P T10 Combining

Method 2: A + AP = (A + A) (A + P) T8’ Distributivity

= 1• (A + P) T5’ Complements
= A+P T1 Identity

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T11: Consensus
Number Theorem Name
T11 (B•C) + (B•D) + (C•D) = Consensus
(B•C) + (B•D)
Prove using other theorems and axioms:
B•C + B•D + C•D
= BC + BD + (CDB+CDB) T10: Combining
= BC + BD + BCD+BCD T6: Commutativity
= BC + BCD + BD + BCD T6: Commutativity
= BC(1 + D) + BD(1 + C) T8: Distributivity
= BC + BD T2': Null Element

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Simplifying Boolean Equations
Example 3:
Y = A(AB + ABC)
= A(AB(1 + C)) T8: Distributivity
= A(AB(1)) T2’: Null Element
= A(AB) T1: Identity
= (AA)B T7: Associativity
= AB T3: Idempotency

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Simplifying Boolean Equations
Example 4:
Y = A’BC + A’ Recall: A’ = A
= A’ T9’ Covering: X + XY = X
or
= A’(BC + 1) T8: Distributivity
= A’(1) T2’: Null Element
= A’ T1: Identity

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Multiplying Out: SOP Form
An expression is in sum-of-products (SOP)
form when all products contain literals
only.
• SOP form: Y = AB + BC’ + DE
• NOT SOP form: Y = DF + E(A’+B)
• SOP form: Z = A + BC + DE’F

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Multiplying Out: SOP Form
Example 5: Recommended Method
Y = (A + C + D + E)(A + B)
Apply T8’ first when possible: W+XZ = (W+X)(W+Z)
Make: X = (C+D+E), Z = B and rewrite equation
Y = (A+X)(A+Z) substitution (X=(C+D+E), Z=B)
= A + XZ T8’: Distributivity
= A + (C+D+E)B substitution
= A + BC + BD + BE T8: Distributivity
or
Y = AA+AB+AC+BC+AD+BD+AE+BE T8: Distributivity
= A+AB+AC+AD+AE+BC+BD+BE T3: Idempotency
=A+ BC+BD+BE T9’: Covering
This method is called multiplying out.
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Simplifying Boolean Equations
Example 6:
Y = AB + BC +B’D’ + AC’D’
Method 1:
Y = AB + BC + B’D’ + (ABC’D’ + AB’C’D’) T10: Combining
= (AB + ABC’D’) + BC + (B’D’ + AB’C’D’) T6: Commutat.
T7: Associativity
= AB + BC + B’D’ T9: Covering
Method 2:
Y = AB + BC + B’D’ + AC’D’ + AD’ T11: Consensus
= AB + BC + B’D’ + AD’ T9: Covering
= AB + BC + B’D’ T11: Consensus

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Literal and implicant ordering
• Variables within an implicant should be in
alphabetical order.
• The order of implicants doesn’t matter.
Examples:
– Correct: Y = AB + BC + BD
– Correct: Y = BC + BD + AB
– Incorrect: Y = CB + BD + BA
– Incorrect: Y = AB + BC + DB

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Simplifying Boolean Equations
Example 7: Recommended Method
Y = (A + BC)(A + DE)
Apply T8’ first when possible: W+XZ = (W+X)(W+Z)
Make: X = BC, Z = DE and rewrite equation
Y = (A+X)(A+Z) substitution (X=BC, Z=DE)
= A + XZ T8’: Distributivity
= A + BCDE substitution
or
Y = AA + ADE + ABC + BCDE T8: Distributivity
= A + ADE + ABC + BCDE T3: Idempotency
= A + ADE + ABC + BCDE
=A + BCDE T9’: Covering
= A + BCDE T9’: Covering

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Review: Canonical SOP & POS Forms
SOP – sum-of-products E = CM
C M E minterm
0 0 0 C M
0 1 0 C M same
1 0 1 C M
1 1 0 C M
POS – product-of-sums E = (C + M)(C + M)(C + M)
C M E maxterm = (C + MM)* (C + M)
0 0 0 C + M = (C + 0)* (C + M)
0 1 0 C + M
= C * (C + M)
1 0 1 C + M
1 1 0 C + M = CC + CM
= 0 + CM
= CM
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Factoring: POS Form
An expression is in product-of-sums (POS)
form when all sums contain literals only.
• POS form: Y = (A+B)(C+D)(E’+F)
• NOT POS form: Y = (D+E)(F’+GH)
• POS form: Z = A(B+C)(D+E’)

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Factoring: POS Form
Example 8:
Y = (A + B’CDE)
Apply T8’ first when possible: W+XZ = (W+X)(W+Z)
Make: X = B’C, Z = DE and rewrite equation
Y = (A+XZ) substitution (X=B’C, Z=DE)
= (A+B’C)(A+DE) T8’: Distributivity
= (A+B’)(A+C)(A+D)(A+E) T8’: Distributivity

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Factoring: POS Form
Example 9:
Y = AB + C’DE + F
Apply T8’ first when possible: W+XZ = (W+X)(W+Z)
Make: W = AB, X = C’, Z = DE and rewrite equation
Y = (W+XZ) + F substitution W = AB, X = C’, Z = DE
= (W+X)(W+Z) + F T8’: Distributivity
= (AB+C’)(AB+DE)+F substitution
= (A+C’)(B+C’)(AB+D)(AB+E)+F T8’: Distributivity
= (A+C’)(B+C’)(A+D)(B+D)(A+E)(B+E)+F T8’: Distributivity
= (A+C’+F)(B+C’+F)(A+D+F)(B+D+F)(A+E+F)(B+E+F) T8’: Distr.

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De Morgan’s Theorem
Example 10:
Y = (A+BD)C
= (A+BD) + C
• Work from the outside in
= (A•(BD)) + C (i.e., top bar, then down)
= (A•(BD)) + C • Use involution when
possible
= ABD + C

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De Morgan’s Theorem
Example 11:
Y = (ACE+D) + B
= (ACE+D) • B
= (ACE•D) • B
= ((AC+E)•D) • B
= ((AC+E)•D) • B
= (ACD + DE) • B
= ABCD + BDE

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Common Errors
• Losing bars (alignment will help you avoid this)
• Losing terms (alignment will help you avoid this)
• Trying to do multiple steps at once – this is prone to errors!
• Applying theorems incorrectly, for example:
• Wrong: ABC + ABC = B Correct: ABC + ABC = AC. Products may
only differ in a single term when using the combining theorem.
• Wrong: (A + A) = 0 Correct: A + A = 1
• Wrong: (A • A) = 1 Correct: A • A = 0
• Wrong: ABC = B Correct: B + ABC = B. In order to use the
covering theorem, you must have a term that covers the other
terms.
• Wrong: 𝐴𝐶 = 𝐴ҧ𝐶ҧ Correct: 𝐴𝐶 = 𝐴ҧ + 𝐶ҧ (De Morgan’s)
• Wrong: 𝐴 + 𝐶 = 𝐴ҧ + 𝐶ҧ Correct: 𝐴 + 𝐶 = 𝐴ҧ𝐶ҧ (De Morgan’s)

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Chapter 2: Combinational Logic

From Logic to Gates

From Logic to Gates
Build the following equation using logic gates:
Y = AB + CDE

A
B
Y
C
D
E

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Circuit Schematics Rules
• Inputs on the left (or top)
• Outputs on right (or bottom)
• Gates flow from left to right
• Straight wires are best
A
B
Y
C
D
E
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Circuit Schematic Rules (cont.)
• Wires always connect at a T junction
• A dot where wires cross indicates a
connection between the wires
• Wires crossing without a dot make no
connection
wires crossing
wires connect wires connect without a dot do
at a T junction at a dot not connect

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Two-Level Logic
• Two-level logic: ANDs followed by ORs
• Example: Y = ABC + ABC + ABC
A B C

A B C
minterm: ABC

minterm: ABC

minterm: ABC

Implements functions in SOP form

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Multilevel Logic
• Complex logic is often built from many stages of
simpler gates.

A
B

C Y
D

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Multiple-Output Circuits
• Example: Priority Circuit
Output asserted A3 A2 A1 A0 Y3 Y2 Y1 Y0
corresponding to most 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
significant TRUE input 0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 1 0 0 0
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 0
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0

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Priority Circuit Hardware
A3 A2 A1 A0 Y3 Y2 Y1 Y0 Y3 = A 3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
Y2 = A 3 A 2
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
Y1 = A 3 A 2 A 1
0 1 0 0 0 1 0 0 Y0 = A 3 A 2 A 1 A 0
0 1 0 1 0 1 0 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 0 A3 A 2 A1 A0
1 0 0 0 1 0 0 0 Y3
1 0 0 1 1 0 0 0
1 0 1 0 1 0 0 0 Y2
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 0 Y1
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0
Y0

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Don’t Cares
Y3 = A 3
A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 Y2 = A 3 A 2
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0 Y1 = A 3 A 2 A 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 0 0
Y0 = A 3 A 2 A 1 A 0
0 1 0 1 0 1 0 0
0 1 1 0 0 1 0 0 A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1
1 0 0 1 1 0 0 0 0 0 1 X 0 0 1 0
1 0 1 0 1 0 0 0 0 1 X X 0 1 0 0
1 0 1 1 1 0 0 0 1 X X X 1 0 0 0
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 0
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0

82 Digital Design & Computer Architecture Combinational Logic Design

Chapter 2: Combinational Logic

Two-Level
Logic Forms
Two-Level Logic Variations
• ANDs followed by ORs: SOP form
• ORs followed by ANDs: POS form
• Only NAND gates: SOP form
• Only NOR gates: POS form

Most common form of two-level logic

84 Digital Design & Computer Architecture Combinational Logic Design

Two-Level Logic Variation
• Two-level logic variation: ORs followed by ANDs
• Example: Y = (A+B)(A+B+C)
A B C

A B C
(A+B)

(A+B+C)

Implements functions in POS form

85 Digital Design & Computer Architecture Combinational Logic Design
Two-Level Logic
• Two-level logic: ANDs followed by ORs → NANDs
• Example: Y = ABC + ABC + ABC
A B C

A B C
minterm: ABC

minterm: ABC

minterm: ABC

Y
Both: SOP form
Put bubbles on internal nodes.
86 Digital Design & Computer Architecture Combinational Logic Design
Two-Level Logic Variation
• Two-level logic: ORs followed by ANDs → NORs
• Example: Y = (A+B)(A+B+C)
A B C

A B C
(A+B)

(A+B+C)

Y
Y Both: POS form
Put bubbles on internal nodes.
87 Digital Design & Computer Architecture Combinational Logic Design
Chapter 2: Combinational Logic

Bubble Pushing
De Morgan’s Theorem

# Theorem Dual Name

T12 B•C•D… = B+C+D… B+C+D…= B•C•D… De Morgan’s
Theorem

89 Digital Design & Computer Architecture Combinational Logic Design

De Morgan’s Theorem
Example D1:
Y = A+BC • Work from the outside in
= A•BC (i.e., top bar, then down)
• Use involution when possible
= A•BC
= ABC

90 Digital Design & Computer Architecture Combinational Logic Design

De Morgan’s Theorem
Example D2:
Y = A+BC+AB • De Morgan applies to:
= A•BC •AB ▪ Products under a bar
▪ Sums under a bar
= A•BC •(A + B)
• Do not try to apply
= ABC •(A + B) DeMorgan’s to a mix of
= ABCA + ABCB operations
= ABC

91 Digital Design & Computer Architecture Combinational Logic Design

De Morgan’s Theorem
Example D2:
Y = A+BC+AB Don’t forget these
= A•BC •AB parentheses!
Remember:
= A•BC •(A + B) AB = (A + B)
= ABC •(A + B)
= ABCA + ABCB
= ABC

92 Digital Design & Computer Architecture Combinational Logic Design

De Morgan’s Theorem: Gates
• Y = AB = A + B A
Y
B NAND gate
A two forms
Y
B

• Y=A+B=A B A
Y
B NOR gate
A two forms
Y
B

93 Digital Design & Computer Architecture Combinational Logic Design

Bubble Pushing
• Backward:
– Body changes
– Adds bubbles to inputs
A A
Y Y
B B

• Forward:
– Body changes
– Adds bubble to output

A A
Y Y
B B

94 Digital Design & Computer Architecture Combinational Logic Design

Bubble Pushing
• What is the Boolean expression for this
circuit?
A
B
Y
C
D

∙ CD
Y = AB + CD

95 Digital Design & Computer Architecture Combinational Logic Design

Bubble Pushing Rules
• Begin at output, then work toward inputs
• Push bubbles on final output back
• Draw gates in a form so bubbles cancel

A
B

C Y
D

96 Digital Design & Computer Architecture Combinational Logic Design

Bubble Pushing Example
no output
A bubble
B

C Y
D

bubble on
A input and output
B

C Y
D
no bubble on
input and output
A
B

C Y
D
Y = ABC + D

97 Digital Design & Computer Architecture Combinational Logic Design

Chapter 2: Combinational Logic

X’s and Z’s, Oh My

Contention: X
• Contention: circuit tries to drive output to 1 and 0 at the same time
– Actual value somewhere in between 0 and 1
– Could be 0, 1, or in forbidden zone
– Might change with voltage, temperature, time, noise
– Often causes excessive power dissipation

A=1
X indicates that the circuit node
Y=X has an unknown or illegal value
B=0

• X is also used for:

– Uninitialized values
– “Don’t care” values
• Warnings:
– Contention or uninitialized outputs usually indicate a bug.
– Look at the context to tell meaning

99 Digital Design & Computer Architecture Combinational Logic Design

Floating: Z
• Floating, high impedance, open,
high Z
• Floating output might be 0, 1, or
Tristate Buffer
somewhere in between (High, Low, floating)

– A voltmeter won’t indicate whether a E (enable)

node is floating A Y

– But if you touch the node or your

E A Y
instructor walks over for a checkoff, it may 0 0 Z
change randomly 0 1 Z
1 0 0
1 1 1

100 Digital Design & Computer Architecture Combinational Logic Design

Tristate Buffers on Busses
Floating nodes are used in tristate
processor en1

busses to bus
from bus

– Many different drivers

• E.g., a microprocessor, a video controller, video en2

to bus
and an Ethernet controller all communicate

sharedbus
from bus

with the memory system in a PC.

– Exactly one is active at once Ethernet
to bus
en3

from bus

memory en4

to bus
from bus

101 Digital Design & Computer Architecture Combinational Logic Design

Chapter 2: Combinational Logic

Karnaugh Maps
Karnaugh Maps (K-Maps)
• Boolean expressions can be minimized by
combining terms
• K-maps minimize equations graphically
– PA + PA = P
A B C Y Y Y
AB AB
0 0 0 1
00 01 11 10 C 00 01 11 10
0 0 1 1 C
0 1 0 0
0 1 1 0 0 1 0 0 0 0 ABC ABC ABC ABC
1 0 0 0
1 0 1 0
1 1 0 0 1 1 0 0 0 1 ABC ABC ABC ABC
1 1 1 0

103 Digital Design & Computer Architecture Combinational Logic Design

K-Map
• Circle 1’s in adjacent squares
• In Boolean expression: include only literals
whose true and complement forms are not in
the circle
A B C Y Y Y
AB AB
0 0 0 1
00 01 11 10 C 00 01 11 10
0 0 1 1 C
0 1 0 0
0 1 1 0 0 1 0 0 0 0 ABC ABC ABC ABC
1 0 0 0
1 0 1 0
1 1 0 0 1 1 0 0 0 1 ABC ABC ABC ABC
1 1 1 0

Y = AB Y = ABC+ABC = AB

104 Digital Design & Computer Architecture Combinational Logic Design

3-Input K-Map
• Circle 1’s in adjacent squares
• In Boolean expression: include only literals
whose true and complement forms are not in
the circle
Truth Table K-Map
Y
A B C Y AB
0 0 0 0 C 00 01 11 10
0 0 1 0
0
0
1
1
0
1
1
1
0 0 1 0 0
1 0 0 0
1
1
0
1
1
0
0
0
1 0 1 1 0
1 1 1 1

Y = AB + BC
105 Digital Design & Computer Architecture Combinational Logic Design
Some Definitions
• Complement: variable with a bar over it
A, B, C
• Literal: variable or its complement
A, A, B, B, C, C
• Implicant: product of literals
ABC, AC, BC
• Prime implicant: implicant that cannot be combined
with any other implicants in the equation to form a
new implicant with fewer literals

106 Digital Design & Computer Architecture Combinational Logic Design

K-Map Rules
• Every 1 must be circled at least once
• Each circle must span a power of 2 (i.e. 1, 2,
4) squares in each direction
• Each circle must be as large as possible
• A circle may wrap around the edges

107 Digital Design & Computer Architecture Combinational Logic Design

4-Input K-Map
A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

108 Digital Design & Computer Architecture Combinational Logic Design

4-Input K-Map
A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Y = AC + ABD + ABC + BD

109 Digital Design & Computer Architecture Combinational Logic Design

Chapter 2: Combinational Logic

Karnaugh Maps with

Don’t Cares
K-Map Rules
• Every 1 must be circled at least once
• Each circle must span a power of 2 (i.e. 1, 2,
4) squares in each direction
• Each circle must be as large as possible
• A circle may wrap around the edges
• Circle a “don't care” (X) only if it helps
minimize the equation

111 Digital Design & Computer Architecture Combinational Logic Design

K-Maps with Don’t Cares
A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
01 0 X X 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1 11 1 1 X X
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X 10 1 1 X X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

112 Digital Design & Computer Architecture Combinational Logic Design

K-Maps with Don’t Cares
A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
01 0 X X 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1 11 1 1 X X
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X 10 1 1 X X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X Y = A + BD + C
1 1 1 1 X

113 Digital Design & Computer Architecture Combinational Logic Design

 Chapter 2: Combinational Logic

Combinational Building
Blocks: Multiplexers
Multiplexer (mux)
• Selects one of N inputs and connects it to
output
• Select input takes log2N bits – control input
• Example: 2:1 mux
S

D0 0
Y
D1 1

S D1 D0 Y S Y
0 0 0 0 0 D0
0 0 1 1 1 D1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

115 Digital Design & Computer Architecture Combinational Logic Design

2:1 Multiplexer Implementations
• Logic gates • Tristates
– Sum-of-products form – Two tristate buffers
Y
D0 D1
– Turn on exactly one to
S
00 01 11 10 select the appropriate
0 0 0 1 1 input

1 0 1 1 0

S
Y = D0S + D1S

D0
D0

S D1
D1

116 Digital Design & Computer Architecture Combinational Logic Design

4:1 Multiplexer Implementations
2-Level Logic Tristates 4:1 mux symbol

Hierarchical

117 Digital Design & Computer Architecture Combinational Logic Design

Logic using Multiplexers
Using mux as a lookup table
AB
A B Y S1 S0
0 0 0 00
0 1 1 01
Y
1 0 0 10
1 1 0 11

Y = AB

118 Digital Design & Computer Architecture Combinational Logic Design

 Chapter 2: Combinational Logic

Combinational Building
Blocks: Decoders
Decoders
• N inputs, 2N outputs
• One-hot output: only one output HIGH at once
2:4
Decoder
11 Y3
A1 10 Y2
A0 01 Y1
00 Y0

A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

120 Digital Design & Computer Architecture Combinational Logic Design

Decoder Implementation
A1 A0

Y3

Y2

Y1

Y0

121 Digital Design & Computer Architecture Combinational Logic Design

Logic Using Decoders
• Two-input XNOR using decoder

2:4
Decoder Minterm
11 AB
A 10 AB
B 01 AB
00 AB

Y = AB + AB
= A  B Y
122 Digital Design & Computer Architecture Combinational Logic Design
Chapter 2: Combinational Logic

Timing
Timing
• Delay: time between input change and
subsequent output change
• How to build fast circuits?
A Y

delay

Time

124 Digital Design & Computer Architecture Combinational Logic Design

Propagation & Contamination Delay
• Propagation delay: tpd = max delay from
input to output
• Contamination delay: tcd = min delay from
input to output
A Y

tpd

tcd

Time
125 Digital Design & Computer Architecture Combinational Logic Design
Propagation & Contamination Delay
• Delay is caused by
– Capacitance charging and resistance in a circuit
– Speed of light limitation
• Reasons why tpd and tcd may be different:
– Different rising and falling delays
– Multiple inputs and outputs, some of which are
faster than others
– Circuits slow down when hot and speed up when
cold

126 Digital Design & Computer Architecture Combinational Logic Design

Critical (Long) & Short Paths
Critical Path

A n1
B
n2
C
D Y

Short Path

Critical (Long) Path: tpd = 2tpd_AND + tpd_OR (max delay)

Short Path: tcd = tcd_AND (min delay)

127 Digital Design & Computer Architecture Combinational Logic Design

Glitches
• Def.: a single input change causes an
output to change multiple times
A
B
Y
• Q: What happens
C
when A = 0, C = 1,
Y
B falls? AB
00 01 11 10
C
0 1 0 0 0

1 1 1 1 0

Y = AB + BC

128 Digital Design & Computer Architecture Combinational Logic Design

Glitches (cont.)
Critical Path
A=0 0 1
B=1 0 n1
Y=1 0 1
n2
C=1 1 0

Short Path

n2

n1

Y glitch

Time

129 Digital Design & Computer Architecture Combinational Logic Design

Fixing the Glitch
Y
AB
00 01 11 10
C
0 1 0 0 0

1 1 1 1 0

AC Y = AB + BC + AC
.. covers the prime
implicant boundary
A=0
B=1 0
Y=1

C=1

130 Digital Design & Computer Architecture Combinational Logic Design

Why Understand Glitches?
• Because of synchronous design
conventions (see Chapter 3), glitches don’t
cause problems.
• We can’t get rid of all glitches –
simultaneous transitions on multiple inputs
can also cause glitches.
• It’s important to recognize a glitch: in
simulations or on oscilloscope.

131 Digital Design & Computer Architecture Combinational Logic Design

About these Notes
Digital Design and Computer Architecture Lecture Notes
© 2021 Sarah Harris and David Harris

These notes may be used and modified for educational and/or

non-commercial purposes so long as the source is attributed.

132 Digital Design & Computer Architecture Combinational Logic Design