CA Assignment 2025 - 20-Line Answers

(Assignment-1)
Set-I

1. Fundamental principles of computer architecture; comparative analysis of

2. Instruction Length: CISC instructions vary in length; RISC instructions are fixed length
(typically 32-bit).

3. Microcode vs Hardwired: CISC often uses microprogramming; RISC uses hardwired

4. Execution Cycles: CISC may take multiple cycles per instruction; RISC is designed for
single-cycle execution.

5. Register Count: CISC uses fewer registers; RISC architectures provide many general-
purpose registers.

6. Addressing Modes: CISC supports numerous modes; RISC limits to simple load/store
addressing.

7. Memory Access: CISC allows multiple memory accesses per instruction; RISC employs
load/store architecture.

8. Pipeline Efficiency: RISC pipelines are deeper and simpler; CISC pipelines are shorter
with complex stages.

9. Compiler Role: RISC relies heavily on compiler optimizations; CISC offloads complexity to
hardware.

10. Code Density: CISC instructions pack more work per instruction, often yielding denser
code.

11. Performance: RISC often outperforms CISC in pipelined, parallel environments.

12. Power Consumption: RISC’s simplicity leads to lower power use, beneficial in embedded
systems.

13. Hardware Complexity: CISC control units are more complex; RISC simplifies the control
path.
14. Implementation Cost: RISC design is cheaper to implement in silicon due to simplicity.

15. Legacy Support: CISC maintains backward compatibility with older codebases.

16. Scalability: RISC architectures scale well with increasing clock speeds.

17. Throughput: RISC’s uniform instruction timing enhances throughput predictability.

18. Examples: x86 is historically CISC; ARM and MIPS are classic RISC.

19. Modern Convergence: Many modern CISC chips internally translate to RISC-like micro-
ops.

20. Summary: CISC optimizes code density and legacy support; RISC focuses on speed and
simplicity.

2. Role of data types (integers) and implications of arithmetic operations;

2. Integer operations: addition, subtraction, multiplication, division behave on two’s

3. Fixed-point representation encodes fractional values by scaling integers.

4. Multiplication and division operations vary in complexity and cycle count.

5. Floating-point uses IEEE 754 standard: sign bit, exponent, mantissa.

6. Floating-point arithmetic supports a wide dynamic range at cost of precision.

7. Integer overflow wraps around via modulo arithmetic; floating-point overflow leads to
infinities.

8. Rounding modes in floating-point affect numerical accuracy.

9. Hardware FPU accelerates floating-point operations relative to integer emulation.

10. Denormalized numbers handle very small magnitudes in floating-point.

11. Fixed-point arithmetic is faster and simpler but less flexible than floating.

12. Division is slower than multiplication and often implemented in microcode.

13. Pipeline stalls occur on multi-cycle arithmetic instructions.

14. SIMD extensions (SSE, AVX) apply vectorized integer and floating operations.

15. Sign extension and zero extension handle converting between integer sizes.
16. Floating-point exceptions: NaN, overflow, underflow, invalid operations.

17. Precision loss in floating arithmetic necessitates careful algorithm design.

18. Mixed-type arithmetic requires type promotion and potential conversion overhead.

19. Compiler optimizations leverage specific hardware instructions for speed.

20. Choosing between fixed and floating involves trade-offs of speed, precision, and range.

3. Performance of memory hierarchy: system memory, cache, virtual memory,

2. Cache levels (L1, L2, L3) bridge gap between CPU and main memory latency.

3. Hit rate and miss penalty determine cache effectiveness on performance.

4. Cache associativity, line size, and replacement policy impact hit rates.

5. Main memory latency (~50-100ns) and bandwidth limit throughput.

6. Virtual memory uses page tables to map virtual to physical addresses.

7. Page faults incur high penalty due to disk access (~ms).

8. TLB (Translation Lookaside Buffer) caches page table entries for speed.

9. Secondary storage: HDDs have mechanical delays (seek, rotational latency).

10. Optical disks (CD/DVD) are slower with higher access times and lower bandwidth.

11. SSDs replace HDDs for faster random access and higher throughput.

12. Prefetching and write-back policies improve memory performance.

13. Cache coherence protocols maintain consistency in multiprocessors.

14. Memory interleaving and banking increase bandwidth.

15. RAID and caching layers accelerate storage access.

16. Virtual memory enables program isolation and memory overcommitment.

17. Swap space on disk prolongs available memory at performance cost.

18. Hierarchical design balances cost, capacity, and speed trade-offs.

19. System performance hinges on optimizing hotspot data in faster tiers.

20. Holistic tuning across cache, RAM, and storage yields best overall throughput.
4. Organization and utilization of system memory and cache memory: types and
organization.
1. System memory (DRAM) organized in rows, columns, banks, and channels.

2. DRAM refresh cycles maintain data integrity periodically.

3. Multi-channel memory architecture increases parallelism and bandwidth.

4. Memory controllers schedule reads/writes to optimize row hits.

5. Cache memory is SRAM-based for low latency and high speed.

6. Cache organized by levels: L1 (split I/D), L2 (unified), L3 (shared).

7. Direct-mapped, fully associative, and set-associative are common cache mappings.

8. Cache lines store contiguous bytes; line size affects spatial locality.

9. Write-through vs write-back policies determine write behavior.

10. Write-back uses dirty bits to mark modified lines for later write-back.

11. Victim and victim cache help reduce conflict misses.

12. Inclusive vs exclusive cache hierarchies manage data redundancy.

13. Prefetching predicts future accesses to reduce miss rates.

14. Cache locking and partitioning optimize real-time and multi-core workloads.

15. NUMA architectures feature local caches tied to specific processors.

16. Memory interleaving spreads addresses across banks for throughput.

17. ECC DIMMs detect and correct single-bit errors in main memory.

18. Cache coherence protocols (MESI) ensure consistency across cores.

19. Hardware prefetchers use stride and streaming detection.

20. Proper balance of cache size, associativity, and policies maximizes efficiency.