VLSI Question Bank

Differentiate dataflow, behavioral, and with suitable examples.

Explain possible abstraction levels for any digital circuit.
Briefly write about various data types and operators used in VHDL programming with suitable
examples.
Describe various abstraction levels possible in VLSI design process with suitable example.
Explain briefly various types of delays used in VHDL programming with suitable examples and
timing diagrams.
Briefly write about various types of attributes used in VHDL programming suitable examples.
Compose VHDL code for 6 bits wide binary ripple adder using structural type of modeling.
Differentiate role of signal and variable used in VHDL with proper examples.
Compose VHDL code for 7 bits wide (data bits) even parity generator clrcuit using behavioral
type of modeling.
Explain the functioning of generate statement available in VHDL with suitable example.
Design 011 Moore sequence detector circuit using D flip-flops and prove that output is
independent of input.
Compose a VHDL code for 011 sequence detector circuit.
Design a circuit for 011 sequence detector with following features....should be of Melay type,
last single bit overlapping, and use D flip-flops for designing. Also prove that output is a
function of input.
Compose VDHL code for 011 Melay type of sequence detector with last bit overlapping. Draw
state diagram also.
Model VHDL code for a D flip-flop working in an asynchronous mode with clock input. Draw
entity diagram also.
Describe variants of wait statement used in VHDL programming with suitable examples.
Model the given Boolean expression in following mentioned VHDL coding style.....FA'B'I0+
A'BI1 + AB'12 + ABI3
1. Data flow
2. Behavioral.
With the help of neat sketch diagram explain VLSI design flow.
Compose VHDL code for 3:8 bubbled output decoder using with-select concurrent statement.
This circuit should work as decoder only when enable lines E1, E2, and E3 must have values
110 resp.
Model a synchronous UP/DOWN counter whose counting sequence is 0-1-2-3-4-5-6-7-8-9-0
during UP count and 9-8-7-6-5-4-3-2-1-0-9 during DOWN count using any suitable VHDL
coding technique.
Compose a VHDL code for 3 bit ripple counter using Structural type of modeling. Consider JK
flip-flop as a component for the same.
Explain possible types of attributes used in VHDL programming with suitable examples
Compose VHDL code for BCD to 7-segment (common cathode type decoder using with select
statement.
Compose VHDL code for decade· counter using any suitable behavioral type of modeling
Design a Moore machine to detect a sequence 011 using D flip-flops and prove that the output
is independent of input
Which are possible wait statements in VHDL programming? Explain each with suitable
example.

In 2022 IPL cricket tournament many people have witnessed the final match between Mumbai
Indians and Punjab Kings at D. Y. Patil stadium, Mumbai. Design a system to detect group of
male and female sitting in a sequence male-female-male. Consider logic 1 for male and logic 0
for female. Model the same design using suitable VHDL coding technique.

Interpret the output of following VHDL operations if A = 1101, B = 0110, C = 1110

i. Y1 := A sra 2; ii. Y2 := A sll 2; iii. Y3 := B srl 2; iv. Y4 := C**2;
v. Y5:= C sla 2; vi. Y6 := A rol 2; Y7 := A & not B.
List various Operators used in Verilog HDL. Write in detail about logical operators with
suitable examples.
Explain with suitable examples Lexical tokens, and Operators used in Verilog HDL.
Elaborate different Loop statements available in Verilog HDL with suitable examples.
Explain various delays used in Verilog HDL. Mention suitable examples also.
Explain briefly the functioning of "always" statement used in Verilog programming with
suitable example.
Compose Verilog code for 4 bit ALU which will perform operations like addition, subtraction,
anding, oring, xoring using behavioral type of modeling
Compose Verilog code for positive edge triggered synchronous D flip-flop.
Compose Verilog code for MOD-13 counter.
Compose Verilog HDL code for BCD to common cathode type seven segment decoder.
Compose Verilog code for 4:1 mux using always and case statement.
Compose Verilog HDL code for 4 bit binary to excess-3 code converter.
Compose Verilog HDL code for 4 bit up-counter using behavioral type of modeling.
Compose Verilog HDL code for 4:1 mux using data flow type of modeling
Compose Verilog HDL code for 4 bit binary to Gray code converter
Compose Verilog HDL code for 3:8 decoder using always and case statement
Explain briefly Spartan family FPGA architecture
With suitable sketch explain CLB architecture available in FPGA
Briefly write about Input/Output pin block architecture for Spartan Family FPGA.
Explain briefly how the architecture of a 4:1 multiplexer is getting configured in FPGA
Draw the detail circuit diagram for XC9500 CPLD macrocell and explain its working
Draw the detail circuit diagram for XC9572 CPLD input-output block and explain its working.
Elaborate stuck-at-fault techniques used for testing combinational circuits.
Write briefly about Built-In-Self-Test (BIST) testing mechanism used for testing configured
digital circuits.
Explain Boundary Scan testing mechanism used for testing sequential digital circuits.
Explain how faults could be identified using path sensitization technique in combinational logic
circuits.
With the help of neat sketch explain working of enhancement type nMOS transistor.
Draw the circuit diagram of 4 input CMOS NAND gate and explain its working.
Draw the circuit diagram of 3 Input CMOS NAND gate and explain its working.
Sketch complementary CMOS gate circuitry for the following Boolean Equations.
a. Y A. B. C
b. YA+B+C
Sketch and explain each abstraction level for a single NAND gate