70 Practice Questions
70 Practice Questions
A. Control Unit
B. ALU
C. Registers
D. Cache
C. Read-Only Memory
A. Data Bus
B. Address Bus
C. Control Bus
D. Power Bus
4. The control unit is responsible for directing operations inside the CPU. True or False?
A. True
B. False
C. Depends on architecture
D. None
A. RAM
B. ROM
C. Cache
D. Hard Disk
A. ALU
B. Control Unit
C. CPU
D. Motherboard
A. External
B. Internal
C. Slower
D. Volatile
A. Instruction Register
B. Program Counter
C. Stack Pointer
D. Data Register
A. Program Counter
B. Process Control
C. Program Control
D. Processor Counter
A. ALU
B. Control Unit
C. Registers
D. Cache
A. Bits
B. Bytes
C. Seconds
D. Cycles
A. Specific tasks
B. Temporary data
C. Only arithmetic
D. Only logic
A. Decode
B. Execute
C. Fetch
D. Store
14. During decode, the control unit interprets the instruction. True or False?
A. True
B. False
C. Only in RISC
D. Only in CISC
A. True
B. False
C. Depends
D. None
A. Fetch
B. Decode
C. Execute
D. Store
A. MAR
B. MDR
C. PC
D. IR
A. Error occurs
C. User interrupts
D. Half instructions
A. True
B. False
C. Only in CISC
D. Not possible
A. Current instruction
B. Next instruction
C. Data
D. Address
A. Software
B. Hardware
C. GPU
D. ALU
A. Fetch
B. Decode
C. Execute
D. Store
Types of Computer Architecture
A. True
B. False
C. Depends
D. Only in Harvard
26. Harvard architecture separates instruction and data memory. True or False?
A. True
B. False
C. Depends
D. Only in RISC
A. True
B. False
C. Depends
D. Only in CISC
28. CISC stands for Complex Instruction Set Computer. True or False?
A. True
B. False
C. Depends
D. None
A. Von Neumann
B. Harvard
C. RISC
D. CISC
A. True
B. False
C. Depends
D. In hybrid
31. x86 is an example of CISC architecture. True or False?
A. True
B. False
C. Depends
D. Only in Intel
A. RISC
B. CISC
C. Both
D. Neither
33. Harvard architecture can improve speed due to separate buses. True or False?
A. True
B. False
C. Depends
D. None
A. CPU power
B. Memory bandwidth
C. Disk speed
D. GPU speed
35. Which architecture uses unified cache for data and instructions?
A. RISC
B. CISC
C. Von Neumann
D. Harvard
A. Von Neumann
B. Harvard
C. RISC
D. CISC
High-Level Languages
37. Which is NOT a high-level language?
A. Python
B. C
C. Assembly
D. Java
A. True
B. False
C. Only Java
D. Only Python
A. True
B. False
C. Only compiled
D. Depends
A. True
B. False
C. None
D. Depends
A. Python
B. Java
C. JavaScript
D. Ruby
A. C
B. C++
C. Java
D. Assembly
B. Fortran
C. Simula
D. Pascal
A. Python
B. C
C. SQL
D. HTML
A. PHP
B. C
C. Assembly
D. Fortran
A. C
B. Java
C. Python
D. Assembly
A. C
B. Python
C. Java
D. Ruby
A. Java
B. C#
C. C
D. JavaScript
B. False
C. Only in Ada
D. Only in C
A. True
B. False
C. Only in C
D. Only in Java
A. True
B. False
C. Depends
D. Only by pointer
A. Python
B. C
C. Java
D. Ruby
A. Copy-in copy-out
B. Delayed evaluation
C. Reference copy
D. None
A. Algol
B. C
C. Java
D. Python
A. True
B. False
C. Depends
D. None
A. Value
B. Reference
C. Value of reference
D. Pointer
A. True
B. False
C. Only macros
D. Only functions
A. True
B. False
C. Only in C
D. Only in Java
A. Pass by value
B. Pass by reference
C. Pass by copy
D. Pass by name
A. Pass by value
B. Pass by reference
C. Pass by pointer
D. Pass by result
A. Bytecode
B. Machine code
C. Source code
D. None
A. Compile time
B. Run time
C. Link time
D. None
A. C++
B. Java
C. Python
D. Fortran
A. Parser
B. Lexer
C. Compiler
D. Interpreter
A. Loops
B. Stack frames
C. Variables
D. None
A. Heap
B. Stack
C. Cache
D. Registers
A. Process
B. Thread
C. Function
D. None
C. No waiting
D. None
A. Opcode
B. Operand
C. Register
D. Flag
A. Registers
B. Memory
C. Cache
D. CPU
Answer Key
1. B
2. A
3. B
4. A
5. C
6. C
7. B
8. B
9. A
10. B
11. A
12. B
13. C
14. A
15. A
16. D
17. B
18. A
19. A
20. B
21. A
22. A
23. B
24. A
25. A
26. A
27. A
28. A
29. B
30. A
31. A
32. B
33. A
34. B
35. C
36. B
37. C
38. A
39. A
40. A
41. B
42. C
43. C
44. B
45. A
46. C
47. B
48. C
49. A
50. A
51. A
52. B
53. A
54. A
55. A
56. C
57. A
58. A
59. B
60. B
61. B
62. B
63. C
64. B
65. B
66. B
67. A
68. A
69. A
70. B