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Blocking and Non Blocking Assignment

The document compares blocking and non-blocking assignments in Verilog, highlighting that blocking assignments are preferred for combinational logic due to their sequential execution, while non-blocking assignments are better for sequential logic as they allow concurrent execution. Using blocking assignments in sequential logic can lead to race conditions, while using non-blocking assignments in combinational logic can cause errors and confusion. Overall, the choice between the two types of assignments is crucial for correct and efficient circuit design.

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1bt18cs002 Amudha
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9 views2 pages

Blocking and Non Blocking Assignment

The document compares blocking and non-blocking assignments in Verilog, highlighting that blocking assignments are preferred for combinational logic due to their sequential execution, while non-blocking assignments are better for sequential logic as they allow concurrent execution. Using blocking assignments in sequential logic can lead to race conditions, while using non-blocking assignments in combinational logic can cause errors and confusion. Overall, the choice between the two types of assignments is crucial for correct and efficient circuit design.

Uploaded by

1bt18cs002 Amudha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Blocking Assignment( = )

1) Blocking assignment is a one step process


2) Evaluate the RHS of the expression and update the LHS without any delay.
3) Blocking statement executed in the Active region of Verilog stratified event queue.
4) While modelling combinational logic,blocking statements are preffered .
5) Blocking statement can be used in initial,always blocks and assign statements.
6) blocking assignment executed sequentially.
7) Any delay attached is also got added to delay in execution of next statement.
8) It is time consuming simulation.
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Non Blocking Assignment ( <= )


1) Non-Blocking assignment is a two step process
2) Evaluate the RHS expression at the beginning of time step and update the LHS at the
end of time step.
3) Evaluation of Non blocking statement occurred in Active region and updation of Lhs
side happen in NBA region
4) While modelling sequential logic,non blocking statements are preffered.
5) Non blocking can only be used in initial and always block but assign statements can
not used.
6) Non-blocking assignment executed concurrently.
7) Do not cause delays in the execution of subsequent statement.They are more
efficient

Why should a non blocking assignment be used for sequential logic,and what
would happen if a blocking assignment were used.
 In Verilog,non-blocking assignment (<=) should be used for
sequential logic
 Non-blocking assignment follow concurrent execution of
multiple assignment within the same always block
 If a blocking assignment were used in a sequential block,it
causes race around condition.
 This can lead unpredictable behaviour and incorrect results
in the circuit.

Why should a blocking assignment be used for combinational logic,and what


would happen if a non-blocking assignment were used.

 Blocking assignment should be used for combinational logic


 Blocking assignment follow sequential execution.Therefore
there is no risk of race condition.
 Use of blocking assignment in combinational logic is preffered
because it avoids unneccesary complexity and confusion.
 If a non blocking assignments were used in combinational
logic,it would cause error but it would be unneccassary and
could potentially confuse other designers who are modifying
the code.

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