DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

DIGITAL SYSTEM DESIGN USING VERILOG

BEC302
III SEMESTER
QUESTION BANK
Prepared by,
Mrs. MEGHANA M N
Assistant Professor
Dept. of ECE
MIT Thandavapura

A Unit of Maharaja Education Trust®

MAHARAJA INSTITUTE OF TECHNOLOGY

THANDAVAPURA

NH 766, Nanjangud Taluk, Mysuru- 571 302

(An ISO 9001:2015 and ISO 21001:2018 Certified Institution)
(Affiliated to VTU, Belagavi and approved by AICTE, New Delhi)
 MODULE – 1
PRINCIPLES OF COMBINATIONAL LOGIC

No VTU QP with
Questions
. Marks
1 Combinational Logic Circuits ***
Define and explain the combinational logic circuit along with the block diagram. MAR 2022 – 6M
2 Definitions *** Any definitions
Define the following terms: can be asked
 Literals 1M each
 Truth table***
 Product term and sum term***
 Sum of product and Product of sum
 Minterm and Max terms***
 Canonical form***
 Canonical sum of product and Canonical product of sum***
 Karnaugh maps
 Prime implicant and essential prime implicant***
 Incompletely specified terms and completely specified terms***
3 Problem Statement To Truth Table Conversion*****
 Design a combinational circuit that will multiply two 2 bit numbers.
 Design an odd parity generator using gates for the decimal digits 0 to 9
represented in 8421 BCD. Write the truth table and logic diagram.
 Design a combinational logic circuit that will generate the square of all
the combinations of three-bit binary numbers represented as A2, A1 and
A0. MAR 2022 – 5M
 Design a combinational logic circuit for valid single digit BCD data. The
output is 1 whenever a number greater than 5 appears in the input. SEP 2020 – 5M
 Represent the number of days in a month for a non-leap year by the truth
table, indicating the output of invalid input if any by ‘0’. AUG 2022 – 5M
 Design a combinational logic circuit that has three input variables and
produces a logic 1 output when more than one input variables are logic 1.
 Design logic circuits that has 4 inputs, the output will be high when
majority of the inputs are high. Use K-map to simplify. JAN 2020 – 5M
 Design a combinational circuit to output the 2’s complement of a 4-bit
binary number.
4 Canonical Forms*****
Develop the canonical minterm and maxterm forms in the decimal notation for
the following Boolean functions / place the following equations in proper
canonical form:
 X =f ( a ,b , c , d )=a b +c d
 Y =f ( a , b , c )=(a+b)(b+c ) MAR 2022 –
 Y =f ( a , b , c )=a b+a c +bc 6M
 X =f ( a ,b , c , d )=(a+b)+(a+ b+d )

SEP 2020 – 6M
5 K-Map*****
Find the minimal sum and minimal product for the function using K-Map
 X =f ( a ,b , c , d )=Σ ( 6 , 7 , 9 ,10 , 13 ) + Σ d (1 , 4 , 5 , 11,15) SEP 2020 – 8M
 f ( a , b , c , d )=π ( 1 ,2 , 3 , 4 , 9 , 10 ) + πd (0 , 14 , 15) SEP 2020 – 5M
6 K-Map***
Simplify the following using K–Map method and also construct logic circuit for
the simplified equation:
 Y =f ( a , b , c , d )=Σ ( 0 ,1 , 2 , 4 , 5 ,6 ,8 , 9 , 10 , 12, 13 , 14 ) MAR 2022 – 6M
 f ( w , x , y , z )=π (2 ,3 , 8 , 9 , 10 ,11, 12 ,13 ,14 ,15) AUG 2020 – 6M
7 K-Map
Simply the following expression using K-Map, implement the simplified using
NAND gates only
 F=f ( a ,b , c , d )=Σm ( 0 , 1 ,2 , 5 , 6 ,7 ,8 , 9 , 10 , 13 ,14 ,15 ) FEB 2021 – 6M
8 K-Map
Simply in POS form, implement the simplified using NOR gates only
 G=f ( a , b , c , d )=πM ( 1 ,3 ,8 , 10 , 12, 13 , 14 , 15 ) JAN 2019 – 8M
9 QMC*****
Simplify the following using Q-M method / tabulation method / PI reduction
table:
 X =f ( a ,b , c )=Σ ( 0 , 1 ,2 , 3 , 4 , 5 , 6 ) FEB 2021 - 8M
 Y =Σm ( 1 , 2 ,3 , 5 , 9 ,12 , 14 , 15 ) +dc (4 , 8 , 11)
10 QMC
Find all the prime implicants of the following using Quine-McClusky technique
 f ( a , b , c , d )=Σ ( 7 , 9 , 12, 13 , 14 , 15 ) + Σ d (4 ,11) SEP 2020 – 10M
11 K-Map***
Identify the PI and EPI for the following functions:
 M =f ( a , b , c , d ) =Σ ( 1 , 2, 3 , 5 ,7 ,11, 12 ,13 ,14 ,15 ) MAR 2022 – 5M
  f ( a , b , c , d )=Σ ( 0 , 1 ,2 , 5 ,6 ,7 , 8 , 9 , 10 ,13 ,14 ,15 ) SEP 2020 -6M

MODULE – 2
LOGIC DESIGN WITH MSI COMPONENTS AND PROGRAMMABLE
LOGIC DEVICES

Questions

BINARY ADDERS AND SUBTRACTORS

1. Design full subtractor and implement using logic gates. ** (Jan 2019 6M)
2. Design full adder and implement using logic gates.** (Jan 2019 6M)
or
Explain full adder with K-Map and logical representation of equations for sum and carry. (Feb 2023
6M)
3. Construct the parallel binary adder/subtractor. **
4. Explain carry look ahead adder with the neat diagram and relevant diagram. ***** (Jan 2020 8M, July
2019 8M, Mar 2022 8M, Jan 2019 10M)
or
Explain carry look ahead adder using general and sigma block (Jan 2023 6M)
5. Design a BCD adder or design Decimal adder or Explain working of decimal adder with neat block
diagram. ***** (Sept 2020 6M, Jan 2023 6M)

COMPARATOR

6. What is magnitude comparator? Design 2-bit magnitude comparator by writing truth table, relevant
expression and logic diagram. ***** (Jan 2023 8M, Jan 2018 6-8M, July 2019 6M, Mar 2022 8M, Jan
2018 6M, Sept 2020 8M, Aug 2022 6M)
7. Design one-bit comparator. Implement using suitable gates.

DECODERS AND ENCODERS

8. Explain priority encoder using 8 input lines. *** (July 2019 6M)
9. Design 4:2 priority encoder which gives MSB the highest priority and LSB the least priority.
10. Design 3:8 NAND decoder with active low enable and realize full adder using it. Jan 2019 4M

PROBLEMS

11. Implement the following function using single 3:8 decoder. **** (Jan 2023 6M, Jan 2018 6M)
12. Implement the function using 74138 3:8 decoder. (Jan 2019 6M)
13. Realize the following function in 2 possible ways using 3:8 decoders. Or implement the function using
 3 to 8 decoder with active low and active high output conditions. *** (Feb 2021 10M, Jan 2020 6M)
14. Implement the full subtractor using 3:8 decoder using active low outputs. **** (Jan 2020 6M)
15. Implement the full subtractor using 3:8 decoder (sept 2020 6M)
16. Design 4 to 16-line decoder using 3 to 8 line decoders (74LS138) (Mar 2022 8M)
17. Implement the following function using 8:1 MUX. **** (Feb 2021 4M, Jan 2020 6M, Jan 2023 8M,
Jan 2018 6-8M, Mar 2022 8M, Aug 2022 6M)
18. Implement the following function using 74151 8:1 MUX **** (Jan 2019 4M, Sept 2020 6M)
19. Realize the following using 4:1 MUX (Feb 2021 4M, jan 2020 6M)
 MODULE – 3
FLIP-FLOP AND ITS APPLICATIONS

Questions
20. Illustrate the working of Master-Slave SR flipflop with function table and timing diagram. *****
21. Illustrate the working of Master-Slave JK flipflop with function table and timing diagram. *****
22. Illustrate the working of Master-Slave D flipflop with function table and timing diagram. ***
23. Illustrate the working of Master-Slave T flipflop with function table and timing diagram. ***
24. Build the characteristic equation for JK and D flip flop. *****
25. Build the characteristic equation for SR and T flip flop.*****

MODULE 4
INTRODUCTION TO VERILOG & VERILOG DATAFLOW DESCRIPTION

Questions
26. Describe the structure of Verilog HDL with an example.
27. Write a note on datatypes of Verilog HDL.
28. Give the classification of styles of description with example.
29. Write a note on signal assignment statements.

MODULE 5
VERILOG DESCRIPTION

Questions
30. Develop a Verilog dataflow description for full adder.
31. Develop a Verilog dataflow description for full subtractor.
32. Develop a Verilog description for 8:1 MUX using case statement.
33. Develop a Verilog description for encoder and priority encoder using case statement.
34. Develop a Verilog description for 2bit comparator using case statement.
35. Develop a Verilog structural description for 3-bit ripple carry adder.