INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES (PLD):

Programmable Logic Circuit

1. Hardwire System / Circuit
 The operation of any circuit depends on IC chips used & electrical
connection between chips.
 No access to internal interconnections of IC chips.
 To design circuit, internal circuit diagram is to be specified.
 Once designed, the intended function can be performed.
 If the function changes, design needs to modified.
 So the internal circuit diagram needs to be changed.
 Such systems are called HARDWIRED SYSTEM.
2. Programmable Circuit
 It uses programmable components.
 Device includes arrays of logic elements on a chip & allows the user to
specify or
program many internal connections between these components on the chip.
 Logic elements could be various gates, inverters, buffers and even flip flops.
 A system function can be created on the chip, simply by programming the
chip or telling the chip where the interconnections are to be made.
 Such devices in general are called PROGRAMMABLE LOGIC DEVICE.
3. Programmable Logic Devices (PLD):-
 PLD is an IC chip that includes arrays of logic elements and allows a user to
specify the connections among many of these elements.
Advantages:
 Chip count & physical size of a system can be minimized.
 Time from conception of system to marketing of the system can be
minimized.
 Less chip count leads to integration of system on a single chip or small no. of
chips.
 Low development cost.
 Less space requirement.
 High reliability.
 Easy circuit testing.
 Easy design modification.
Disadvantages:
 Interconnections between elements on the chip must be specified or
programmed.
 PLDs also have hard wired connection but they cannot function until they are
programmed while Hardwired System functions.

TYPES OF PROGRAMMABLE LOGIC DEVICES (PLD):

Programmable Arrays
 OR Array
 AND Array
Classifications of Simple Programmable Logic Devices (SPLD)
 Read-Only Memory (ROM)
 Programmable Array Logic (PAL)
 Programmable Logic Array (PLA)
 Programmable Logic Sequencer (PLS)
More complex
 FPGA (Field Programmable Gate Arrays)
 CPLD (Complex Programmable Logic Devices)

Classifications of Simple Programmable Logic Devices (SPLD)

Read Only Memory (ROM / PROM):
 N-input address lines, m-output data lines.
 Address lines point locations within ROM that store words of m bits.
 ROM size is defined by the no. of locations & the word size.
 A 256 X 4 ROM indicates that the device has 256 storage locations each
holding a 4-bit word.
 This ROM would require eight address lines to access 256 locations.
 ROM of 32 X 8 has 32 memory locations each of 8-bit word and requires 5
address lines.
Structure of ROM is as shown below;

So No. of address lines (Input Lines) = n.

 No. of data lines (Output Lines) = m.
 ROM size = 2n X m.
 Size of decode which is to be used = n X 2n .
 ROM Consists of an array of semiconductor devices interconnected to store
an array of binary data.
 Can’t be changed once burned in.
 Conceptually, consist of a decoder and a memory array.
Advantages:
 Design become extremely easy.
 It is possible to change or modify the design quickly.
 Reduced cost.
 Modification takes less time than SSI/MSI circuits.
Disadvantages:
 Increase in power requirement.
 Complete circuit is not utilizes
 Increase in size with increase in number of input variables.
Programmable Array Logic (PAL):
 PAL is most commonly used type of PLD. It is a programmable array of
logic gates.
 The array of logic gates is on single chip and it is in the AND-OR
configuration.
 The special feature of PLA is that a programmable AND array and fixed OR
array.
 Also note that in each OR gate in the OR array gets input from some of the
AND gates.
That means output of all AND gates are not applied to any of the OR gates

In Un-programmed PAL all the links are connected with Fusible Link as shown
in below figure.
 As per required output function one needs to burn the fusible link and this
kind of PAL is known as a programmed PAL.
Simplified representation of PAL is shown in below figure.

Input Buffers:
 Input buffer in a PAL is used for avoiding the loading of sources connected at
the inputs.
 The buffer produce inverted and non-inverted versions of their corresponding
inputs.
 One such buffer is used for each of the input lines as shown in above figure.

AND Matrix:
 AND matrix is shown as above figure.
 The (X) mark indicate that a connection is present. Each AND gate has 2M
input which are shown only by a single line (e.g. A,B,C, etc….). Where M is the
No. of inputs.
 When a logic function is to be implemented, we have to program the array. In
programming the desired connections are left with the (X) marks and such mark
is not used when connection is not required.

OR Matrix:
 OR matrix is shown as above figure. In PAL fixed OR array is used so there
is no need to do programming to the OR array.
 No. of OR arrays are equal to the required No. of functions at the output.
Input and Output Circuit:
 The input and output circuit of PAL are similar to those PLAs.
 The No. of fusible link in PAL is equal to 2M x n. where M = No. of
available inputs and n = Corresponds to No. of product terms.
Advantages:
 For given internal complexity, a PAL can have larger N and M.
 Some PALs have outputs that can be complemented, adding POS functions.
 No multilevel circuit implementations in ROM (without external connections
from output to input). PAL has outputs from OR terms as internal.
Disadvantages:
 n x m ROM guaranteed to implement any m functions of n inputs. PAL may
have too few inputs to the OR gates.

Programmable Logic Array (PLA):

 A PLD generally consist of programmable array of logic gates.
Interconnections are made with the array inputs.
 PLA consist two levels of logic, an AND-plane and an OR-plane, where both
levels are programmable.
 The outputs are connected to the device pins through inverting or non-
inverting buffers and flip flops.
 The basic block diagram of a PLA is shown in below figure.
 Here programmable AND matrix can be used to implement the product terms
in the SOP form and the programmable OR array can be used for implementing
the sum of the product terms.
 Logic gates used can be two level AND-OR, NAND-NAND or NOR-NOR
configuration. Sometimes AND-OR-EXOR configuration is also used. But
generally AND-OR is most preferable configuration.
 Simplified representation of PLA is shown in below figure
Input Buffers:
 Input buffer in PLA is used for avoiding the loading of sources connected at
the inputs.
 Buffer of two types namely, inverted buffers and non-inverted buffers as
shown in below figure.
 One such buffer is used in each of the M input lines.
AND matrix
 The X indicates that a connection is present. Each AND gate has 2M inputs
which are shown only by single line where, M is No. of inputs (e.g. A,B,C,
etc….).
 When a logic function is to be implemented, we have to program the array. In
programming the desired connections are left with the (X) marks and such mark
is not used when connection is not required.
OR Matrix:

Above figure shows simplified representation of the OR matrix.

 It is possible to program the OR matrix, by open circuiting the unwanted
fusible links.
The open fusible links are equivalent to a ‘0’ at the input of corresponding OR
gate.
Applications of PLA:
1. We can implement combinational circuit using PLA. For this only ouput
buffers are used.
2. We can also implement sequential circuit using PLA. For implement this flip
flops and buffers are included in output stage.