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Hyper-Threading (HT) Technology

Hyper-Threading (HT) technology allows a single physical processor to function as multiple logical processors, enabling simultaneous execution of separate code streams. It was introduced with the Intel Pentium 4 Xeon processor, featuring replicated and shared resources to enhance performance while maintaining a low cost increase. By reducing context switches and optimizing CPU execution time, HT technology can improve system performance by approximately 25% with only a 5% increase in die area size.

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7 views3 pages

Hyper-Threading (HT) Technology

Hyper-Threading (HT) technology allows a single physical processor to function as multiple logical processors, enabling simultaneous execution of separate code streams. It was introduced with the Intel Pentium 4 Xeon processor, featuring replicated and shared resources to enhance performance while maintaining a low cost increase. By reducing context switches and optimizing CPU execution time, HT technology can improve system performance by approximately 25% with only a 5% increase in die area size.

Uploaded by

gunjansagvekar547
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Hyper-Threading (HT) Technology

Traditional P6 micro-architecture approaches to processor design have


focused on higher clock speeds, super pipelining, Instruction-Level parallelism
(ILP) and caches. Super pipelining is a way to achieve higher clock speeds by
having finer granularities. By using this technique, it is possible to execute
more and more instructions within a second. As there are far more
instructions in-fly, handling such events like cache misses, interrupts and
branch-miss prediction will be costly.

The features of hyper-threading technology are given below:

● HT makes a single physical processor appear as multiple logical


processors.
● Each logical processor has its own architecture state where a set
of single execution units are shared between logical processors.
● HT allows a single processor to fetch and execute two separate
code streams simultaneously.
● In most of the applications, the physical unit is shared by two
logical units.

Fig. 12.63 shows a two-processor system where each unit is capable of


hyper-threading technology. Therefore, the system in Fig. 12.63 can be
implemented as 4 CPU systems. This scheme has the same performance
gains but the cost increase is only 5% due to about 5% die-area size increase.
Architecture State (AS) Hyper-threading technology was introduced on the
Intel Pentium 4 Xeon TM processor. In this processor, there are two logical
processors in a single physical processor. Each logical processor has a
complete set of the architecture state.

The architecture state has the following registers:

● Registers including the general-purpose registers


● Control register
● Advanced Programmable Interrupt Controller (APIC) registers
● Machine state registers

Since two architecture states are present in a single physical processor, the
processor acts as two proces­sors with respect to software perspective. There
are three types of resources in hyper-threading technology such as replicated
resources, shared resources, and shared/replicated resources,

Replicated Resources Each processor has general-purpose registers, control


registers, flags, time stamp counters, and APIC registers. The content of these
registers are used as replicated resources.
Shared Resources Memory and range registers can be independently
read/write. Therefore, memory, range registers and data buses are used as
shared resources.

Shared/Replicated Resources The caches and queues in the hyper-threading


pipeline can he shared or not shared according to the situation.

When the process consists of m number of threads, the total time for context
switching will be m times that of a single thread context-switching time.
Hence, context switching requires a number of CPU cycles. If multiple
numbers of threads are present, system performance will be improved. But a
large number of threads consume more time in context switching.

To improve the system performances, the following methods are used:

● Reduce the number of context switches.


● Provide more CPU execution time to each process.
● Execute more than one process at the same time by increasing
the number Of CPUs.
● In multiple number of processor systems, the scheduler can
schedule two processes to two different CPUs for execution
simultaneously. Hence, the process will not be waiting for a long
duration to get executed.

In hyper-threading, the concept of simultaneous multi-threading is used.


Hence, there is an improvement in the Intel micro-architecture. With increasing
the cost of less than 5% in the die area, the system perfor­mance is increased
by about 25 per cent.

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