21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

INTRODUCTION TO HDL
In computer engineering, a Hardware Description Language (HDL) is a specialized computer
language used to describe the structure and behavior of electronic circuits, and most commonly, digital
logic circuits.
Due to the exploding complexity of digital electronic circuits since the 1970s (see Moore's law),
circuit designers needed digital logic descriptions to be performed at a high level without being tied to a
specific electronic technology, such as CMOS or BJT. HDLs were created to implement register-transfer
level abstraction, a model of the data flow and timing of a circuit.

 There are two major hardware description languages:

1. VHDL - Very High Speed Integrated Circuits Hardware Description Language
2. Verilog – Verification Logic
 There are different types of description/modeling in them:
1. Dataflow modeling
2. Behavioral modeling
3. Structural / Gate level modeling

INTRODUCTION TO VERILOG HDL

Verilog Hardware Description Language (HDL) is a hardware description language used to model and
simulate digital circuits. It is widely used in the design, verification, and implementation of digital
systems, including integrated circuits (ICs), field-programmable gate arrays (FPGAs), and application-
specific integrated circuits (ASICs).
1. Modules:
The basic building block in Verilog is the module.
A module represents a logical unit of hardware, similar to a function or subroutine in
software.Modules encapsulate the behavior and structure of a digital circuit.
2. Ports:
Modules can have input, output, or inout ports.
Ports define the interface of the module, allowing signals to flow in and out of it.
Ports are declared within module definitions.
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

3. Data Types:
Verilog supports various data types for representing different kinds of digital signals and
variables.
Common data types include wire, reg, integer, parameter, etc.
wire: Used for representing connections between components.
reg: Used for sequential logic elements like flip-flops and registers.
4. Continuous Assignments:
Continuous assignments allow you to assign values to wires directly within the module body.
They are used for combinational logic, where the output depends solely on the current input
values. Continuous assignments use the “assign” keyword.
5. Behavioral Statements:
Behavioral statements describe the behavior of a digital circuit.
They include procedural blocks like always, initial, and begin/end.
Procedural blocks are used to model sequential logic and control the simulation flow.
6. Simulation Constructs:
Verilog provides constructs for specifying simulation scenarios and test cases.
Testbenches are written to verify the functionality of modules.
Simulation constructs include initial blocks for initialization and always b locks for continuous
behavior.

DIFFERENCE BETWEEN VHDL & VERILOG

DESCRIPTION VERILOG VHDL

Program structure Defined by “module” Defined by “entity”

Root Language C programming language Pascal & Ada programming language
Sensitivity Case sensitive Case insensitive
Complexity Less complex More complex
Built Loosely typed language Strongly typed language

Usage Used to model electronic system Used in chip designing

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

INTRODUCTION TO XILINX
ISE Xilinx (Integrated Software Environment (ISE)), i.e. programmable logic design tool in electronics
industry. This Xilinx design software suite allows taking design from design entry through Xilinx device
programming. The ISE Project Navigator manages and processes design through several steps in the ISE
design flow. These steps are Design Entry, Synthesis, Implementation, Simulation/Verification, and
Device Configuration. Xilinx is one of most popular software tool used to synthesize VHDL code.
Release version : 14.7

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

XILINX TOOL PROCEDURE

PROCEDURE FOR SOFTWARE EXECUTION

STEP 1:

1. Double click on the ISE Design Suite 14.7 icon.

2. Go to file in file menu bar and select the option close project to close the old projects.
3. Go to file in file menu bar and select the new project.
4. Give the project name, location (Mandatory D Drive) and click on next.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

STEP 2:

5. In Step 2 make necessary changes:

Family : Spartan 6
Device : XC6SLX4
Package : TQG144
Speed : -3
Simulator : ISim (VHDL/Verilog)
Preferred language : Verilog
Then click on next and finish.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

STEP 3:

6. In the Design window (Left most top corner) Select available device (Ex. Xc6slx4-3csg225),
right click on it. Select the new source, select Verilog module, give file name, enable the Add
Project and click on next.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

7. Specify the ports (Input, Output and Inout). Then click on Next and Finish.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

STEP 4:

8. Write the verilog program and save it.

9. In the process window (Left most bottom corner), e xpand synthesize XST and double click on
check syntax.

10. If no errors found, then proceed to step 5.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

STEP 5:

11. In the Design window (Left most top corner), select .v file, click on new source.

12. In new source window select Verilog Test Fixture and give file name and enable the option Add
to Project, click on next, next and finish.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

STEP 6:
13. Give the inputs (between initial begin and end) in the Test bench (TB) file and click on save.

14. In the Design window (Left most top corner), Change the view to Simulation, select the test
bench (TB) file.
15. In the Process window (Left most bottom corner), elaborate ISim Simulator. Double click on
Behavioral Check Syntax to check for errors and double click on Simulate Behavioral Model to
observe the output waveform.

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16. Select the measure marker option in the Toolbar to verify the simulation output.
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

PROGRAM 01
4 - BIT ADDER

AIM
To design a Verilog model for 4-bit adder and to generate a report for determining total area,
maximum delay and power requirement.

APPARATUS REQUIRED

Sl. No. Name of the equipment / Software Quantity

1 PC with Windows 1
2 ISE Design Suite 14.7 (XilinxProject navigator) 1

THEORY

A 4-bit adder is a digital circuit that performs addition of two 4-bit binary numbers. The basic building
blocks of a 4-bit adder are the full adders. Each full adder takes in three inputs : two bits to be added (A
and B) and a carry in (Cin) from the previous stage. It produces two outputs: a sum (S) and a carry out
(Cout) to the next stage.

WORKING OF A 4-BIT ADDER

Input: Two 4-bit binary numbers are provided as input, typically labeled as A and B. Each of these
numbers is broken down into individual bits: A0, A1, A2, A3 and B0, B1, B2, B3.
Carry In (Cin): Initially, there is no carry into the least significant bit (LSB), so Cin is usually set to 0.
Addition: The bits from each position (A0 and B0, A1 and B1, and so on) are added together along with
the carry in (Cin) from the previous stage using full adders. This generates a sum (S) and a carry out
(Cout) for each stage.
Propagation: The carry out (Cout) from each stage is fed as the carry in (Cin) to the next higher-order
stage.
Output: The sum bits (S0, S1, S2, S3) generated at each stage constitute the result of the addition
operation. The carry out (Cout) from the most significant bit (MSB) indicates whether there is a carry
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beyond the 4-bit boundary, which would imply overflow in unsigned addition.
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

LOGIC SYMBOL

TRUTH TABLE

Inputs Outputs
A3 A2 A1 A0 B3 B2 B1 B0 Cin Cout S3 S2 S1 S0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 1 0 0 0 0 1 0 0
0 0 1 1 0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 1 0 0 0 0 1 0 0 0
0 1 0 1 0 1 0 1 1 0 1 0 1 1
0 1 1 0 0 1 1 0 0 0 1 1 0 0
0 1 1 1 0 1 1 1 1 0 1 1 1 1
1 0 0 0 1 0 0 0 0 1 0 0 0 0
1 0 0 1 1 0 0 1 1 1 0 0 1 1
1 0 1 0 1 0 1 0 0 1 0 1 0 0
1 0 1 1 1 0 1 1 1 1 0 1 1 1
1 1 0 0 1 1 0 0 0 1 0 1 0 0
1 1 0 1 1 1 0 1 1 1 0 1 1 1
1 1 1 0 1 1 1 0 0 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

VERILOG CODE
DESIGN BLOCK (DATAFLOW DESCRIPTION)

module adder_4bit(
input [3:0] a,b,
input c_in,
output [3:0] s,
output c_out);
assign {c_out,sum}=a+b+c_in;
endmodule

STIMULUS BLOCK

module adder_4bit_sb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg c_in;
// Outputs
wire [3:0] s;
wire c_out;
// Instantiate the Unit Under Test (UUT)
adder_4bit uut (
.a(a),
.b(b),
.c_in(c_in),
.s(s),
.c_out(c_out));

initial begin
a=4'b0000;b=4'b0000; c_in=0;
#10 a=4'b0001;b=4'b0001; c_in=1;
#10 a=4'b0010;b=4'b0010; c_in=0;
#10 a=4'b0011;b=4'b0011; c_in=1;
#10 a=4'b0100;b=4'b0100; c_in=0;
#10 a=4'b0101;b=4'b0101; c_in=1;
#10 a=4'b0110;b=4'b0110; c_in=0;
#10 a=4'b0111;b=4'b0111; c_in=1;
#10 a=4'b1000;b=4'b1000; c_in=0;
#10 a=4'b1001;b=4'b1001; c_in=1;
#10 a=4'b1010;b=4'b1010; c_in=0;
#10 a=4'b1011;b=4'b1011; c_in=1;
#10 a=4'b1100;b=4'b1100; c_in=0;
#10 a=4'b1101;b=4'b1101; c_in=1;
#10 a=4'b1110;b=4'b1110; c_in=0;
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#10 a=4'b1111;b=4'b1111; c_in=1;

end
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endmodule

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

RTL SCHEMATIC

TECHNOLOGY SCHEMATIC

OUTPUT WAVEFORM
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

ANALYSIS REPORT

1. Total Area
Device utilization summary:
Number of IOs: ______ out of _____ ______

2. Maximum Delay
Timing Details:
Maximum Delay: __________

3. Power Requirement
Total Power Dynamic Quiescent

15

RESULT: The 4-bit adder has been realized and simulated using verilog code and report has bee n
Page

generated for calculating total area, maximum delay and power requirement..

Dept. of ECE, MIT Thandavapura

21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

VIVA QUESTIONS –4 BIT ADDER

1. What is a 4-bit adder?

2. How many bits are there in the input and output of a 4-bit adder?
3. What is the significance of the carry-out (Cout) in a 4-bit adder?
4. How many full adders are required to implement a 4-bit adder?
5. Can you describe the operation of a full adder?
6. How would you test a 4-bit adder to ensure its correctness?
7. What are some common applications of 4-bit adders in digital systems?
8. How would you extend a 4-bit adder to support subtraction?

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

PROGRAM 02
32-BIT ALU

AIM
To design a Verilog model for 32-bit ALU supporting 4-Logical and 4-Arithmetic operations using
case statement and if statement and to generate a report for determining to tal area, maximum dela y
and power requirement.

THEORY

ALU stands for Arithmetic Logic Unit.An arithmetic- logic unit is the part of a central processing unit
that carries out arithmetic and logic operations on the operands. The inputs to an ALU are the data to
be operated on, called operands, and an opcode indicating the operation to be performed; the ALU's
output is the result of the performed operation.

Working of a 32-bit ALU:

Typically, the ALU has direct input and output access to the processor controller, main memor y
(random access memory or RAM in a personal computer) and input/output devices. Inputs and
outputs flow along an electronic path that is called a bus.

The input consists of an instruction word, that contains an opcode which tells the ALU what
operation to perform and the operands are used in the operation.

The output consists of a result that is placed in a storage register and settings that indicate whether
the operation was performed successfully.

The four basic arithmetic operations are: Addition (Finding the Sum; ‘+’), Subtraction (Finding the
difference; ‘-’), Multiplication (Finding the product; ‘×’ ), and Division (Finding the quotient; ‘÷’)
The basic Logical operations are: AND, OR, NOT, XOR, and NAND.
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

LOGIC SYMBOL

TRUTH TABLE

Consider A = 32’b0100 and B = 32’b0010

Opcode Operation Operator Result

000 Addition A+B 32’b0110
001 Subtraction A-B 32’b0010
010 Multiplication A*B 32’b1000
011 Division A/B 32’b0010
100 AND A&B 32’b0000
101 OR A|B 32’b0110
110 XOR A^B 32’b0110
111 NOT ~A 32’b1011

VERILOG CODE
DESIGN BLOCK (BEHAVIORAL DESCRIPTION)

module alu_4bit(
input [31:0] a,b,
input [2:0] opcode,
output reg[31:0] y);
always @ (a,b,opcode)
begin
case(opcode)
3'b000:y=a+b;
3'b001:y=a-b;
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3'b010:y=a*b;
3'b011:y=a/b;
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3'b100:y=a&b;

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

3'b101:y=a|b;
3'b110:y=~(a&b);
3'b111:y=a^b;
endcase
end
endmodule

STIMULUS BLOCK

module alu_4bit_sb;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg [2:0] opcode;
// Outputs
wire [31:0] y;
// Instantiate the Unit Under Test (UUT)
alu_4bit uut (.a(a), .b(b), .opcode(opcode), .y(y));
initial begin
a = 32'b0100;b =32'b0010;
opcode=3'b000;
#10 opcode=3'b001;
#10 opcode=3'b010;
#10 opcode=3'b011;
#10 opcode=3'b100;
#10 opcode=3'b101;
#10 opcode=3'b110;
#10 opcode=3'b111;
end
endmodule

RTL SCHEMATIC

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

OUTPUT WAVEFORM

ANALYSIS REPORT

1. Total Area
Device utilization summary:
Number of IOs: ______ out of _____ ______

2. Maximum Delay
Timing Details:
Maximum Delay: __________

3. Power Requirement
Total Power Dynamic Quiescent

20

RESULT: The 32-bit ALUhas been realized and simulated using verilog code and report has bee n
Page

generated for calculating total area, maximum delay and power requirement.

Dept. of ECE, MIT Thandavapura

21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

VIVA QUESTIONS – 32-BIT ALU

1. Expand ALU.
2. Explain the functioning of ALU.
3. Define opcode.
4. Define operand.
5. Explain the types of logical operators in digital system.
6. Explain the types of arithmetic operators in digital system.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

PROGRAM 03
LATCH AND FLIP-FLOP

1. SR LATCH AND SR FLIP-FLOP

AIM
To design a Verilog model for SR Latch and SR Flip-Flop and to generate a report for determining
total area, maximum delay and power requirement.

THEORY
SR is also called as Set (Logic 1) and Reset (Logic 0). SR latch affects the outputs as long as the
enable, E is maintained at ‘1’. For SR flip- flop a clock pulse is supplied to operate. If the flip- flop
works either with positive clock or negative clock.
Set and Reset condition: The output is set (Q = 1) when S = 1 and R = 0, and reset (Q = 0) when S =
0 and R = 1.
No change condition: The output is no change (Q = Q) when S = R = 0.
Invalid condition: The output is invalid (Q = X) when S = R = 1.

LOGIC SYMBOL

TRUTH TABLE

SR LATCH SR FLIP-FLOP
INPUTS OUTPUTS INPUTS OUTPUTS
En S R Q Qb ACTION Reset Clk S R Q Qb ACTION
0 X X 0 1 Reset 1 X X X 0 1 Reset
1 0 0 Q Qb No change 0 1 0 0 Q Qb No change
1 0 1 0 1 Reset 0 1 0 1 0 1 Reset
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1 1 0 1 0 Set 0 1 1 0 1 0 Set
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1 1 1 X X Invalid 0 1 1 1 X X Invalid

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

DESIGN BLOCK (BEHAVIORAL DESCRIPTION)

SR LATCH SR FLIP-FLOP
module SR_LATCH( module SR_FF(
input [1:0] SR, input [1:0] SR,
input en, input reset,clk,
output reg Q,Qb); output reg Q,Qb);
always @ (SR,en) always @ (posedge clk)
begin begin
if (en == 0) if (reset == 1)
Q=0; Q=0;
else else
begin begin
casex (SR) casex (SR)
2'b00:Q=Q; 2'b00:Q=Q;
2'b01:Q=0; 2'b01:Q=0;
2'b10:Q=1; 2'b10:Q=1;
2'b11:Q=1'bX; 2'b11:Q=1'bX;
endcase endcase
end end
Qb=~Q; Qb=~Q;
end end
endmodule endmodule

STIMULUS BLOCK

SR LATCH SR FLIP-FLOP
module SR_LATCH_SB; module SR_FF_SB;
// Inputs // Inputs
reg [1:0] SR; reg [1:0] SR;
reg en; reg reset;
// Outputs reg clk;
wire Q; // Outputs
wire Qb; wire Q;
// Instantiate the Unit Under Test (UUT) wire Qb;
SR_LATCH uut ( // Instantiate the Unit Under Test (UUT)
.SR(SR), SR_FF uut (
.en(en), .SR(SR),
.Q(Q), .reset(reset),
.Qb(Qb)); .clk(clk),
initial begin .Q(Q),
en=0;SR=2'b00; .Qb(Qb));
#10 en=1;SR=2'b00; initial begin
#10 en=1;SR=2'b01; clk=1;
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#10 en=1;SR=2'b10; forever #5 clk=~clk;

#10 en=1;SR=2'b11; end
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end initial begin

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

endmodule reset=1;SR=2'b00;
#10 reset=0;SR=2'b00;
#10 reset=0;SR=2'b01;
#10 reset=0;SR=2'b10;
#10 reset=0;SR=2'b11;
end
endmodule

RTL SCHEMATIC

TECHNOLOGY SCHEMATIC

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

OUTPUT WAVEFORM

1. SR LATCH

2. SR FLIP-FLOP

ANALYSIS REPORT (SR LATCH & SR FLIP FLOP)

1. Total Area
Device utilization summary:
Number of IOs: ______ out of _____ ______

2. Maximum Delay
Timing Details:
Maximum Delay: __________

3. Power Requirement
Total Power Dynamic Quiescent
25

RESULT: The SR Latch and Flip-Flop has been realized and simulated using verilog code and report
Page

has been generated for calculating total area, maximum delay and power requirement.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

2. JK LATCH AND JK FLIP-FLOP

AIM
To design a Verilog model for JK Latch and JK Flip-Flop and to generate a report for determining
total area, maximum delay and power requirement.

THEORY
The JK represents an advancement over the SR by resolving the invalid state issue inherent in the SR
latch / flip- flop through the inclusion of feedback. The JK originally named after its inventor, Jack
Kilby, stands for Jack Kilby latch / flip-flop.
JK latch affects the outputs as long as the enable, E is maintained at ‘1’. For JK flip- flop a clock
pulse is supplied to operate. If the flip-flop works either with positive clock or negative clock.
Set and Reset condition: The output is set (Q = 1) when J = 1 and K = 0, and reset (Q = 0) when J = 0
and K = 1.
No change condition: The output is no change (Q = Q) when J = K = 0.
Toggle condition: The output is toggle (Q = ~Q) when J = K = 1.

LOGIC SYMBOL

TRUTH TABLE

JK LATCH JK FLIP-FLOP
INPUTS OUTPUTS INPUTS OUTPUTS
En J K Q Qb ACTION Reset Clk J K Q Qb ACTION
0 X X 0 1 Reset 1 X X X 0 1 Reset
1 0 0 Q Qb No change 0 1 0 0 Q Qb No change
1 0 1 0 1 Reset 0 1 0 1 0 1 Reset
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1 1 0 1 0 Set 0 1 1 0 1 0 Set
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1 1 1 Qb Q Toggle 0 1 1 1 Qb Q Toggle

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

DESIGN BLOCK (BEHAVIORAL DESCRIPTION)

JK LATCH JK FLIP-FLOP
module JK_LATCH( module JK_FF(
input [1:0] JK, input [1:0] JK,
input en, input reset,clk,
output reg Q,Qb); output reg Q,Qb);
always @ (JK,en) always @ (posedge clk)
begin begin
if (en == 0) if (reset == 1)
Q=0; Q=0;
else else
begin begin
case(JK) case (JK)
2'b00:Q=Q; 2'b00:Q=Q;
2'b01:Q=0; 2'b01:Q=0;
2'b10:Q=1; 2'b10:Q=1;
2'b11:Q=~Q; 2'b11:Q= ~Q;
endcase endcase
end end
Qb=~Q; Qb=~Q;
end end
endmodule endmodule

STIMULUS BLOCK

JK LATCH JK FLIP-FLOP
module JK_LATCH_SB; module JK_FF_SB;
// Inputs // Inputs
reg [1:0] JK; reg [1:0] JK;
reg en; reg reset;
// Outputs reg clk;
wire Q; // Outputs
wire Qb; wire Q;
// Instantiate the Unit Under Test (UUT) wire Qb;
JK_LATCH uut ( // Instantiate the Unit Under Test (UUT)
.JK(JK), JK_FF uut (
.en(en), .JK(JK),
.Q(Q), .reset(reset),
.Qb(Qb)); .clk(clk),
initial begin .Q(Q),
en=0;JK=2'b10; .Qb(Qb));
#10 en=1;JK=2'b00; initial begin
#10 en=1;JK=2'b01; clk=1;
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#10 en=1;JK=2'b10; forever #5 clk=~clk;

#10 en=1;JK=2'b11; end
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end initial begin

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endmodule reset=1;JK=2'b10;
#10 reset=0;JK=2'b00;
#10 reset=0;JK=2'b01;
#10 reset=0;JK=2'b10;
#10 reset=0;JK=2'b11;
end
endmodule

RTL SCHEMATIC

TECHNOLOGY SCHEMATIC

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

OUTPUT WAVEFORM

1. JK LATCH

2. JK FLIP-FLOP

ANALYSIS REPORT (JK LATCH & JK FLIP-FLOP)

1. Total Area
Device utilization summary:
Number of IOs: ______ out of _____ ______

2. Maximum Delay
Timing Details:
Maximum Delay: __________

3. Power Requirement

Total Power Dynamic Quiescent

29

RESULT: The JK Latch and Flip-Flop has been realized and simulated using verilog code and report
Page

has been generated for calculating total area, maximum delay and power requirement.

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

3. D LATCH AND D FLIP-FLOP

AIM
To design a Verilog model for D Latch and D Flip-Flop and to generate a report for determining tota l
area, maximum delay and power requirement.

THEORY
D represents “Delay” or “Data”. They are used to store 1 – bit binary data. D latch affects the outputs
as long as the enable, E is maintained at ‘1’. For D flip-flop a clock pulse is supplied to operate. If the
flip-flop works either with positive clock or negative clock.
Set and Reset condition: The output is set (Q = 1) when D = 1, and reset (Q = 0) when D = 0.

LOGIC SYMBOL

TRUTH TABLE

D LATCH D FLIP-FLOP
INPUTS OUTPUTS INPUTS OUTPUTS
En D Q Qb ACTION Reset Clk D Q Qb ACTION
0 X 0 1 Reset 1 X X 0 1 Reset
1 0 0 1 Reset 0 1 0 0 1 Reset
1 1 1 0 Set 0 1 1 1 0 Set

DESIGN BLOCK (BEHAVIORAL DESCRIPTION)

D LATCH D FLIP-FLOP
module D_LATCH( module D_FF(
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input D, en, input D,reset,clk,

output reg Q,Qb); output reg Q,Qb);
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always @ (D,en) always @ (posedge clk)

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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

begin begin
if (en == 0) if (reset == 1)
begin begin
Q=0; Q=0;
Qb=~Q; Qb=~Q;
end end
else else
begin begin
Q=D; Q=D;
Qb=~Q; Qb=~Q;
end end
end end
endmodule endmodule

STIMULUS BLOCK

D LATCH D FLIP-FLOP
module D_LATCH_SB; module D_FF_SB;
// Inputs // Inputs
reg D, en; reg D, reset, clk;
// Outputs // Outputs
wire Q; wire Q;
wire Qb; wire Qb;
// Instantiate the Unit Under Test (UUT) // Instantiate the Unit Under Test (UUT)
D_LATCH uut ( D_FF uut (
.D(D), .D(D),
.en(en), .reset(reset),
.Q(Q), .clk(clk),
.Qb(Qb)); .Q(Q),
initial begin .Qb(Qb));
en=0;D=0; initial begin
#10 en=1;D=0; clk=1;
#10 en=1;D=1; forever #5 clk=~clk;
end end
endmodule initial begin
reset=1;D=0;
#10 reset=0;D=0;
#10 reset=0;D=1;
end
endmodule
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

RTL SCHEMATIC

TECHNOLOGY SCHEMATIC

OUTPUT WAVEFORM

1. D LATCH

2. D FLIP-FLOP
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

ANALYSIS REPORT (D LATCH & D FLIP-FLOP)

1. Total Area
Device utilization summary:
Number of IOs: ______ out of _____ ______

2. Maximum Delay
Timing Details:
Maximum Delay: __________

3. Power Requirement
Total Power Dynamic Quiescent

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RESULT: The D latch and Flip-Flop has been realized and simulated using verilog code and report
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has been generated for calculating total area, maximum delay and power requirement.

Dept. of ECE, MIT Thandavapura

21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

PROGRAM 04
4-BIT BOOTH’S ALGORITHM

AIM
To design a Verilog model for 4-bit Booth’s algorithm and to generate a report for determining tota l
area, maximum delay and power requirement.

THEORY
Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement
representation in efficient way, i.e., less number of additions/subtractions required. It is also used to
speed up the performance of the multiplication process.

FLOWCHART OF BOOTH’S ALGORITHM

Start

A = 0; Accumulator,
P = 0; Previous bit,
X = Multiplicand, Y = Multiplier, N = Count

10 Y0,P 01

00, 11

A=A-X A=A+X

Arithmetic Right Shift

No N=0? Yes
End
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Dept. of ECE, MIT Thandavapura

21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

WORKING ON THE BOOTH ALGORITHM

The following flowchart outlines the basic steps of the algorithm:

Step 1: Begin by setting the value of the register “A = 0” to the first operand and the value of the
previous state register “P = 0” to the second operand.
Step 2: Check the value of the Least Significant Bit (LSB) of the multiplier “Y” i.e. Y0 and compare
with the value of register “P”, if
 Y0, P = 00 or 11 – Perform Arithmetic Right Shift
 Y0, P = 10 perform A = A – X and then Arithmetic Right Shift
 Y0, P = 01 perform A = A + X and then Arithmetic Right Shift
Step 3: Check if the value of Count “N = 0”, If it is, the algorithm is complete and the value in the
register “Y” is the result. If the value is not zero, go back to step 2.

OPERATION

Example 1: 4 * 2 = 8
Where X = 4 = 0100 and Y = 2 = 0010
Step A Y P Operation
0 0000 0010 0 Initial
1 0000 0001 0 00 = Arithmetic Right Shift
10 = A = A-X
-X = 2’s complement of X
X = 0100
1’s complement = 1011
1100 0001 0 + 1
2
-X = 2’s complement = 1100
A =A–X
A = 0000 + 1100 = 1100

1110 0000 1 Arithmetic Right Shift

01 = A = A+ X
0010 0000 1 A = 1110 + 0100 = 0010
3
0001 0000 0 Arithmetic Right Shift
4 0000 1000 0 00 = Arithmetic Right Shift
Output is Y = 1000 = 8
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

Example 2: -5 * 4 = -20
Where X = -5 (2’s complement) = 1011 and Y = 4 = 0100
Step A Y P Operation
0 0000 0100 0 Initial
1 0000 0010 0 00 = Arithmetic Right Shift
2 0000 0001 0 00 = Arithmetic Right Shift
10 = A = A - X
0101 0001 0 -X = 0101
3 A = 0000 + 0101 = 0101
0010 1000 1 Arithmetic Right Shift
01 = A = A + X
1101 1000 1
4 A = 0010 + 1011 = 1101
1110 1100 0 Arithmetic Right Shift
Verification: 11101100
1’s complement: 00010011
+ 1
2’s complement: 00010100 (-21)

DESIGN BLOCK (BEHAVIORAL DESCRIPTION)

module booth_multiplier(
input signed [3:0] X, Y,
output reg signed [7:0] Z);
reg [1:0] temp;
integer N;
reg P;
reg [3:0] X1;
always @ (X, Y)
begin
Z = 8‘b00000000;
P = 0;
for (N = 0; N < 4; N = N + 1)
begin
temp = {Y[N], P};
X1 = - X;
case (temp)
2'd2 : Z [7 : 4] = Z [7 : 4] + X1;
2'd1 : Z [7 : 4] = Z [7 : 4] + X;
endcase
Z = Z >>> 1;
Z[7]=Z[6];
P = Y[N];
end
end
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endmodule
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21ECL66 – VLSI LABORATORY ACADEMIC YEAR 2023-24

STIMULUS BLOCK

module booth_tb;
reg [3:0] X;
reg [3:0] Y;
wire [7:0] Z;
booth_multiplier uut (.X(X),.Y(Y),.Z(Z));
initial begin
X = 4'b0100; Y = 4'b0010;
#10 X = -4’b0101; y = 4’b1000;
end
endmodule

RTL SCHEMATIC

OUTPUT WAVEFORM

ANALYSIS REPORT
1. Total Area
Device utilization summary:
Number of IOs: ______ out of _____ ______

2. Maximum Delay
Timing Details:
Maximum Delay: __________

3. Power Requirement
Total Power Dynamic Quiescent
37

RESULT: The 4-bit Booth’s algorithm has been realized and simulated using verilog code and report
Page

has been generated for calculating total area, maximum delay and power requirement.

Dept. of ECE, MIT Thandavapura