Verilog Interview Questions

Part-2
31. How does Verilog handle race conditions, and how can
you avoid them?
Race conditions occur when multiple signals are updated in
the same simulation cycle, leading to non-deterministic
results. To avoid them, use non-blocking (<=) assignments in
sequential logic and blocking (=) assignments in
combinational logic.
32. What is a finite state machine (FSM) and how is it
implemented in Verilog?
An FSM is a model of computation with defined states and
transitions. It's implemented using a combination of always
blocks and case statements driven by a clock and input
conditions.
33. What are the types of FSMs and how do they differ?
Moore and Mealy machines: Moore's outputs depend only on
state, Mealy's outputs depend on both state and input.
34. How can you infer a latch unintentionally in Verilog?
If not all conditions in an if or case statement assign a value to
a variable in a combinational block, a latch is inferred.
35. How do you prevent latch inference in Verilog?
Always assign default values in combinational blocks or use
full-case constructs to cover all input conditions.
36. What is the difference between a function and a task in
Verilog?
A function returns a single value and executes in zero
simulation time. A task can return multiple values and
consume simulation time.
37. What is synthesizable and non-synthesizable Verilog
code?
Synthesizable code can be mapped to hardware. Non-
synthesizable constructs (e.g., #delay, file I/O) are simulation-
only.
38. What is the purpose of the initial block in testbenches?
The initial block is used to apply a stimulus, monitor outputs,
and control the simulation flow.
39. Explain clock gating and how it is implemented in
Verilog.
Clock gating saves power by disabling clock to inactive
modules. It’s implemented using conditional clock enable
logic or gated clock cells.
40. How do you model a tri-state buffer in Verilog?
//Use conditional assignments:
//Verilog code:
assign out = enable? data: 1'bz;
41. What is metastability, and how do you avoid it?
Metastability occurs when a flip-flop's input changes too close
to the clock edge. Use synchronizer circuits (e.g., double flip-
flops) to reduce risk.
42. What is a synchronizer in digital design?
A synchronizer ensures safe transfer of signals between
different clock domains, usually implemented with two or
more cascaded flip-flops.
43. How do you perform clock domain crossing (CDC) in
Verilog?
Use synchronizers for control signals and FIFOs for data
signals when transferring between asynchronous clock
domains.
44. What is the difference between posedge clk and @
(posedge clk)?
posedge clk is part of the sensitivity list for always blocks,
while @ (posedge clk) can also be used in procedural delay or
control statements.
45. How do you write a parameterized module in Verilog?
//Verilog Code:
module my_module #(parameter WIDTH = 8) (input
[WIDTH-1:0] in, output [WIDTH-1:0] out);
46. What are the uses of localparam in Verilog?
localparam defines constants within a module that cannot be
overridden during instantiation, unlike parameter.
47. How can you model memory in Verilog?
//Using arrays:
//Verilog Code:
reg [7:0] mem_array [0:255];
48. How do you synthesize a ROM or RAM using Verilog?
Write memory code using arrays and control access using
clocked always blocks; synthesis tools infer memory blocks.
49. What are the different types of delays in Verilog?
Inertial and transport delays in simulation; setup, hold,
propagation delays in hardware timing.
50. What is the def param statement used for?
def param is used to override parameters during module
instantiation, but is discouraged in favor of #() syntax.
51. What are the key differences between Verilog and
VHDL?
Verilog is C-like, concise, and popular in the U.S.; VHDL is
verbose, strongly typed, and popular in Europe. Both are used
for RTL design.
52. What is the purpose of the disable statement in
Verilog?
Used to terminate a named block prematurely, typically within
loops or conditional logic in simulation.
53. What is meant by posedge and negedge, and how are
they used in synthesis?
They indicate edge sensitivity in sequential circuits. Only one
edge should be used for synthesis to avoid glitches.
54. How do you model a counter in Verilog?
Using a sequential always block with posedge clk, increment
or reset a register based on control inputs.
55. How do you detect overflow in an adder circuit using
Verilog?
//By checking carry into and out of the MSB:
//Verilog Code:
assign overflow = (a[MSB] & b[MSB] & ~sum[MSB]) |
(~a[MSB] & ~b[MSB] & sum[MSB]);
56. What is the difference between a wire and a tri data
type?
A wire can have a single driver, while tri allows multiple
drivers and resolves using wired logic.
57. How do you model a shift register in Verilog?
//Use a sequential block and bit slicing:
//Verilog Code:
reg [3:0] shift;
always @(posedge clk) shift <= {shift[2:0], data_in};
58. How do you prioritize conditions in a case statement?
Use case z or case x for pattern matching, but to prioritize, use
if-else instead of case.
59. What is a blocking vs non-blocking assignment
hazard?
Mixing = and <= in the same always block or for the same
signal can cause unintended simulation behaviour due to
timing mismatch.
60. How do you write synthesizable code for an edge
detector in Verilog?
//Use two flip-flops to store current and previous signal states
and compare them:
//Verilog Code:
reg sig_d, edge;
always @(posedge clk) begin
sig_d <= sig;
edge <= sig & ~sig_d;
end