International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014

VHDL Design and FPGA Implementation of

Reed Solomon Encoder and Decoder for RS (7,3)
Diplaxmi Chaudhari , Mayura Bhujade, Pranali Dhumal

 basically used for encoding purpose. The coefficients of the

Abstract— In this paper, Reed-Solomon (RS) encoder and RS generator polynomial are nothing but the multiplier
decoder for RS (7,3) codec and their hardware implementation coefficients. After that, encoding is achieved by adding the
in Actel ProASIC3 (Field Programmable Gate Array (FPGA) remainder of a GF polynomial division into the message. For
kit is analyzed. RS codes are subclass of non binary cyclic error implementation of this division method, linear feedback
correcting block codes which can correct burst errors at the
Shift Register (LFSR) technique is used [7]. At the decoder,
receiver. The RS code provides a wide range of code rates
which can be chosen to obtain the optimum performance. the syndrome calculation of the received codeword is carried
Parity symbols are generated in the encoder using a generator out. Then we find error locations using Chien algorithm and
polynomial by shift register concept and then concatenated error magnitudes using Forney algorithm. Further Massey
with the input message symbols. RS decoder determines the Berlekamp is used to calculate coefficients of error locator
location and magnitude of errors in the received polynomial polynomial for error locations and coefficients of error
caused due to noise while communication. For this, efficient evaluator polynomial for error values.
decoding techniques like Chien, Forney and Berlekamp RS codes have a widespread use to provide error
Massey algorithms are used by the decoder. The thesis correction especially for burst errors. This feature has been
proposes RS encoding and decoding algorithm, synthesis and
an important factor in adopting RS codes in many practical
simulation results of RS encoder using Very High Speed
hardware description Language (VHDL) and ProASIC3
applications such as wireless communication system, cable
FPGA. modem, computer memory etc. The paper covers RS theory
in section II. Architecture of RS encoder is discussed in brief
in section III. Section IV includes RS decoding algorithms.
Index Terms— Reed Solomon (RS), FPGA, Chien, Forney, Section V provides results of RS encoder. Conclusion is
VHDL Syndrome calculator, Key Equation Solver ( KES) discussed in section VI.

II. RS BASICS
I. INTRODUCTION The RS code is represented as RS (n,k) where n is code size in
In practical communication system data or information symbols, k is message size in symbols and 2t is number of
may get corrupted by noise during transmission. Now a day parity symbols (n-k).
as demand is continuously increasing for development of
reliable telecommunication and wireless systems, it is
important to detect and correct errors in the information
received over communication channels. Therefore error
control coding is important in communication system design
for various applications.
Reed Solomon codes [1] are systematic linear block error Figure 1: Structure of RS code word [2]
correcting codes and these are sub class of non binary BCH The relation between symbol size m, and code size n is given
error correcting codes. RS codes operate on the information by
by dividing the message stream into blocks of data. Then
redundancy can be added as per block depending only on the (1)
current inputs. The symbols are elements of a finite field or
Galois Field (GF). Galois field is used for encoding and For RS(7,3) symbol size is m=3 and maximum correcting
decoding of Reed Solomon codes. GF multipliers are capability is t=2, given by

Manuscript received February 2014.

[5] (2)
Diplaxmi Sunil Chaudhari, Electronics and Telecommunication, Pune
University, Rajarshi Shahu College of Engg. Pune, India,+919028973464
Firstly primitive polynomial f(X) is used to define Galois
Mayura Ashok Bhujade, Electronics and Telecommunication, Pune field element which is given as GF(2m). An irreducible
University, Rajarshi Shahu College of Engg. Pune,India,+919021802577 polynomial is said to be primitive, if the smallest positive
integer n for which f(X) divides Xn+1 is n=2m - 1. For (7,3)
Pranali Abhay Dhumal, Electronics and Telecommunication, Pune
University, Rajarshi Shahu College of Engg. Pune, India,+919595689264
code we use primitive polynomial which is given as 1+X+X3.

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ISSN: 2278 – 7798
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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014

III. RS ENCODER Equations for shift registers:

A (7,3) cyclic code is specified by set of code word
polynomials of degree 6 or less, which contains minimum (6)
degree of n-k i.e. 7-3=4 as a factor. This factor is denoted by
g(X) which is called as generator polynomial of the code.
That is the highest degree of generator polynomial is equal to (7)
number of parity bits in the code. The g(X) and the parity
check polynomial h(X) are factors of 1+Xn. A y factor of
1+Xn can be used as generator polynomial [8]. (8)

(9)
[8]
For t=2, g(X) has 2t=n-k=4 roots. Table 1: Contents of shift register

[8] Msg R3 R2 R1 R0
By solving we get, Symbol
Initially 0 0 0 0
(3)
The message polynomial is α α4 α α2 α4

(4) α3 α4 α0 α5 α2

Transmitted codeword is α5 α α4 α4 α3

[5] (5)
Transmitted symbol:

Message symbols parity symbols

IV. RS DECODER
In communication system while transmitting input message
codeword through channel noise may get added to it. Thus
RS decoding [4], [5] includes detection and correction of
errors at the receiver. Received codeword after being
corrupted can be represented as

(10)
Figure 2: Architecture of RS Encoder
where, e(x) is error polynomial with same degree as c(x) and
r(x). The transmitted message c(x) is then recovered by
The encoder reads three message symbols, computes the adding received message, r(x) to error polynomial, e(x) as
parity symbols as 7-3=4 for total n symbols. The RS encoder shown in equation 11
consists of 2t linear feedback shift register [3] where each
register is of 3 bits size. Generator polynomial coefficients
are given to the multiplier coefficient. The coefficients (11)
produced will be symbols such that polynomials will exactly
divide the parity polynomial. The process continues till all RS decoding technique involves following steps:
the 3 symbols of m(x) are given as input to the encoder. Thus 1. Calculating the syndromes from the received
during this time, the input switch is enabled while keeping codeword.
the output i.e. parity switch disabled. For each clock cycle 2. Computing the error locator polynomial.
parity symbols are generated. After the last message symbol 3. Finding the error locations.
is given as input to the encoder and parity symbols are 4. Computing error values.
obtained, the output switch is enabled. In this way we obtain
the parity symbols at the last clock cycle. Hence a new block
can be started at the (n+1)th clock pulse.

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International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014

V. SYNTHESIS RESULTS

Figure 4: Objects of RS Encoder

Figure 3: Architecture of RS decoder [3]

RS decoder consists of following blocks:

1) Syndrome calculator S(x) :

The syndrome is the result of a parity check performed on
received polynomial to determine whether received
codeword is a valid member of codeword set. Syndrome
values will be calculated as follows

(12)

S(x)=0 indicates, there is no error in received codeword and

if S(x)≠0 then there is error in the received codeword.

2) Key Equation Solver (KES):

This is the main block of RS decoder which solves a set of 2t
linearly dependent equations. Two key equations i.e. error
locator polynomial σ(x) and error evaluator polynomial Ω(x)
are generated from the syndrome polynomial. By solving
equation 13, we can determine above two unknown
polynomials σ(x) and Ω(x). Figure 5: Synthesis result of RS Encoder

(13)

The two techniques to solve key equations are Berlekamp

Massey algorithm [6] and Euclidean algorithm. We have
used Berlekamp Massey algorithm as it has least hardware
complexity as compared to Euclidean algorithm.

3) Forney algorithm:
Forney algorithm calculates error values ei by using error
locator polynomial σ(x) and error magnitude polynomial Figure 6: Gate level schematic of RS Encoder
Ω(x).

4) Chien search: VI. HARDWARE IMPLEMENTATION

This block is used to find the roots of σ(x) which are
ProASIC3 is the third generation family of Microsemi
reciprocals of error locations. When Chien sum is zero then FPGAs. ProASIC3 has non-volatile flash technology with
there is error in that particular location. In this way location low power, secure and single chip solution. The .pdb file
of error can be computed easily using Chien search. generated by Actel libero software is dumped into ProASIC3
A3P250 208FQGA device using FlashPro programming
software and verified parity bits on Led’s given on the FPGA

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ISSN: 2278 – 7798
All Rights Reserved © 2014 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014

board [9]. [8] Petrus Mursanto, ―Generic Reed Solomon Encoder”, Makara, Sains,
Vol. 10, No.2, pp. 58-62, November 2006.
[9] ― Microsemi ProASICs flash family FPGAs datasheet‖, Revision 13.

Diplaxmi Chaudhari was born in Pune, India on

12th June 1993. She is currently pursuing the
under graduate course Bachelors of Engineering
in Electronics and telecommunication at
Rajarshi Shahu College of Engineering.

Author’s Photo
Mayura Bhujade was born in Pune, India on 10th
December 1992. She is currently pursuing the
under graduate course Bachelors of Engineering
in Electronics and telecommunication at
Figure 7: ProASIC3 FPGA kit Rajarshi Shahu College of Engineering.

VII. CONCLUSION Author’s Photo

Pranali Dhumal was born in Pune, India on 17th
In this paper, design of RS (7,3) encoder and decoder and its
May 1993. She is currently pursuing the under
implementation on Actel ProASIC kit is analyzed. We have graduate course Bachelors of Engineering in
verified the parity symbols mathematically using Linear Electronics and telecommunication at Rajarshi
Feedback Shift Register (LFSR) and the synthesized results Shahu College of Engineering.
obtained on Libero software. At the encoder, we have
successfully obtained the parity symbols for given message
symbols by dumping code into FPGA kit. Thus we have Author’s Photo
performed decoding using Berlekamp-Massey algorithm. All
the results are simulated using Actel Libero software.

ACKNOWLEDGMENT
At the first we would like to thank our guide Prof.S.C.Wagaj
for giving us opportunity and support to work on this project.
We express sincere thanks to our friends who helped us
directly and indirectly for this work.
.
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