Sequential Circuit Design

ELEC2141: Digital Circuit Design

Dr. Beena Ahmed

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 Previously…
Sequential circuit analysis
State equations
State tables
State diagrams
Moore and Mealy sequential circuits
State minimization
State assignment

2
 This lecture…
Sequential circuit design procedure
Finding state diagrams and tables
Designing with D, JK, T flip flops
Circuit synthesis

Reading: Mano - Chapter 4: 4.5

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Sequential circuit design
Procedure
1. Derive the state diagram from the word description and
specifications of the desired operation
2. Reduce the number of states
3. Assign binary values to the states
4. Obtain the binary-coded state table
5. Choose the type of flip-flops to be used
6. Derive the simplified flip-flop input equations and output
equations
7. Draw the logic diagram
Sequential circuit design
Procedure
1. Derive the state diagram from the word description and
specifications of the desired operation
2. Reduce the number of states
3. Assign binary values to the states
4. Obtain the binary-coded state table
5. Choose the type of flip-flops to be used
6. Derive the simplified flip-flop input equations and output
equations
7. Draw the logic diagram
Sequential circuit design example
We need to design a circuit that detects a sequence of
three or more consecutive 1’s in a string of bits coming
from an input line (i.e. the input is in serial bit stream)
Sequential circuit design example
We need to design a circuit that detects a sequence of
three or more consecutive 1’s in a string of bits coming
from an input line (i.e. the input is in serial bit stream)
1. State diagram and state table

Present Next state Output

state
X =0 X =1 X =0 X =1
Sequential circuit design example

2. State reduction

Present Next state Output

state
B
X =0 X =1 X =0 X =1
C
A A B 0 0
D B A C 0 0
A B C C A D 0 0
D A D 1 1
Sequential circuit design example
Present Next state Output
3. State assignment state
X =0 X =1 X =0 X =1
0 1 A A B 0 0

0
B A C 0 0
A/0 D/1
C A D 0 0

1
0 D A D 1 1
1
0

1
B/0 C/0
Sequential circuit design example
4. Binary coded state diagram and table
0 1
Present Next state Output
state
0
00/0 11/1 X =0 X =1 X =0 X =1
A A B 0 0
0
1 1
0 B A C 0 0

1 C A D 0 0
01/0 10/0
D A D 1 1

Present Next state Output

state
X =0 X =1 X =0 X =1
0 0
0 0
0 0
1 1
Sequential circuit design example
5. Synthesis using D flip-flops
The next state equation is Present Input Next state Output
state
the same as the D flip-
Y Z X 𝒀𝒀 𝒕𝒕 + 𝟏𝟏 𝒁𝒁 𝒕𝒕 + 𝟏𝟏 F
flop input equation
(taking flip flops Y and Z)
𝑫𝑫𝒀𝒀 = 𝒀𝒀 𝒕𝒕 + 𝟏𝟏
𝑫𝑫𝒁𝒁 = 𝒁𝒁 𝒕𝒕 + 𝟏𝟏
Present Next state Output
state
X =0 X =1 X =0 X =1
00 00 01 0 0
01 00 10 0 0
10 00 11 0 0
11 00 11 1 1
Sequential circuit design example
ZX
Y 00 01 11 10 Present Input Next state Output
state
0
DY Y Z X 𝒀𝒀 𝒕𝒕 + 𝟏𝟏 𝒁𝒁 𝒕𝒕 + 𝟏𝟏 F
1
0 0 0 0 0 0
ZX 0 0 1 0 1 0
Y 00 01 11 10
0 1 0 0 0 0
0
DZ 0 1 1 1 0 0
1 1 0 0 0 0 0
1 0 1 1 1 0
ZX
Y 00 01 11 10 1 1 0 0 0 1
0 1 1 1 1 1 1
F
1
Sequential circuit design example
6. Flip flop equations
𝑫𝑫𝒀𝒀 = 𝑿𝑿𝑿𝑿 + 𝒀𝒀𝒀𝒀
�
𝑫𝑫𝒁𝒁 = 𝑿𝑿𝑿𝑿 + 𝒀𝒀𝒁𝒁
𝑭𝑭 = 𝒀𝒀𝒀𝒀

7. Logic diagram

X A
Y
A

B
Clock
Excitation Tables
When D flip-flops are employed, the input equations are
obtained directly from the next state
However, for JK and T flip-flops, the input equations
need to be derived indirectly from the state table
An excitation table that lists the required inputs for a
given change of state in state table is thus needed
Excitation Tables
Characteristic table for JK flip-flop

J K Q(t+1) Characteristic table for T flip-flop

0 0 Q(t) T Q(t+1)
0 1 0 0 Q(t)
1 0 1 1 Q(t)
1 1 Q(t)

Excitation table for JK flip-flop Excitation table for T flip-flop

Q(t) Q(t+1) J K Q(t) Q(t+1) T
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1
 Synthesis using JK flip-flops
The excitation table is used to obtain the required inputs
from the state table
For this design problem:
Present Input Next state Flip-Flop Inputs
state

Y Z X 𝒀𝒀 𝒕𝒕 + 𝟏𝟏 𝒁𝒁 𝒕𝒕 + 𝟏𝟏 JY KY JZ KZ Q(t) Q(t+1) J K
0 0 0 0 0 0 0 0 X
0 0 1 0 1 0 1 1 X
0 1 0 1 0 1 0 X 1
0 1 1 0 1 1 1 X 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
 Synthesis using JK flip-flops
The required JK input equations can then be obtained
from the state table
ZX JY
Present Input Next state Flip-Flop Inputs Y 00 01 11 10
state
0
Y Z X 𝒀𝒀 𝒕𝒕 + 𝟏𝟏 𝒁𝒁 𝒕𝒕 + 𝟏𝟏 JY KY JZ JZ
1
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
ZX
KY
0 1 0 1 0 1 X X 1
Y 00 01 11 10
0 1 1 0 1 0 X X 0
0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X 1

1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
 Synthesis using JK flip-flops
The required JK input equations can then be obtained
from the state table
ZX JZ
Present Input Next state Flip-Flop Inputs Y 00 01 11 10
state
0
Y Z X 𝒀𝒀 𝒕𝒕 + 𝟏𝟏 𝒁𝒁 𝒕𝒕 + 𝟏𝟏 JY KY JZ JZ
1
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
ZX
KZ
0 1 0 1 0 1 X X 1
Y 00 01 11 10
0 1 1 0 1 0 X X 0
0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X 1

1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
Synthesis using JK flip-flops
𝑱𝑱𝒀𝒀 =
𝑲𝑲𝒀𝒀 =
𝑱𝑱𝒁𝒁 =
𝑲𝑲𝒁𝒁 =
Logic diagram

X A
J
C
K

J B
C
K

Clock
Synthesis using T flip-flops
Design a three-bit counter consisting of three T flip-flops
that can count in binary form from 0 to 7
State diagram
111
000 110

001 101

010 100
011
Synthesis using T flip-flops
State Table
Present Next state Flip-Flop
state Inputs
A B C 𝑨𝑨 𝒕𝒕 + 𝟏𝟏 𝑩𝑩 𝒕𝒕 + 𝟏𝟏 𝑪𝑪 𝒕𝒕 + 𝟏𝟏 TA TB TC
0 0 0 Q(t) Q(t+1) T
0 0 0
0 0 1
0 1 1
0 1 0
1 0 1
0 1 1
1 1 0
1 0 0
1 0 1
1 1 0
1 1 1
Synthesis using T flip-flops
Present Next state Flip-Flop
state Inputs TA
BC
A B C 𝑨𝑨 𝒕𝒕 + 𝟏𝟏 𝑩𝑩 𝒕𝒕 + 𝟏𝟏 𝑪𝑪 𝒕𝒕 + 𝟏𝟏 TA TB TC A 00 01 11 10

0 0 0 0 0 1 0 0 1 0
0 0 1 0 1 0 0 1 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
TB
1 0 0 1 0 1 0 0 1 BC
A 00 01 11 10
1 0 1 1 1 0 0 1 1
0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1 1

BC
A 00 01 11 10
TC 0

1
Synthesis using T flip-flops
𝑻𝑻𝑨𝑨 = Logic diagram
𝑻𝑻𝑩𝑩 = T A
C

𝑻𝑻𝑪𝑪 =

T B
C

1 T C
C

Clock