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Spring - 2025 - Tutorial 06 PDF

Verilog is a hardware description language used for modeling electronic systems, enabling designers to create complex circuits from simple logic gates to processors. It operates at three levels of abstraction: gate level, data-flow, and behavioral modeling, each providing different perspectives on circuit design. Additionally, Verilog includes modules, data types, operators, procedural blocks, control structures, tasks, and functions to facilitate the design and simulation of electronic circuits.

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9 views5 pages

Spring - 2025 - Tutorial 06 PDF

Verilog is a hardware description language used for modeling electronic systems, enabling designers to create complex circuits from simple logic gates to processors. It operates at three levels of abstraction: gate level, data-flow, and behavioral modeling, each providing different perspectives on circuit design. Additionally, Verilog includes modules, data types, operators, procedural blocks, control structures, tasks, and functions to facilitate the design and simulation of electronic circuits.

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Atabek Isakov
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© © All Rights Reserved
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Tutorial 06

Introduction to Verilog

Verilog is a hardware description language (HDL) used to model electronic systems. It allows
designers to describe the structure and behavior of electronic circuits, which can then be
synthesized into actual hardware.

Design Complex Systems: Verilog is used to design everything from simple logic
gates to complex processors.
Industry Standard: Widely used in the industry for FPGA and ASIC design.
Simulation: Before physical implementation, designs can be simulated to ensure
correctness.

Verilog HDL is commonly used for design of both Field programmable gate arrays(FPGA)
and Application-specific Integrated Circuits(ASIC). There are mainly three levels of abstraction
for writing in Verilog:

Gate Level Modeling


If a circuit is represented completely using basic gates it is called gate level modeling. For
example refer to the below circuit of half adder where we can represent it simply using the AND
and XOR gates. This level of abstraction involves describing the circuit using primitive logic gates
such as AND, OR, XOR, etc. This level provides a detailed representation of the circuit's structure
and logic.

module half_adder(input a,b, output sum,carry);


xor x1(sum, a, b);
and a1(carry, a, b);
endmodule
Data-flow Modeling

Here in this level of abstraction we make use of the functions that define the working of the
circuit instead of it's gate structure. This abstraction level mainly focuses on the flow of data
through the circuit logic gates or functional expressions.

module half_adder(input a,b, output sum,carry);


assign sum = a ^ b;
assign carry = a & b;
endmodule

Behavioral Modeling
This is the highest level of abstraction in Verilog. At this level the designers describe the
functionality of the circuit without specifying the functionality and structure of the digital circuit.
This modeling will be helpful because it focuses on what the circuit should do rather than how it
should be implemented.

module half_adder(input a,b, output reg sum,carry);


always@(*)
begin
sum = a ^ b;
carry = a & b;
endmodule
AND gate in different levels of abstraction in Verilog
Behavioral Level: High-level abstraction, focusing on the behavior without worrying
about implementation details.
module and_gate_behavioral (
input A,
input B,
output reg Y
);
always @(*) begin
if (A && B)
Y = 1;
else
Y = 0;
end
endmodule

Dataflow Level: Uses expressions to describe how data flows through the circuit.
module and_gate_dataflow (
input A,
input B,
output Y
);
assign Y = A & B; // Dataflow description of AND operation
endmodule

Gate-level: Specifies the design using basic logic gates.


module and_gate (input A, input B, output Y);
assign Y = A & B; // Logical AND operation
endmodule

Switch-level: Represents the circuit using transistors, offering the lowest level of
abstraction.
module and_gate_switchlevel (
input A,
input B,
output Y
);
wire nA, nB, nY;

// Using NMOS and PMOS to implement AND logic


nmos (nY, 0, A); // NMOS conducting when A=1
nmos (Y, nY, B); // NMOS conducting when B=1
pmos (Y, 1, A); // PMOS conducting when A=0
pmos (Y, 1, B); // PMOS conducting when B=0
endmodule
Verilog Modules
Modules
●​ The basic building block of Verilog.
●​ Defines the structure and behavior of a design.

module and_gate (input A, input B, output Y);


assign Y = A & B; // Logical AND operation
endmodule

Data Types
●​ wire: Represents a connection between hardware elements.
●​ reg: Stores data (used in procedural blocks).
●​ integer: For calculations in testbenches.

wire myWire;
reg myReg;
integer myInt;

Operators
●​ Arithmetic: +, -, *, /
●​ Logical: &&, ||, !
●​ Bitwise: &, |, ^, ~
●​ Relational: ==, !=, >, <

Procedural Blocks
●​ always: Executes statements whenever a specified event occurs.
●​ initial: Executes statements once at the beginning of the simulation.

always @(posedge clk) begin


q <= d; // Non-blocking assignment
end

Control Structures
●​ if / else: Conditional execution.
●​ case: Multi-way branching.

always @(posedge clk) begin


q <= d; // Non-blocking assignment
end

always @(a or b) begin


if (a > b)
max = a;
else
max = b;
end

Tasks and Functions


●​ Task: Used for operations that require multiple lines of code.
●​ Function: Returns a value and is used for combinational logic.

task displayValues;
input a, b;
begin
$display("A: %d, B: %d", a, b);
end
endtask

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