196 IEEE TRANSACTIONS ON EDUCATION, VOL. 47, NO.

2, MAY 2004

Interactive Teaching of Elementary Digital Logic

Design With WinLogiLab
Charles Hacker and Renate Sitte, Member, IEEE

Abstract—This paper presents an interactive computerized In introductory undergraduate electrical engineering courses,
teaching suite developed for the design of combinatorial and students are required to understand digital logic design con-
sequential logic circuits. This suite fills a perceived gap in the cepts. Students acquire the knowledge of how to design initially
currently available computer-based teaching software, with the
purpose of providing alternative-mode subject delivery. The a digital logic circuit, allowing them to solve, for example, the
authors were, therefore, prompted to develop a Microsoft-Win- following semi-real-life problem:
dows tutorial suite, WinLogiLab, comprising a set of interactive “An alarm is required to activate if an intruder is de-
tutorials that show the link between Boolean algebra and dig- tected from a window breaking, a pressure pad signaling, or
ital combinatorial and sequential circuits. The combinatorial
tutorials follow the initial design steps: from Boolean algebra, a movement detector signal. However, the alarm must not
to truth tables, to minimization techniques, to production of the activate if the person comes in the door, which is detected
combinatorial circuit in a seamless way. Similarly, the sequential by the movement detector and pressure pad signaling to-
tutorials can design simple finite-state counters and can model gether.”
more complex finite-state automata. Students are requested to develop a combinatorial digital
Index Terms—Boolean algebra, computer-aided logic design, logic circuit that will perform this task. In this process, the truth
educational technology, Karnaugh map, logic gates, minimization tables must be derived and then solved into the most efficient
software, online-interactive learning, Quine–McCluskey.
Boolean algebra expression by applying the Karnaugh map, the
Quine–McCluskey, or other algorithms. This expression results
I. INTRODUCTION in the final digital circuit diagram, which contains the logic
gates and connections obtained by the minimization process.
T EACHING elementary circuit design can be a challenge
because electrical engineering students often do not see
the immediate relationship between cause and effect, which can
Many useful computer programs are available that achieve
various aspects of digital logic design. They range from simple
simulators, to specific teaching tools, to advanced and special-
be seen, for example, in mechanical engineering experiments.
ized software. The authors tested several of these packages for
Traditionally, circuit-design teaching follows a three-stage se-
the purpose of introductory circuit design teaching. These pack-
quence from introductory logic to combinatorial circuits, and,
ages often perform the functions traditionally required in under-
several lectures later, to sequential circuits. While a number of
graduate courses, for example, Karnaugh maps and Quine–Mc-
packages dealing with circuit-related issues are available, they
Cluskey and Espresso minimizations. What makes WinLogiLab
are not specifically designed for a seamless interactive-learning
distinct is that it integrates all necessary functions into one tu-
environment that demonstrates the progression from Boolean
torial suite.
algebra through optimization, to the finally designed circuit in
Several programs can perform the simulation of a digital cir-
a modern Windows environment. To fill this gap, the authors
cuit, e.g., Logic Works [1], PSpice Mixed Mode Simulator [2],
have designed and implemented WinLogiLab. WinLogiLab is
and Micro-Cap V [3]. Other programs can emulate the func-
an interactive Microsoft (MS)-Windows-compatible computer-
tions performed in a digital electronic laboratory, e.g., Win-
ized teaching suite to aid in the teaching of combinatorial and
Breadboard [4] and Electronics Workbench [5]. The authors
sequential logic design. This software is applicable to introduc-
also looked at programs written to provide the teaching of dig-
tory digital design courses in Electrical Engineering, Computer
ital logic circuits in the style of an electronic book, e.g., Digital
Science, and Computer Engineering curricula. It serves both as
Technology Learning Package [6] and Digital Logic Tutor I [7].
student-centered self-paced learning and as a teaching demon-
There are others that electronically design certain segments of
stration tool. The main contribution of this work is to provide a
digital logic, such as the Espresso Logic Minimizer [8]. A range
set of interactive teaching aids to approach the basics of com-
of specialized designed software is available, which is devel-
binatorial and sequential digital circuit design. Its strength lies
oped for proprietary equipment, such as Programmable Logic
in its pedagogic value by showing to novices the link between
Devices (PLD) and Field Programmable Gate Arrays (FPGA).
Boolean algebra and the finally designed digital logic circuits,
They cover various aspects of digital logic design and simu-
in a fully integrated environment, and the convenience of being
lation, e.g., Hardware Description Language (HDL) programs,
MS-Windows compatible.
such as Mentor Graphics [9] and Cadence [10], as well as soft-
Manuscript received November 7, 2001; revised January 23, 2003. ware designed for ASIC/FPGA hardware, such as Xilinx [11]
The authors are with the Faculty of Engineering and Information Technology, and Actel [12]. These programs are very efficient at designing
Griffith University, Gold Coast Campus, Queensland 9726, Australia (e-mail:
[email protected]). very complex digital systems, but they are mainly for PLD and
Digital Object Identifier 10.1109/TE.2004.824843 FPGA design.
0018-9359/04$20.00 © 2004 IEEE
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
HACKER AND SITTE: INTERACTIVE TEACHING OF ELEMENTARY DIGITAL LOGIC DESIGN 197

Fig. 1. Structure of WinLogiLab interactive computerized teaching suite.

Undoubtedly, these programs can be used in teaching at dif- defined principles and offers greater commercial opportunity.
ferent levels, and some are perhaps better suited for specific The absence of software to perform digital logic design could,
purposes than others. For example, the HDL programs (such most likely, be attributed to the highly theoretical nature of the
as Mentor Graphics, Cadence, Xilinx, and Actel) are very ad- design, commonly resulting in very subjective designs. The pro-
vanced design and simulation tools and are, indeed, success- gramming of such subjective tasks is complex and must be ele-
fully being used in teaching in more advanced courses; however, mentary enough to enable automation.
they are beyond the purpose of an introductory course because
their complexity would detract the pupils’ focus and attention.
The size and complexity of these programs usually require spe- II. THE WINLOGILAB INTERACTIVE TUTORIAL SUITE
cific training to learn a program’s operation. Professional com-
puter-aided design (CAD) tools can and have been successfully To address the distinct absence in software for the teaching
applied in undergraduate learning in specifically integrated cur- of introductory digital logic design, the authors have developed
ricula [13] and conventional courses. However, with student edi- WinLogiLab. WinLogiLab is an interactive MS-Windows-com-
tions’ availability either limited or unavailable altogether, the patible computerized teaching suite to aid in the teaching of
price and licensing requirements of such programs can be justi- combinatorial and sequential logic design. Its emphasis lays in
fied only for more advanced courses. For introductory courses demonstrating to novice students the steps of elementary circuit
that typically are attended by a high number of students, the design in a seamless transition sequence and in an interactive
high cost may not be cost-effective or within reach, in particular, visual way.
when the purpose is to gain fundamental process understanding. The structure of WinLogiLab, including its major modules, is
From search and experience, the authors found that MS-Win- depicted in Fig. 1. Its major clusters are the combinatorial logic
dows-compatible teaching software was desirable. It would and the sequential logic modules. There is also a small cluster
cover the complete introductory digital logic design process in for introduction to Numerical Theory.
an interactive way. The software was required to demonstrate The modules in the combinatorial logic are WinBoolean,
the link between Boolean algebra, truth tables, logic circuits, BoolTut, and WinEspresso. These modules cover logic gates,
and minimization techniques of combinatorial logic to junior Boolean algebra, truth tables, and logic minimization tech-
students. In addition, the software was required to extend niques with Karnaugh maps and the Quine–McCluskey and
these fundamentals into sequential circuits to design flip-flop Espresso algorithms. The sequential modules are WinCounter
counters and finite-state machines (FSMs). The software also and WinState, which cover state counter design and the design
needed to be user friendly, and thus very intuitive to use, while of general-purpose FSMs.
producing formal presentations and realistic design outputs. Special attention was paid to implement WinLogiLab in a
Most currently available digital logic software focuses on user-friendly environment. A tutorial with short pop-up instruc-
simulation rather than design because simulation is based on tions provides additional guidance to new students.
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
198 IEEE TRANSACTIONS ON EDUCATION, VOL. 47, NO. 2, MAY 2004

The components of the WinLogiLab tutorial suite can be used

in two modes. One mode is a step-by-step, self-paced, set tuto-
rial that guides the student through any of its tasks and serves
as an introduction because it provides specific explanatory in-
formation. Alternatively, students can experiment by designing
their own circuits as independent self-paced exercises in which
students use their own input. Both modes offer ample help and
feedback to the student in a self-paced learning mode, in partic-
ular, because the students can see an immediate relationship in
cause and effect by what happens on the screen and, in addition,
from pop-up feedback comments. This level of understanding
would be difficult in conventional Boolean algebra teaching.
Students do not need to go through all steps until the final cir-
cuit is designed. Input can occur at several points throughout the
circuit design sequence, by either a manual input or a file saved
from an earlier session.
In addition, a self-test is available to the student. In this test, Fig. 2. Example of input as circuit diagram.
a student is requested to answer a number of computer-gener-
ated multiple-choice or short-answer questions on digital logic.
For example, the student can be requested to enter the Boolean
equation for a given randomly generated circuit diagram. Sim-
ilarly, other randomly generated questions on circuits, equa-
tions, truth tables, or minimization techniques are possible. A
true/false feedback is given immediately after each answered
test question, and a total score of the number of questions that
were correctly answered is given at the end. WinLogiLab has
also proven to be a useful lecturing aid when projected on a
large screen.
The current state of development of the WinLogiLab tutorial
suite can be obtained on CD from the authors or downloaded
from the Griffith University School of Engineering web page at Fig. 3. Example input as Boolean equation.
http://www.gu.edu.au/school/eng/mmt/MMTdownlds.html
In the following sections, the authors will briefly explain the
features of each of the modules.

A. WinBoolean
WinBoolean is designed to show the link between the equiva-
lent digital logic forms of logic gates, Boolean algebra, and truth
tables. All three techniques can be used interchangeably; thus,
a student in Digital Logic is required to be familiar with con-
verting from one to any other of these three equivalent forms.
Therefore, WinBoolean allows input in any of the three logic
forms and automatically converts it to any of the other equiva-
lent forms. Figs. 2 and 3 show sample screen images for input by
circuit diagram and equation, respectively. The entered user data
can then be simplified by a Karnaugh map or the Quine–Mc-
Cluskey algorithm [14]. Fig. 4 shows an example of Quine–Mc- Fig. 4. Example of a final Quine–McCluskey output.
Cluskey output of WinBoolean. The entered user data can then
be simplified by a Karnaugh map, a Quine–McCluskey algo-
stage of the minimization process [15]. It allows the user to
rithm, or Espresso algorithm to produce a minimized logic dia-
enter a truth table via the keyboard or mouse clicks, or alter-
gram.
natively, the program can randomly generate a truth table. The
user then selects the minimization process to be demonstrated
B. BoolTut by either the Karnaugh map, the Quine–McCluskey algorithm,
BoolTut is designed to provide an interactive tutorial on the or Espresso. The Karnaugh map process is valid for up to four
Karnaugh map or the Quine–McCluskey minimization process. inputs, while the Quine–McCluskey process will allow up to 12
The program operates with a user-supplied truth table and dis- input variables. Although it is clear that a Karnaugh map can be
plays an animated step-by-step presentation on each individual used for more than four variables, a higher number of variables
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
HACKER AND SITTE: INTERACTIVE TEACHING OF ELEMENTARY DIGITAL LOGIC DESIGN 199

Fig. 5. Sample interactive Karnaugh map generation.

Fig. 7. Example of interactive minimization of the Quine–McCluskey Prime
List.

algorithms are implemented in the WinBoolean and BoolTut

modules. These exact minimization techniques, in particular the
Quine–McCluskey algorithm, require the generation of all pos-
sible solutions (known as primes) and then the finding of the best
solution by a minimum cover procedure. In exact minimization
techniques, when the number of inputs to the function becomes
large, the computing process required increases exponentially.
This process is very inefficient because of the extreme number
of iterations that are required to generate all the possible solu-
tions. For this reason, the process becomes impractical or im-
possible to implement [16].
In contrast, truth table minimization techniques have con-
Fig. 6. Sample interactive Karnaugh map minimization. centrated on heuristic solving methods, which avoid computing
all possible results (the primes) [16], [18]. Instead they succes-
noticeably slows the process down. There is a tradeoff with how sively modify a given result until a suitable stopping criterion is
much can be put on a computer screen without the need for con- met, as depicted in Fig. 8.
stantly scrolling up and down to see one single diagram. For the The minimization is thus accomplished more efficiently and
purpose of understanding the process of deriving a Karnaugh rapidly. One should note that for inputs up to seven variables,
map, the authors considered it more important to show the two Espresso always finds the absolute optimal solution, but for
modes, the truth table, and the Karnaugh map together on the higher numbers of variables, it will find a near-optimal solution,
screen to visualize interactions, rather than a high number of not necessarily the absolute optimal solution.
variables. For more complex minimizations with multiple out- As a component in WinLogiLab, this method provides prac-
puts, the students would be using the Espresso algorithm. This ticing fast simplification of truth tables with up to 12 input and
technique is explained in the next section. eight output variables simultaneously [19]. It allows for the vi-
Figs. 5–7 show selected examples of different stages of the sual circuit schematic output as well as the associated Boolean
screen animations as they appear in the interactive tutorials. function.

C. WinEspresso D. DigiTrace
WinEspresso provides an alternative method for simplifying The DigiTrace module provides the final testing of a designed
Boolean truth tables, using a more efficient approach. The ra- logic circuit by partially simulating the operation of the circuit.
tionale is that there are two main fields in Boolean truth table The simulation is performed by displaying the trace of the dig-
minimization: the exact and the heuristic techniques. The exact ital logic signals throughout the circuit, which provides suffi-
techniques use thorough Boolean algebra operations resulting cient visual indication of the circuit’s function [20].
in an optimal minimized solution. The heuristic techniques use DigiTrace allows the user input of a digital circuit or the
rule-based approximations, which result in near-optimal min- loading of a circuit developed by any of the other combinatorial
imized solutions. Brayton et al. discuss different logic-mini- WinLogiLab modules. The DigiTrace module then displays the
mizing techniques and introduce or expand the heuristic tech- visual trace of the logic levels through each component of the
niques [16], [17]. circuit. Simulated light-emitting diode (LED) lights indicate the
The two exact techniques for truth table minimization are logic levels. A red light represents a logic low (0), and a green
the Karnaugh map and the Quine–McCluskey algorithm. Both light represents a logic high (1). The simulated circuit can have
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
200 IEEE TRANSACTIONS ON EDUCATION, VOL. 47, NO. 2, MAY 2004

Fig. 9. Sample result of the designed circuit to implement the counter.

applications, where transitions are frequent, such as continuous

changing counts. The data mode is more commonly used in data
storage applications, such as random access memory (RAM)
circuits.
The WinCounter program aids circuit analysis and design of
sequential state machine counters. State machine counters form
Fig. 8. Example of an Espresso heuristic procedure.
the fundamental process of most logic control applications, in-
cluding electronic timers, electronic clocks, remote controls,
one to four inputs, and these inputs can all have varying logic and industrial process controllers. WinCounter enables the cir-
levels. Thus, the logic levels throughout the circuit can be traced cuit design, or circuit analysis, of sequential state machine coun-
through for all possible combinations of the input logic levels. ters. The counters are implemented with data- or toggle-mode
The tracing can be done in one of the three following modes: flip-flop components and associated combinatorial logic gates
1) setting manually the values of the inputs in a circuit di- [21].
agram (via mouse clicks) on a logic-level input control The WinCounter software provides an interactive tutorial to
and observing the result of a simulated LED light at the exercise and understand flip-flop counter circuits. Its input can
output; be either as an input counter sequence or as a circuit. Its output
2) tracing all logic inputs where the result appears as an array produces a state diagram. A counter circuit is designed from a
of simulated LED lights; desired count sequence that is entered by the user. This count
3) tracing all waves displays a timing window showing mul- sequence is input into a state transition table; the table is then
tiple square-wave pulse output, similar to the outputs ob- minimized by the Karnaugh map process, resulting in the final
tained from many commercial and shareware logic simu- logic circuit that will perform the required count sequence. An
lation packages. example of the screen images of this process is shown in Fig. 9.
An existing counter circuit can also be analyzed by the pro-
gram. In this case, the user is required to input the known counter
E. Sequential Logic and WinCounter schematic. The program will then determine and display the
Following the natural progress of lectures on introductory Boolean functions to each of the flip-flop components and de-
logic and combinatory circuit stages, sequential circuits are also rive the state transition table of the circuit. Finally, a state transi-
included in the WinLogiLab. tion table then models the final count sequence of the analyzed
Sequential circuits have a primitive internal memory, assem- counter example.
bled with combinatorial logic to form a counter circuit. The
counter circuits form a branch of FSM. In WinLogiLab, the se- F. WinState
quential logic offers the state counter design with flip-flop com- The WinState tutorial software assists undergraduate students
ponents and the design of general-purpose FSM. in understanding the function of general-purpose FSMs, in par-
One might argue that flip-flops are not used much nowadays; ticular, the Mealy and Moore machines. The animated computer
however, they do have a pedagogical benefit. This benefit comes screen is ideal for conveying the required design and analysis
because flip-flop memory circuits can be wired in a number of procedures, while enabling students to better visualize the func-
modes. These modes are the data mode and toggle mode. A tioning of the FSM. In general, the purpose of FSMs as a mod-
sequential logic circuit can utilize a flip-flop that is wired in any eling tool goes beyond the machines that are used in digital
of these modes. The toggle mode is commonly used in counter control logic systems. For example, FSMs can be used for lan-
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
HACKER AND SITTE: INTERACTIVE TEACHING OF ELEMENTARY DIGITAL LOGIC DESIGN 201

affected node and arc. This highlighting occurs while the pro-
gram parses and executes the current input string and produces
the output string.

III. BENEFITS OF WINLOGILAB AND DISCUSSION

There are a number of issues that the authors have specifi-
cally addressed. The most important aim was to demonstrate to
the students the full transition from the numbering systems to
the testing of the simulated circuit by tracing its functioning,
where the student can learn by participating. The contents of
topics offered in WinLogiLab map to what would be a typical
undergraduate course.

Fig. 10. Example of WinState input by constructing the FSM as a graph, and
its automatically updated state transition table.
A. Self-Study and Alternative-Mode Learning
Students are able to learn at their own pace, “discovering”
principles while they experiment. Alternatively, they can step
guage parsing, mathematical processing, communication net-
through a set tutorial until they feel confident to use their own
work analysis, data encryption, and decryption [22].
input. Pop-up prompts provide guidance and feedback, and
FSMs operate on a recognizable (or legal) input string of “undo” buttons allow for quick amendments.
symbols (not necessarily binary), which continuously modifies BoolTut is different from the digital logic tutorial packages
its internal state and produces a corresponding output symbol tested, as initially explained. The program has improved capa-
string. FSMs can be either Moore or Mealy types. In a Moore bilities in letting the students enter their own initial data. This
machine, the derived outputs depend solely on the present in- procedure is in contrast to other tested packages that are cur-
ternal state of the FSM. In a Mealy machine, the derived outputs rently available that only present one “sample” input, going
depend on the present state and the applied inputs [23]. WinState through the same steps and the same solving process each time
allows both the design and the analysis of Mealy or Moore gen- the program is run. Other packages could not handle a large
eral-purpose FSM, operating with user-provided input data [24]. number of inputs by using an algorithm such as the Quine–Mc-
FSMs can be represented in two modes: in a state transition Cluskey process. Again these issues were specifically addressed
table, which lists tables of present state, inputs, next state, and and resolved in BoolTut, in flexible data input, and demon-
outputs, and in a directed graph, the state transition diagram. strated with step-by-step animations of both the Karnaugh map
This diagram consists of nodes (circles), representing the states, and the Quine–McCluskey minimization process.
and linking arcs, representing the transitions or next-state func- The Espresso algorithm is a heuristic technique for Boolean
tions. Input symbols are placed above the arcs, while output minimization, which has become a widely adopted and exten-
states are placed either next to the node (for a Moore machine) or sively discussed procedure that has been incorporated into the
underneath the input symbol (for a Mealy machine). A linking teaching curriculum of many university digital logic courses
arc is drawn for each possible input symbol, linking one node [18]. The Espresso algorithm was developed at the University
with another. of California-Berkeley, with its authorship being attributed to
WinState allows users to enter their own FSM design. States Rudell [8], [17]. The UNIX C compiler code for the Espresso
and arcs can be picked from the menu and placed. By clicking algorithm is freely available for downloading from the Design
on the arrow, one sees a pop-up box that prompts for input or Technology Warehouse, University of California-Berkeley [8].
output. Fig. 10 shows an example of a user input by constructing The UNIX C Espresso compiler code [8] is readily adaptable
the FSM as a graph, and its equivalent state transition table is for compiling to an MS-DOS (text base) executable program. A
automatically updated while the graph is being drawn. number of authors have generated MS-DOS executables from
WinState allows a range of recognizable (legal) input sym- this Espresso code, including Espresso.exe by Changwook [25].
bols, not just 0/1. This range purposely extends its use beyond The original Espresso code takes as input a text-based
digital circuit design. A typical FSM learning example is the Boolean truth table and generates a text-based minimized truth
parsing of an input string (not necessarily binary), with a null table output. The input truth table is provided from a text file,
character to mark the end of a string. Once the FSM has or as text data from the keyboard, while the minimized output
been implemented, a user-defined input symbol string, in binary is written to the computer’s display.
or in an other alphabet, can then be entered for execution. This A student’s initial understanding in digital logic design is that
procedure is equivalent to entering an instruction set or a rudi- a tabulated Boolean truth table is minimized to a logic circuit
mentary program. The string to be executed is input or edited schematic or Boolean function. The “Berkeley standard PLA”
by the user in the string dialogue window. text format of the original Espresso C code is adequate for rep-
This input string is then “executed” on the FSM. To aid the resenting a text-based input truth table and the corresponding
user in visualizing the execution, the current-state and link con- text-based minimized output. However, its cryptic text-based
ditions are highlighted on the FSM with thicker lines for the format does not match the standard Boolean truth table input,
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
202 IEEE TRANSACTIONS ON EDUCATION, VOL. 47, NO. 2, MAY 2004

nor does it correspond to the logic circuit or Boolean function with different minimization techniques. These minimizations
output. can be performed by exact methods, using Karnaugh maps and
These deficiencies were overcome by reimplementing the Quine–McCluskey algorithm, or by a computation-efficient
algorithm as Microsoft-Windows TM-compatible software, heuristic approximation, using the WinEspresso algorithm. The
called WinEspresso. This new graphical user interface allows paper also explains the implementation of a computer-based
for student input of a standard visual tabulated Boolean truth tutorial for designing and simulating counters and general-pur-
table and, after minimization by the Espresso algorithm, allows pose FSMs. WinLogiLab covers a range of topics typically
for the visual circuit schematic output and the associated taught in an introductory digital logic course, i.e., combi-
Boolean function. national and sequential circuits. It employs a graphical user
Implementing the WinLogiLab in the MS-Windows environ- interface in an MS-Windows environment, which provides
ment gives further benefits. First, it modernizes the code for the students with interactive, visual, and user-friendly software.
now standard MS-Windows 95, 98, and NT computer teaching Both the user friendliness and ease of use helps students to
laboratories. The implemented WinEspresso code can currently understand better the subject material. A student evaluation
operate on all MS-Windows platforms, from Windows 95 on- survey produced favorable responses. The survey also provided
wards. In addition, the windows graphical user interface en- valuable suggestions for further improvements in this digital
ables the displaying and printing of all forms of truth table in- logic design teaching and learning aid.
puts and circuit schematic outputs. In addition, the program is
fully mouse-click driven and includes helpful menu commands
REFERENCES
and toolbar buttons, with quick user-friendly operations, such
as open, save, print, and copy. Furthermore, the software en- [1] Capilano Computing Systems, Logic Works Version 3.0, Benjamin
Cummings, Redwood City, CA, 1995.
ables the user to use the menu items, or header toolbar buttons, [2] Orcad/MicroSim Corporation. (2002, Oct) WinPSpice Mixed
to continuously switch between the input Boolean truth table Mode Simulator—Version 9 (Student Version). [Online] Available:
and multiple output circuit displays. Finally, full copying and http://www.orcad.com
[3] A. Thompson, T. O’Brien, and B. Steele. (2002, Oct.). Micro-Cap V
pasting capabilities, with the MS-Windows clipboard, enables (Version 1.3), Spectrum Software. [Online] Available: http://www.spec-
the transfer of truth tables, circuit schematics, and Boolean func- trum-soft.com
tions to other applications, such as word processors. This latter [4] Yoeric Software. (2002, Oct) WinBreadboard Version 1.1 (Demo Ver-
sion). [Online] Available: http://www.yoeric.com/
capability was either not possible or very difficult to achieve [5] Interactive Image Technologies. (2002, Oct) Electronics Workbench
with DOS text-based code. 3.0E. Distributed by Applied Electro Systems, Australia. [Online]
To assess the usefulness of the tutorial suite, the author/lec- Available: http://www.interactiv.com
[6] R. J. Delahoy, Digital Technology Learning Package. North Dande-
turer administered a survey to the students of the introductory nong, Australia: R. J. Delahoy, 1995.
digital logic subject. The survey was repeated for two consecu- [7] G. N. Foster, Digital Logic Tutor I. New York: MacMillan, 1994.
tive years. Overall results revealed that the majority of students [8] UCB Design Technology Warehouse. (2002, Oct.) Espresso:
Logic Minimization Algorithms. UNIX compiler code, EECS
found the tutorial suite useful and user friendly, with an overall Dept., University of California-Berkeley. [Online] Available:
rating of 4.35 out of 5. http://www.cad.eecs.berkeley.edu/Software/software.html
The questionnaire also posed three open-ended questions: 1) [9] Mentor Graphics. (2002, Oct.) QuickSim & ModelSim HDL Simulator,
Wilsonville, OR. [Online] Available: http://www.mentor.com
what were the best features of the software; 2) what were the [10] Cadence Design Systems. (2002, Oct.) Ambit BuildGates, Irvine, CA.
worst features; and 3) what improvements would the students [Online] Available: http://www.cadence.com
suggest. The students’ statements about the best features in- [11] Xilinx, Inc.. (2002, Oct.), San Jose, CA. [Online] Available:
http://www.xilinx.com
cluded that it was a good study aid and that the tutorials made [12] Actel Corp.. (2002, Oct.), Sunnyvale, CA. [Online] Available:
it easy to design circuits, to solve Boolean equations, and to un- http://www.actel.com
derstand Karnaugh maps. Students also appreciated that results [13] N. L. V. Calazans and F. G. Moraes, “Integrating the teaching of com-
puter organization and architecture with digital hardware design early in
or outputs could be easily copied and pasted into other applica- undergraduate courses,” IEEE Trans. Educ., vol. 44, pp. 109–119, May
tions, such as reports for their assignment or tutorials. 2001.
Student statements on the worst features and suggested im- [14] C. Hacker and R. Sitte, “Development of a computer program, to elec-
tronically design digital logic circuits using Boolean algebra,” in Proc.
provements were similar. Suggestions included adding an op- 9th Annu. Australasian Association Engineering Education (AaeE97),
tion for ANSI/IEEE standard logic circuit symbols, adding an Dec. 1997, pp. 353–357.
option for the circuits to snap to a grid, allowing for higher num- [15] , “A computer based tutorial, for demonstrating the solving of dig-
ital logics circuits,” in Proc. 10th Annu. Australasian Association Engi-
bers of input variables, and making improvements in the style neering Education (AaeE98), Sept. 1998, pp. 509–519.
and wording on various tutorials. [16] R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli,
Logic Minimization Algorithms for VLSI Synthesis. Boston, MA:
Kluwer, 1984.
IV. CONCLUSION [17] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, “A
multi-level logic optimization system,” IEEE Trans. Computer-Aided
This paper outlines the characteristics and implementation of Design, vol. C-6, pp. 1062–1081, Nov. 1987.
[18] M. Theobald and S. M. Nowick, “Fast heuristic and exact algorithms
WinLogiLab, a computer-based tutorial suite to aid in teaching for two-level hazard-free logic minimization,” IEEE Trans. Computer-
the introductory design of digital logic circuits. WinLogiLab Aided Design, pp. 1130–1147, Nov. 1998.
fills a perceived gap in computer-aided teaching by providing [19] C. Hacker and R. Sitte, “Implementing the “Espresso—Two level logic
minimizer” algorithm in the MS-Windows environment,” in Proc. 2nd
tutorials that link Boolean algebra and digital logic circuits. Asia-Pacific Forum Engineering Technology Education, UNESCO Int.
The tutorials help students in digital logic design to experiment Conf. Engineering Education (UICEE99), July 1999, pp. 124–127.
Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.
HACKER AND SITTE: INTERACTIVE TEACHING OF ELEMENTARY DIGITAL LOGIC DESIGN 203

[20] , “A computer based teaching program for the tracing of logic levels Renate Sitte (S’90–M’95) received the Systems Engineering degree (Ingeniero
in a digital circuit,” in Proc. 4th Annu. UNESCO Int. Conf. Engineering de Sistemas) from the Universidad de Los Andes, Los Andes, Venezuela, in
Education (UICEE2001), Bangkok, Thailand, Feb. 2001, pp. 509–519. 1985 and the M.Phil. and Ph.D. degrees from Griffith University, Queensland,
[21] , “A computer based teaching program for the design and analysis Australia.
of digital counter circuits,” in Proc. 3rd Annu. UNESCO Int. Conf. En- She is a Faculty Staff Member in engineering and information technology,
gineering Education (UICEE2000), Feb. 2000, pp. 225–228. Griffith University, where she has been teaching computing, software engi-
[22] J. L. Gersting, Mathematical Structures for Computer Science. New neering, and discrete mathematics since 1986. Her research is in modeling and
York: Freeman, 1987. simulation, and she has one major ongoing project in virtual-reality prototyping
[23] A. M. Tenenbaum and M. J. Augenstein, Data Structures Using microelectromechanical systems (MEMS).
Pascal. Englewood Cliffs, NJ: Prentice-Hall, 1981. Dr. Sitte is currently Vice-Chair of the IEEE Queensland Section and Chair of
[24] C. Hacker and R. Sitte, “Implementing finite state machines in a com- the IEEE Computer Chapter. She is also a Member of the Institute of Engineers
puter based teaching system,” in Proc. SPIE Int. Symp. Microelectronics Australia, contributing to the development of the ISO standards for software
Micro Electro Mechanical Systems (MICRO/MEMS), Gold Coast, Aus- engineering.
tralia, Oct. 28–29, 1999, pp. 100–117.
[25] P. Changwook. (1998) Espresso.exe. Shareware, Seodu Logic-Elec-
tronic Technology Institute. [Online] Available: http://eda.seodu.co.kr/
~chang/download/espresso

Charles Hacker received the Dip.Eng. degree and the B.App.Sc. degree in
physics from the University of Central Queensland (UCQ), Queensland, Aus-
tralia, in 1987 and 1990, respectively, the Grad. Dip. Sc. degree in medical
physics from the Queensland University of Technology (QUT), Queensland,
Australia, in 1995, and the M.Phil. degree in electrical engineering from Grif-
fith University, Queensland, Australia, in 2003.
He started working as a Demonstrator, Tutor, and Sessional Lecturer at
the Physics Department, UCQ, in 1989. In 1991, he became a Lecturer in
Electronic Engineering with the School of Engineering, Griffith University.
His teaching areas include electronics, microprocessors, physics, and computer
programming.

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DE PELOTAS. Downloaded on March 23,2025 at 06:08:04 UTC from IEEE Xplore. Restrictions apply.