MANUAL

PROJECT REPORT

submitted by

VAES Branch

to

the APJ Abdul Kalam Technological University

in partial fulfillment of the requirements for the award of the Degree
of

Master of Technology
In
VLSI and Embedded Systems

Department of Electronics and Communication Engineering

Rajagiri School of Engineering and Technology (Autonomous)
Rajagiri Valley, Kakkanad, Kochi - 682039

OCTOBER 2022
Contents

LIST OF FIGURES

LIST OF ABBREVIATIONS

1 LITERATURE SURVEY 2
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 ZedBoard Kit contents: . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 ZedBoard Key Features . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 ZedBoard Basic Setup and Operation . . . . . . . . . . . . 6
1.4.1 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.2 ZedBoard System Block Diagram . . . . . . . . . . . . . . . . . . 12

2 IMPLEMENT A 4-BIT RIPPLE CARRY ADDER DESIGNED

ON Zed BOARD 14
2.1 AIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 THEORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 a) Ripple carry adder . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 b) Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . 14
2.2.3 c) Zed Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 SOURCE CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.1 a) Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.2 b) Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.3 c) Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 TEST BENCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1 Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6 SIMUATION RESULT . . . . . . . . . . . . . . . . . . . . . . . 22
2.7 RTL SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.8 RTL SCHEMATIC AFTER SYNTHESIS . . . . . . . . . 24
2.9 CONSTRAINT FILE FOR FPGA IMPLEMENTA-
TION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.10 FPGA IMPLEMENTATION . . . . . . . . . . . . . . . . . . . 25
2.10.1 a) Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11 RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 DESIGN AND IMPLEMENT A CUSTOM ALU ON Zed
BOARD USING VERILOG HDL. 27
3.1 AIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 THEORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 Arithmetic and Logic Unit . . . . . . . . . . . . . . . . . . . . . 28
3.3 PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 SOURCE CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 TEST BENCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.1 * ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6 SIMUATION RESULT . . . . . . . . . . . . . . . . . . . . . . . 33
3.7 RTL SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.8 RTL SCHEMATIC AFTER SYNTHESIS . . . . . . . . . 35
3.9 CONSTRAINT FILE FOR FPGA IMPLEMENTA-
TION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10 FPGA IMPLEMENTATION . . . . . . . . . . . . . . . . . . . 36
3.10.1 a) Addition . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10.2 b) Subtraction . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10.3 c) Subtraction . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.10.4 d) Multiplication .
. . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10.5 .
e) AND Operation . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10.6 f ) OR Operation . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10.7 .
g) XOR Operation . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.10.8 h) Division . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.11 RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 4 BIT BINARY SYNCHRONOUS UP DOWN COUNTER. 44

4.1 AIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 THEORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 SOURCE CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.1 a) COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.2 b) CLOCK DIVIDER CIRCUIT . . . . . . . . . . . . . . . . . . 47
4.5 TEST BENCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5.1 a) COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5.2 b) CLOCK DIVIDER CIRCUIT . . . . . . . . . . . . . . . . . . 50
4.6 SIMULATION RESULT . . . . . . . . . . . . . . . . . . . . . . 51
4.7 RTL SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.8 RTL SCHEMATIC AFTER SYNTHESIS . . . . . . . . . 53
4.9 CONSTRAINT FILE FOR FPGA IMPLEMENTA-
TION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.10 FPGA IMPLEMENTATION . . . . . . . . . . . . . . . . . . . 55
4.10.1 a) UPCOUNTING(0000 ,0001,. . . 1111) : . . . . . . . . . . . . . 55
4.10.2 b) DOWNCOUNTING(1111,1110,..0000) : . . . . . . . . . . . . 56
4.11 RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 CONCLUSIONS 58
REFERENCES 59
List of Figures

1.1 ZedBoard Hardware Block Diagram . . . . . . . . . . . . . . . . . . . . . . 5

1.2 ZedBoard SC Card Boot Mode Jumper Setting . . . . . . . . . . . . . . . 7
1.3 Device Manager Showing Enumerated USB-UART as COM13 . . . . . . . 8
1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 USB Serial Port Advanced Settings Dialog Box . . . . . . . . . . . . . . . 10
1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8 ZedBoard Example Design Block Diagram . . . . . . . . . . . . . . . . . . 12
1.9 ZedBoard Example LED Output . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2 RTL Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 RTL Schematic after Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Constraint file for FPGA Implementation . . . . . . . . . . . . . . . . . . . 25
2.5 Adder 3+2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 ALU-Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 ALU-RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3 ALU-RTL Schematic after Synthesis . . . . . . . . . . . . . . . . . . . . . 35
3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Addition 3+3 =6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6 Subtraction 11-2 = 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7 Subtraction 2-11 =-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8 Multiplication 3*2 =6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 AND 3*2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10 OR 3/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 XOR 3 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.12 Division 9/3 = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.1 Counter-Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Counter-RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 Counter-RTL after Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4 Counter-Constraint file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5 Upcounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6 Downcounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
List of Abbreviations
1. UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver-Transmitter

2. FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Array

3. ARM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced RISC Machine

4. USB Serial Bus

 The Report is organized into four chapters.Literature Review is presented in chapter
1. In chapter 2 Implementation of 4-bit Ripple Carry Adder is explained and in chapter
3 Implementation of a Custom ALU is explained.Finally, Chapter 4 includes Implemen-
tation of 4-bit binary Synchronous Up Down Counter.

1
Chapter 1
LITERATURE SURVEY

1.1 Introduction

ZedBoard™ is a complete development kit for designers interested in exploring designs

using the AMD Xilinx Zynq®-7000 All Programmable SoC. The board contains all the
necessary interfaces and supporting functions to enable a wide range of applications.

ZedBoard™ is a low-cost development board for the Xilinx Zynq®-7000 All Pro-
grammable SoC. This board contains everything necessary to create a Linux, Android,
Windows® or other OS/RTOS-based design. Additionally, several expansion connectors
expose the processing system and programmable logic I/Os for easy user access. Take
advantage of the Zynq-7000 AP SoC’s tightly coupled ARM® processing system and 7
series programmable logic to create unique and powerful designs with ZedBoard. Zed-
Board is supported by the zedboard.org community website where users can collaborate
with other engineers also working on Zynq designs.

The ZedBoard enables hardware and software developers to create or evaluate Zynq™-
7000 All Programmable SoC designs. The expandability features of this evaluation and
development platform make it ideal for rapid prototyping and proof-of-concept devel-
opment. The ZedBoard includes Xilinx XADC, FMC (FPGA Mezzanine Card), and
Digilent Pmod™ compatible expansion headers as well as many common features used in
system design. ZedBoard enables embedded computing capability by using DDR3 mem-
ory, Flash memory, gigabit Ethernet, general purpose I/O, and UART technologies. This
Getting Started Guide will outline the steps to setup the ZedBoard hardware. It docu-
ments the procedure to run a simple Linux design to show a Linux application running

2
on the ARM® dual-core Cortex™- A9 MPCore™ Processing System (PS) and interacting
with the tightly coupled 7 series 85K Programmable Logic (PL) cells. Xilinx Embedded
Development tools are also introduced where the design can be built from scratch and
customization options can be discovered. If Xilinx ISE WebPACK or Design Suite soft-
ware is not already installed, further resources to install the software, get updated and
generate a license

1.2 ZedBoard Kit contents:

*ZedBoard

*12 volt / 5 ampere power supply with US, European AC adapter

*USB-A to Micro-USB-B cable

*Micro-USB-B to Type A Female adapter cable

*4GB SD car

*Software : Xilinx Vivado DVD, Xilinx License Voucher for Vivado Design Edition
tools for ZedBoard designs

3
1.3 ZedBoard Key Features

* Memory : 512 MB DDR3 , 256 Mb Quad-SPI Flash, 4 GB SD card

* Communication : Onboard USB-JTAG Programming, o 10/100/1000 Ethernet,

USB OTG 2.0 and USB-UART

* Expansion connectors : FMC-LPC connector (68 single-ended or 34 differential

I/Os),5 Pmod™ compatible headers (2x6), Agile Mixed Signaling (AMS) header

* Clocking : 33.33333 MHz clock source for PS, 100 MHz oscillator for PL

* Display : HDMI output supporting 1080p60 with 16-bit, YCbCr, 4:2:2 mode color,
VGA output (12-bit resolution color), 128x32 OLED display

* Configuration and Debug : Onboard USB-JTAG interface, Xilinx Platform Cable

JTAG connector

* General Purpose I/O : 8 user LEDs, 7 push buttons, 8 DIP switches

4
Figure 1.1: ZedBoard Hardware Block Diagram

5
1.4 ZedBoard Basic Setup and Operation

The ZedBoard SD card is preloaded with an example open source Linux build with
a RAMdisk file system. This document was created using a host PC running Windows
7 and the instructions contained would apply directly to a Windows 7 host PC. See
Appendix III for an example of how to connect a Linux host PC to ZedBoard. It is also
recommended that the host PC also have a wired (RJ-45 connector) Network Interface
Card (NIC) that can operate at 100 Mbps or 1000 Mbps.

1.4.1 Hardware Setup

1.Connect 12 V power supply to barrel jack (J20).

2. Connect the USB-UART port of ZedBoard (J14) which is labeled UART to a PC

using the MicroUSB cable.

3. Insert the 4GB SD card included with ZedBoard into the SD card slot (J12) located
on the underside of ZedBoard PCB. This SD card comes preloaded with demo software
and contains a basic Linux configuration used to implement the demos listed in the later
sections.

4. Verify the ZedBoard boot (JP7-JP11) and MIO0 (JP6) jumpers are set to SD card
mode as described in the Hardware Users Guide. www.zedboard.org/documentation/1521

6
 Figure 1.2: ZedBoard SC Card Boot Mode Jumper Setting

5. Turn power switch (SW8) to the ON position. ZedBoard will power on and the
Green Power Good LED (LD13) should illuminate.

6. The PC may pop-up a dialog box asking for driver installation. ZedBoard has a
USB-UART bridge based on the Cypress CY7C64225 chipset. Use of this feature requires
that a USB driver be installed on your Host PC. If Windows recognizes the USB-UART
and loads the software driver, then amber LED D6 will light. Please skip ahead to the
next section. However, if the host PC does not recognize the USB-UART and enumerate
it as a COM port device. When driver installation is complete, continue to the next step.

7. www.zedboard.org/documentation/1521

8. Wait approximately 15 seconds. The blue Done LED (LD12) should illuminate,
and a default image will be displayed on the OLED (DISP1).

9. Use Device Manager to determine the COM Port.

7
 Figure 1.3: Device Manager Showing Enumerated USB-UART as COM13

10. To enable ‘Port Persist’ mode double click on the “USB Serial Port (COMx)” or
“Cypress Serial (COMx)” port under “Ports (COM LPT)”. Select the “Port Setting”
tab. Click the “Advanced” button.

8
 Figure 1.4:

11. Check the “Enable Port Persist” check box in the Advanced Settings dialog box.
Click OK to close the Advanced Settings dialog box and again to close the Serial Port
Properties box. The Port Persist property should be enabled the next time the serial port
is opened.

9
 Figure 1.5: USB Serial Port Advanced Settings Dialog Box

12. On your PC, open a serial terminal program. For this demo, Windows 7 was
used which does not come with a built in terminal application. Tera Term was used in
this example which can be downloaded from the Tera Term project on the SourceForge
Japan page: ttssh2.sourceforge.jp

13. Once Tera Term is installed, Tera Term can be accessed from the desktop or start
menu shortcuts.

Figure 1.6:

10
 14. To configure baud rate settings, open the Serial Port Setup window from the
SetupSerial port menu selection. Select the USB-UART COM port enumeration that
matches the listing found in Device Manager. Also set the Baud rate option to 115200,
the Data width option to 8-bit, the Parity option to none, the Stop bit option to 1 bit, and
the flow control to none. Finally, assign the transmit delay parameters to 10 msec/char
and 100 msec/line, and then click OK.

Figure 1.7:

15. Optionally, at this point, the terminal settings can be saved for later use. To
do this, use the Setup - Save setup menu selection and overwrite the existing TER-
ATERM.INI file.

16. If the amber USB-Link Status (LD11) does not flicker to indicate activity, check
the driver installation to determine if the device driver is recognized and enumerated
successfully and that there are no errors reported by Windows.

11
1.4.2 ZedBoard System Block Diagram

Figure 1.8: ZedBoard Example Design Block Diagram

A script for changing the state of the LEDs is also included. To set the state of the user
LEDs (LD0-LD7), use the script writel edandspecif ythebytevaluetobewrittentotheLEDs.F orexample, r
LD7illuminatingasseenin

12
Figure 1.9: ZedBoard Example LED Output

13
Chapter 2
IMPLEMENT A 4-BIT RIPPLE CARRY ADDER DESIGNED
ON Zed BOARD

2.1 AIM

To design and implement Ripple carry adder on Zed Board.

2.2 THEORY

2.2.1 a) Ripple carry adder

Ripple Carry Adder is a combinational logic circuit. It is used for the purpose of
adding two n- bit binary numbers. It requires n full adders in its circuit for adding two
n-bit binary numbers.
It is also known as n-bit parallel adder. Multiple full adder circuits can be cascaded in
parallel to add an N-bit number. For an N- bit parallel adder, there must be N number
of full adder circuits. A ripple carry adder is a logic circuit in which the carry-out of each
full adder is the carry in of the succeeding next most significant full adder. It is called
a ripple carry adder because each carry bit gets rippled into the next stage. In a ripple
carry adder, the sum and carry out bits of any half adder stage is not valid until the carry
in of that stage occurs.

2.2.2 b) Field Programmable Gate Arrays (FPGAs)

FPGAs are semiconductor devices that are based around a matrix of configurable logic
blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed

14
to desired application or functionality requirements after manufacturing. This feature
distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are
custom manufactured for specific design tasks. Although one-time programmable (OTP)
FPGAs are available, the dominant types are SRAM based which can be reprogrammed as
the design evolves. ASIC and FPGAs have different value propositions, and they must be
carefully evaluated before choosing any one over the other. Information abounds that com-
pares the two technologies. While FPGAs used to be selected for lower speed/complexity/volume
designs in the past, today’s FPGAs easily push the 500 MHz performance barrier. With
unprecedented logic density increases and a host of other features, such as embedded
processors, DSP blocks, clocking, and high-speed serial at ever lower price points, FPGAs
are a compelling proposition for almost any type of design. Due to their programmable
nature, FPGAs are an ideal fit for many different markets. As the industry leader, Xilinx
provides comprehensive solutions consisting of FPGA devices, advanced software, and
configurable, ready-to-use IP cores for markets.

2.2.3 c) Zed Board

ZedBoard™ is a low-cost development board for the Xilinx Zynq®-7000 All Pro- grammable
SoC. This board contains everything necessary to create a Linux, Android, Windows®
or other OS/RTOS-based design. Additionally, several expansion connectors expose the
processing system and programmable logic I/Os for easy user access. Take advantage
of the Zynq-7000 AP SoC’s tightly coupled ARM® processing system and 7 series pro-
grammable logic to create unique and powerful designs with ZedBoard. Zed- Board is
supported by the zedboard.org community website where users can collaborate with other
engineers also working on Zynq designs. The ZedBoard enables hardware and software
developers to create or evaluate Zynq™- 7000 All Programmable SoC designs. The ex-
pandability features of this evaluation and development platform make it ideal for rapid
prototyping and proof-of-concept devel- opment. The ZedBoard includes Xilinx XADC,
FMC (FPGA Mezzanine Card), and Digilent Pmod™ compatible expansion headers as well
as many common features used in system design. ZedBoard enables embedded computing
capability by using DDR3 mem- ory, Flash memory, gigabit Ethernet, general purpose
I/O, and UART technologies. This Getting Started Guide will outline the steps to setup
the ZedBoard hardware. It docu- ments the procedure to run a simple Linux design to
show a Linux application running on the ARM® dual-core Cortex™- A9 MPCore™ Pro-
cessing System (PS) and interacting with the tightly coupled 7 series 85K Programmable

15
Logic (PL) cells. Xilinx Embedded Development tools are also introduced where the de-
sign can be built from scratch and customization options can be discovered. If Xilinx ISE
WebPACK or Design Suite soft- ware is not already installed, further resources to install
the software, get updated and generate a license

2.3 PROCEDURE

1) Open Vivado design suite.

2) Create a new project.

3) Choose the Zed board on which the adder design is to be implemented.

4) Add the source code and test bench for 4 bit ripple carry adder.

5) Set the test bench of counter as top module

6) Run simulation and obtain the simulation results for ripple carry adder

7) Perform RTL analysis and obtain the elaborated design.

8) Now set the source

9) Perform RTL analysis once again and open elaborated design.

10) Go to the layout in top right corner and choose I/O planning and the design to
be implemented will be obtained.

11) Assign the ports by choosing I/O ports. Assign slide switch for input a and input
b and LED is assigned for the sum of adder.

12) Set VCCO as tvcmos33 and save. The constraint file(.xdc) will be created.

16
 13) Now run synthesis and the synthesised design will be opened.

14) Next run implementation and generate Bit stream.

15) Connect the Zed board by connecting the USB port of board to the pc and also
plug in the power cable to the board.

16) Click Open hardware manager and then on open target →Autoconnect →Program
device.

17) Now the board will be programmed for the counter design and is ready to imple-
ment the logic.

2.4 SOURCE CODE

2.4.1 a) Half Adder

‘timescale 1ns / 1ps

module half-add(a, b, sum, carry);

input a;
input b;
output sum;
output carry;

assign sum = a or b; // bitwise xor

assign carry = a and b; // bitwise and

endmodule

17
2.4.2 b) Full Adder

‘timescale 1ns / 1ps

module Full-add(A, B, Cin, Sum, Cout);

input A;
input B;
input Cin;
output Sum;
output Cout;

wire ha1-sum;
wire ha2-sum;
wire ha1-carry;
wire ha2-carry;
wire Sum;
wire Cout;

//Instantiate the half adder 1

half-add ha1(
.a(A),
.b(B),
.sum(ha1-sum),
.carry(ha1-carry)
);

//Instantiate the half adder 2

half-add ha2(
.a(Cin),
.b(ha1-sum),
.sum(ha2-sum),

18
 .carry(ha2-carry)
);

//sum output from 2nd half adder is connected to full adder output

assign Sum = ha2-sum;

//The carry’s from both the half adders are OR’ed to get the final carry./

assign Cout = ha1-carry or ha2-carry;

endmodule

2.4.3 c) Ripple Carry Adder

‘timescale 1ns / 1ps

module rc-add-4bit(A, B, Cin, Cout, Sum);

input[3:0] A,B;
input Cin;
output[3:0] Sum;
output Cout;
wire[2:0] cp;

/Instantiate the Full Adder 1(FA1)

Full-add FA1(
.A(A[0]),
.B(B[0]),
.Cin(Cin),
.Sum(Sum[0]),
.Cout(cp[0])

19
);

Full-add FA2(

.A(A[1]),
.B(B[1]),
.Cin(cp[0]),
.Sum(Sum[1]),
.Cout(cp[1])
);

Full-add FA3(

.A(A[2]),
.B(B[2]),
.Cin(cp[1]),
.Sum(Sum[2]),
.Cout(cp[2])
);

Full-add FA4(

.A(A[3]),
.B(B[3]),
.Cin(cp[2]),
.Sum(Sum[3]),
.Cout(Cout)
);

endmodule

20
2.5 TEST BENCH

2.5.1 Ripple Carry Adder

t̀imescale 1ns / 1ps

module rc-add-4bit-tb;

/inputs

reg [3:0] A;
reg [3:0] B;
reg Cin;

/ Outputs

wire [3:0] Sum;

wire Cout;

/ Instantiate the Unit Under Test (UUT)

rc-add-4bit uut(
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.Sum(Sum)
);

initial begin

21
 A = 4’b0010; B = 4’b0110; Cin=0; 20;
A = 4’b0110; B = 4’b0011; Cin=0; 20;
A = 4’b0100; B = 4’b0111; Cin=0; 20;
A = 4’b0010; B = 4’b0001; Cin=0; 20;

f inish;

end

endmodule

2.6 SIMUATION RESULT

Figure 2.1: Simulation Result

22
2.7 RTL SCHEMATIC

Figure 2.2: RTL Schematic

23
2.8 RTL SCHEMATIC AFTER SYNTHESIS

Figure 2.3: RTL Schematic after Synthesis

2.9 CONSTRAINT FILE FOR FPGA IMPLEMENTATION

24
 Figure 2.4: Constraint file for FPGA Implementation

2.10 FPGA IMPLEMENTATION

2.10.1 a) Adder

25
 Figure 2.5: Adder 3+2

2.11 RESULT

Performed the RTL design, simulation and implementation of Ripple Carry Adder on
FPGA using Xilinx Vivado

26
Chapter 3
DESIGN AND IMPLEMENT A CUSTOM ALU ON Zed
BOARD USING VERILOG HDL.

3.1 AIM

To design and implement a 4-bit custom ALU on Zed board using Verilog HDL.

ALU should perform:

000 = Addition

001 = Subtraction

010 = Multiplication

011 = Division

100 = Logical AND

101 = Logical OR

110 = Logical XOR

111 = Check whether both are equal

27
3.2 THEORY

3.2.1 Arithmetic and Logic Unit

An arithmetic logic unit (ALU) is a combinational digital circuit that performs arith-
metic and bitwise operations on integer binary numbers. This is in contrast to a floating-
point unit (FPU), which operates on floating point numbers. It is a fundamental building
block of many types of computing circuits, including the central processing unit (CPU)
of computers, FPUs, and graphics processing units (GPUs). The inputs to an ALU are
the data to be operated on, called operands, and a code indicating the operation to be
performed; the ALU’s output is the result of the performed operation. In many designs,
the ALU also has status inputs or outputs, or both, which convey information about a
previous operation or the current operation, respectively, between the ALU and external
status registers.

3.3 PROCEDURE

1) Open Vivado design suite.

2) Create a new project.

3) Choose the Zed board on which the ALU design is to be implemented.

4) Add the source code and test bench for ALU.

5) Set the test bench of counter as top module

6) Run simulation and obtain the simulation results for custom ALU

7) Perform RTL analysis and obtain the elaborated design.

8) Now set the code of ALU as top module

28
 9) Perform RTL analysis once again and open elaborated design.

10) Go to the layout in top right corner and choose I/O planning and the design to
be implemented will be obtained.

11) Assign the ports by choosing I/O ports. Assign slide switch for inputs and push
buttons as mode and LED is assigned for the output.

12) Set VCCO as tvcmos33 and save. The constraint file(.xdc) will be created.

13) Now run synthesis and the synthesised design will be opened.

14) Next run implementation and generate Bit stream.

15) Connect the Zed board by connecting the USB port of board to the pc and also
plug in the power cable to the board.

16) Click Open hardware manager and then on open target →Autoconnect →Program
device.

17) Now the board will be programmed for the counter design and is ready to imple-
ment the logic.

3.4 SOURCE CODE

module custom-alu(

input [3:0] A,B, // ALU 4-bit Inputs

input [2:0] ALU-Sel,// ALU Selection

output [3:0] ALU-Out // ALU 4-bit Output

//not considering cout here

29
);

reg [3:0] ALU-Result;

assign ALU-Out = ALU-Result;

always @(*)

begin

case(ALU-Sel)
3’b000: // Addition

-Result = A + B ;

3’b001: // Subtraction

ALU-Result = A

-B;

3’b010: // Multiplication

ALU-Result = A * B;

3’b011: // Division

ALU-Result = A/B;

3’b100: //

ALU-Result = A B ;

3’b101: // Subtraction

30
 ALU-Result = A — B ;

3’b110:

ALU-Result = A B ;

3’b111:

ALU-Result = (A==B)?4’d1:4’d0 ;

default: ALU-Result = A + B ;

endcase

end

endmodule

3.5 TEST BENCH

3.5.1 * ALU

‘timescale 1ns / 1ps

module alu-tb;

reg [3:0] A, B;
reg [2:0] mode;
wire [3:0] alu-out;

integer i;

31
alu-4bit uut(
.a(A),
.b(B),
.m(mode),
.alu-out(alu-out)
);

initial
begin

A = 4’h3;
B = 4’h2;
mode = 3’h0;

for (i=0;i¡=7;i=i+1)

begin
10;
mode = mode + 3’h1;
end;

10 f inish;

end

endmodule

32
3.6 SIMUATION RESULT

Figure 3.1: ALU-Schematic

33
3.7 RTL SCHEMATIC

Figure 3.2: ALU-RTL

34
3.8 RTL SCHEMATIC AFTER SYNTHESIS

Figure 3.3: ALU-RTL Schematic after Synthesis

3.9 CONSTRAINT FILE FOR FPGA IMPLEMENTATION

35
 Figure 3.4:

3.10 FPGA IMPLEMENTATION

3.10.1 a) Addition

Figure 3.5: Addition 3+3 =6

36
3.10.2 b) Subtraction

Figure 3.6: Subtraction 11-2 = 9

37
3.10.3 c) Subtraction

38
 Figure 3.7: Subtraction 2-11 =-9

3.10.4 d) Multiplication

Figure 3.8: Multiplication 3*2 =6

39
3.10.5 e) AND Operation

Figure 3.9: AND 3*2

3.10.6 f ) OR Operation

Figure 3.10: OR 3/2

40
41
3.10.7 g) XOR Operation

42
 Figure 3.11: XOR 3 2

3.10.8 h) Division

Figure 3.12: Division 9/3 = 3

3.11 RESULT

Performed the RTL design, simulation and implementation of 4-bit custom ALU on
FPGA using Xilinx Vivado

43
Chapter 4
4 BIT BINARY SYNCHRONOUS UP DOWN COUNTER.

4.1 AIM

To perform the RTL design, simulation and implementation of 4 bit binary counter
on FPGA using Xilinx Vivado.

4.2 THEORY

Counters are used in many different applications. Some count up from zero and provide
a change in state of output upon reaching a predetermined value; others count down from
a preset value to zero to provide an output state change.However, some counters can
operate in both up and down count mode, depending on the state of an up/down count
mode input pin.
Synchronous Counters are so called because the clock input of all the individual flip-
flops within the counter are all clocked together at the same time by the same clock signal.
Unlike asynchronous counters whose output of one stage is connected directly to the clock
input of the next counter stage in the chain. The synchronous counter has its stages all
clocked together at the same time.
This 4-bit synchronous counter counts sequentially on every clock pulse the resulting
outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ) when the mode bit is high and
counts down when the mode bit is counts downwards from 1111 to 0000.
A clock divider is a circuit that takes an input signal of a frequency fin and generates
an output signal of a frequency fout, where fout = fin / n and ”n” is an integer. In
zedboard ,the oscillator frequency is 100Mhz. Thus when implementing counter on to the
board the output will not be visible. So a clock divider circuit is used to scale down the

44
frequency to 1Hz. And thus the counter can be effectively implemented on to the board.

4.3 PROCEDURE

1) Open Vivado design suite.

2) Create a new project.

3) Choose the Zed board on which the counter design is to be implemented.

4) Add the source code and test bench for 4 bit synchronous counter.

5) Since the board operates at 100 MHz frequency to observe the output on the board
a clock divider circuit is added with the source code.

6)Set the test bench as top module

7) Run simulation and obtain the simulation results for upcounter and down counter.

8) Perform RTL analysis and obtain the elaborated design.

9) Now set the source

10) Perform RTL analysis once again and open elaborated design.

11) Go to the layout in top right corner and choose I/O planning and the design to
be implemented will be obtained.

12) Assign the ports by choosing I/O ports. Assign slide switch for mod and reset
pin of counter and LED for displaying the up counting and down counting

45
 13) Since the board operates at 100 MHz frequency the clock must be assigned to pin
Y9 (clock capable pin).

14) Set VCCO as tvcmos33 and save. The constraint file(.xdc) will be created.

15) Now run synthesis and the synthesised design will be opened.

16) Next run implementation and generate Bit stream.

17) Connect the Zed board by connecting the USB port of board to the pc and also
plug in the power cable to the board.

18) Click Open hardware manager and then on open target →Autoconnect →Program
device.

19) Now the board will be programmed for the counter design and is ready to imple-
ment the logic.

20) Now keeping the reset ’high’ and mod as ’1’ will perform upcounting and mod ’0’
performs downcounting. When reset is set to ’low’ the board resets.

4.4 SOURCE CODE

4.4.1 a) COUNTER

‘timescale 1ns / 1ps

module syncounter-4bit(clk, rst, out, m);

input clk, rst, m; //inputs

output [3:0] out; //outputs

46
 wire clk-out;
reg [3:0] out;

Clock-divider uut(
.clock-in(clk),
.clock-out(clk-out)
);

always @(posedge(clk-out) or posedge (rst)

begin
if(rst == 0)
out ¡= 0;
else if ( m == 1) // up counting
if (out == 15)
out ¡= 0;
else
out ¡= out + 1;
else //down counting
if (out == 0)
out ¡= 15;
else
out ¡= out - 1;

end

endmodule

4.4.2 b) CLOCK DIVIDER CIRCUIT

t̀imescale 1ns / 1ps

47
 module Clock-divider(clock-in,clock-out);

input clock-in; // input clock on FPGA

output reg clock-out; // output clock after dividing the input clock by divisor

reg[27:0] counter=28’d0;

parameter DIVISOR = 28’d100000000;

// The frequency of the output clk-out

// = The frequency of the input clk-in divided by DIVISOR

always @(posedge clock-in)

begin
counter ¡= counter + 28’d1;
if(counter¿=(DIVISOR-1))
counter ¡= 28’d0;

clock-out ¡= (counter¡DIVISOR/2)?1’b1:1’b0;

end

endmodule

4.5 TEST BENCH

4.5.1 a) COUNTER

‘timescale 1ns / 1ps

48
module tb-syncounter;

//inputs
reg clk, rst, m;

//outputs
wire [3:0] out;

syncounter-4bit uut (
.clk(clk),
ṙst(rst),
.m(m),
.out(out)
);

initial clk = 0;

always 5 clk = clk;

initial begin

rst = 0;
m = 0;
100;
rst = 1;
m = 0; //down counting
155;
rst = 1;
m = 1; // up counting
200;
rst = 0;
100;

49
 end

endmodule

4.5.2 b) CLOCK DIVIDER CIRCUIT

‘timescale 1ns / 1ps

module Clock-divider(clock-in,clock-out);

input clock-in; // input clock on FPGA

output reg clock-out; // output clock after dividing the input clock by divisor

reg[27:0] counter=28’d0;

parameter DIVISOR = 28’d100000000;

// The frequency of the output clk-out
// = The frequency of the input clk-in divided by DIVISOR

always @(posedge clock-in)

begin
counter ¡= counter + 28’d1;
if(counter¿=(DIVISOR-1))
counter ¡= 28’d0;

clock-out ¡= (counter¡DIVISOR/2)?1’b1:1’b0;

end

endmodule

50
4.6 SIMULATION RESULT

Figure 4.1: Counter-Simulation

51
4.7 RTL SCHEMATIC

Figure 4.2: Counter-RTL

52
4.8 RTL SCHEMATIC AFTER SYNTHESIS

Figure 4.3: Counter-RTL after Synthesis

53
4.9 CONSTRAINT FILE FOR FPGA IMPLEMENTATION

Figure 4.4: Counter-Constraint file

54
4.10 FPGA IMPLEMENTATION

4.10.1 a) UPCOUNTING(0000 ,0001,. . . 1111) :

Figure 4.5: Upcounting

55
4.10.2 b) DOWNCOUNTING(1111,1110,..0000) :

Figure 4.6: Downcounting

56
4.11 RESULT

Performed the RTL design, simulation and implementation of 4 bit binary counter on
FPGA using Xilinx Vivado

57
Chapter 5
CONCLUSIONS

The Project proposes familiarization and Implementation of 4-Bit Ripple Carry Adder,
ALU, 4- Bit binary Counter on Zed Board. Tested using Xilinx Vivado and then performed
RTL, finally implemented on Zed Board.

58
Bibliography

[1] https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-
families/zedboard/
[2] https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html