BRANCH INSTRUCTIONS

A branch instructions is used to change the flow of execution or to call a routine or sub routine.

Branch instructions allows programs to have subroutine, if-then-else structures and loops.

The change of execution flow forces the program counter PC to point to a new address.
The ARMv5E instruction set includes four different branch instructions: B,BL,BX and BLX

Syntax: B{<cond>} label

◦ BL{<cond>} label

◦ BX{<cond>} Rm

◦ BLX{<cond>} Rm

◦ BLX label

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The Branch instruction, B label causes a branch to label
The BL label instruction copies the address of next instruction after BL (return address)
into lr (R14) and causes a branch to label.

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The address label is stored in the instruction as a signed pc-relative offset and must be
within approximately 32 MB of the branch instruction.
T refers to the Thumb bit in the cpsr.
If Rm is 0x01 then state of processor will be in Thumb state.
If Rm is 0x00 then state of processor will be in ARM state.
BX instruction causes a branch to the address held in Rm and changes instruction set to
Thumb if bit0 of Rm is set.
BX and BLX are the third type of Branch Instructions.
BX and BLX uses an absolute address stored in Register Rm.
These instructions are used to branch to and from Thumb State.

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The BLX instructions has two alternative forms;
◦ BLX label: An unconditional branch with link to label address. This instruction copies the
address of next instruction after BLX into lr and causes a branch to label. It also changes the
state to Thumb.

◦ BLX{<cond>} Rm: An unconditional branch with link to the address held in a register. This
instruction copies address of next instruction after BLX into lr and causes branch to the
address held in Rm. It also changes the state to thumb if bit0 of Rm is set.

◦ Note: BX and BLX causes a switch between ARM and Thumb state while branching to a
subroutine.

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Backward jumps and Forward jumps are possible using branch instructions;
◦ Backward jump, the label appears before branch instructions.

◦ Forward jump, the label appears after branch instructions.

◦ Example to compute sum of first n natural numbers

◦ MOV R0,#5

◦ MOV R1,#0

Loop ADD R1,R0

◦ SUBS R0,#1
If z=0
◦ BNE loop
Backward Jump

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Example to compute sum of first n natural numbers
◦ MOV R0,#5

◦ MOV R1,#0

Loop ADD R1,R0

◦ SUBS R0,#1

◦ BEQ STOP

◦ B Loop

◦ STOP B STOP

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Develop an ALP to compare two numbers held in R0 and R1. Design subroutine to compare
two numbers and store 10H in R2 if they are equal and store 20H if they are not equal.

◦ AREA EX1, CODE, READONLY

◦ ENTRY
◦ MOV R0,#5
◦ MOV R1,#10
◦ BL COMPARE
◦ STOP B STOP
COMPARE CMP R0,R1
MOVEQ R2,#0x10
MOVNE R2,#0x20

ARM INSTRUCTION SET 8

 LOAD-STORE INSTRUCTIONS

Load-Store instructions transfer data between memory and processor registers.

Load instruction transfers data held in memory to processor register.

Store instruction transfers data from processor register to memory.

There are three types of load-store instructions

◦ 1. Single-register transfer

◦ 2. Multiple register transfer

◦ 3. Swap

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 Si n g l e -reg iste r tran sfe r

These instructions are used for moving a single date item in and out of a register.

The datatypes supported are signed and unsigned words(32-bit), half words(16-bit) and
bytes(8 bit).
Syntax:
◦ <LDR|STR>{<cond>}{B} Rd, addressing

◦ LDR {<cond>}SB|H|SH Rd, addressing

◦ STR{<cond>} H Rd, addressing

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Below are the list of various load-store single-register transfer instructions.

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NOTE:
STRH stores both signed and unsigned half word.
STRB stores both signed and unsigned bytes.

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Example:

Load register R0 with the contents of the memory address pointed to by register R1.
◦ LDR R0, [R1] ; LDR R0,[R1,#0]

This instruction loads a word (32 bit) from the address stored in register R1 and places
it into register R0. Register R1 is called the base address register.

Store the contents of register R0 to the memory address pointed to by register R1.
◦ STR R0, [R1] ; STR R0,[R1,#0]

This instruction stores the contents of register R0 to the address contained in register
R1. The offset from register R1 is Zero. Register R1 is called the base address register.

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Single Register Load-Store Addressing Modes
The ARM instructions set provides different modes for addressing memory.

These modes incorporate one of the following indexing methods:

 Preindex with writeback

 Preindex

 Postindex
Table: Index Methods

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Preindex with writeback calculates an address from a base register plus offset and then
updates that address base register with the new address.

Preindex is same as the preindex with writeback but does not update the base register.

Postindex updates the base address register only after the address is used.

NOTE:

The Preindex mode is useful for accessing an element in a data structure.

The Postindex and Preindex with writeback modes are useful for traversing an array.

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PRE
◦ R0 = 0x00000000
◦ R1 = 0x00009000
◦ Mem32[0x00009000] = 0x01010101
◦ Mem32[0x00009004] = 0x02020202
◦ LDR R0,[R1,#4]! ;Preindex with writeback
POST
◦ R0 = 0x02020202
◦ R1 = 0x00009004
◦ LDR R0,[R1,#4] ;Preindex
POST
◦ R0 = 0x02020202
◦ R1 = 0x00009000
◦ LDR R0,[R1],#4 ;Postindex
POST
◦ R0 = 0x01010101
◦ R1 = 0x00009004
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Below table shows the addressing modes available for load and store of a 32 bit word or an
unsigned byte

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A signed offset or register is denoted by “+/-” identifying that it is either positive or negative
offset from the base address register Rn.

Immediate means the address is calculated using the base address register and 12-bit offset
encoded in the instruction.

Register means the address is calculated using the base address register and specific register
contents.

Scaled means the address is calculated using the base address register and a barrel shift
operation.

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Below table shows the examples of LDR instructions using different addressing
Modes.

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Below table shows the addressing modes available on load and store instructions
using 16 bit half word or signed byte data.

NOTE: These operations cannot use barrel shifter.

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Below table shows examples of STRH instruction.

STRH instruction can be used to store unsigned and signed 16 bit data.

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MULTIPLE REGISTER TRANSFER
Load-store multiple instructions can transfer multiple data items between memory and
the processor registers in a single instructions.

The Multiple register transfer occurs from the memory address held in base address
register Rn.

The Multiple register transfer instructions are more efficient from single register
transfers for
 Moving blocks of data around memory
 Saving and restoring context
 Stacks

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Syntax:

The addressing mode supported for load-store multiple instructions are IA,IB,DA,DB.

The Base Register Rn determines the source or destination address for a load-store
multiple instruction.

The Register Rn can be optionally updated after the transfer which occurs where Rn is
followed by the ! Character.

Any subset of the current bank of register can be transferred to memory or fetched
from memory.

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Below table shows different addressing modes for the load-store multiple instructions.

Here, N is the number of register in the list of register.

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 Example 1:
PRE
◦ Mem32[0x80018] = 0x00000003
◦ Mem32[0x80014] = 0x00000002
◦ Mem32[0x80010] = 0x00000001
◦ r0 = 0x00080010
◦ r1 = 0x00000000
◦ r2 = 0x00000000 Figure (a). Pre condition of LDMIA Instruction
◦ r3 = 0x00000000
◦ LDMIA r0!,{r1-r3}
POST
◦ r0 = 0x0008001C
◦ r1 = 0x00000001
◦ r2 = 0x00000002
◦ r3 = 0x00000003
Figure (b). Pre condition of LDMIA Instruction

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 Example 2:
PRE
◦ Mem32[0x80018] = 0x00000003
◦ Mem32[0x80014] = 0x00000002
◦ Mem32[0x80010] = 0x00000001
◦ r0 = 0x00080010
◦ r1 = 0x00000000
◦ r2 = 0x00000000 Figure (a). Pre condition of LDMIB Instruction
◦ r3 = 0x00000000
◦ LDMIB r0!,{r1-r3}
POST
◦ r0 = 0x0008001C
◦ r1 = 0x00000002
◦ r2 = 0x00000003
◦ r3 = 0x00000004
Figure (b). Post condition of LDMIB Instruction
After executing LDMIB,r0 points to the last loaded memory location. This is in contrast with LDMIA which points to next memory location
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PRE Example 3:
Mem32[0x80010] = 0x00000001
Mem32[0x8000C] = 0x0000000a
Mem32[0x80008] = 0x0000000b
Mem32[0x80004] = 0x0000000c
r0 = 0x00080010
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
LDMDA r0!,{r1-r3}
POST
r0 = 0x00080004
r1 = 0x0000000b
r2 = 0x0000000a
r3 = 0x00000001

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PRE Example 4:
Mem32[0x80010] = 0x00000001
Mem32[0x8000C] = 0x0000000a
Mem32[0x80008] = 0x0000000b
Mem32[0x80004] = 0x0000000c
r0 = 0x00080010
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
LDMDB r0!,{r1-r3}
POST
r0 = 0x00080004
r1 = 0x0000000c
r2 = 0x0000000b
r3 = 0x0000000a

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Application of Multiple Register Transfer

With the increment and decrement load multiples, we can access arrays in forward or
backward direction. They also allow for stack push or pull operation.

Below table shows a list of load-store multiple instruction pairs.

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PRE
r0 = 0x00009000
r1 = 0x00000009
r2 = 0x00000008
r3 = 0x00000007
STMIB r0!, {r1-r3}
MOV r1,#1
MOV r2,#2
MOV r3,#3
PRE(2)
r0 = 0x00009000
r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
LDMDA r0!, {r1-r3}
POST
r0 = 0x00009000
r1 = 0x00000009
r2 = 0x00000008
r3 = 0x00000007

ARM INSTRUCTION SET 30