MICROPROCESSOR

Lecturer: Sejal M Chopra

Min. Mode and Max. Mode of 8086

1. Comparison of min. mode/ max. mode configuration:

Sr.No. MINIMUM MODE MAXIMUM MODE

1. Pin no.33 is connected to +Vcc Pin no.33 is connected to GND
2. Control signals are generated by processor Control signals are generated by bus
controller
3. In this M/IO*,RD*,WR* decides the type of In this SO*,S1*,S2* decides the type
data transfer of data transfer
4. multiprogramming is not possible because no multiprogramming is possible
co-processor is used because co-processor is used
5. advanced I/O or memory write command is advanced I/O or memory write
not possible command is possible
6. Hardware requirement is less Hardware requirement is more
(8288, 8286)
7. Cheaper Costly
8. 8086 controls the operation of latches & Bus controller (8288) controls the
transceivers operation of latches & transceiver

2. 8086-Minimum mode configuration:

1. The system in minimum mode has the following chips: 8284, 8086, 74LS373/8282, 8286.
2. The signals AD0 – AD15, A16/S3- A19/S6, and BHE*/S7 are multiplexed. These signals are
demultiplexed by the external latches and the ALE signal.
3. If 16 bit address is used there are two latches and if 20 bit address then three latches are
required. These latches provide increased output drive capacity.
4. If the processor system has several devices interfaced to it then to increase the current
sourcing and sinking, it is essential to use transceivers for data bus, then they are
controlled by two signals DEN*,DT/R*. To service 16 bit data two transceivers IC’s are
required.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

DEN* DT/R* Operation

1 X Transreceiver is disabled
0 0 Receive data
0 1 Transmit data
5.8284 clock generator provides clock pulses at constant frequency.
6. The power on reset circuitry initializes the system with clock pulses.
7. The status on the lines M/IO*, RD* &WR* will decide the type of operation IOR, IOW,
MEMR, MEMW.
M/IO* RD* WR* Operation
1 0 1 Memory read
1 1 0 Memory write
0 0 1 I/O read
0 1 0 I/O write

8. The HOLD & HLDA signals are used to interface with other bus masters like DMA controller.
9. The INTR and INTA signals are used to increase the interrupt handling capacity of the
8086.
10. In minimum mode system of 8086, MN/MX is connected to Vcc.

3.8086-Maximum mode configuration:

1. In maximum mode system of 8086, MN/MX is connected to ground.

2. An additional circuitry is required to generate the control signals by converting the status
signals (S2-S0)* to I/O and memory transfer signals. The 8288 bus controller is used to
generate signals like MRDC*, MWTC*,AMWC*,AIOWC*,IORC*,IOWC*.
S2* S1* S0* Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port (IOR)
0 1 0 Write I/O port (IOW)
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory(MEMR)
1 1 0 Write memory(MEMW)
1 1 1 Passive
 MICROPROCESSOR
Lecturer: Sejal M Chopra

3. The bus controller is responsible for the working of two chips that is latches and
transceivers.
4. The ALE of bus controller is connected to STB of latch, while DEN is connected to OE* of
transceivers and DT/R* is connected to T of transceivers.
DEN DT/R* Operation
0 X Transreceiver is disabled
1 0 Receive data
1 1 Transmit data

5. The MRDC* and MWTC* instruct the memory to accept or send data on the data bus.
6. The IORC* AND IOWC* instruct the I/O device to read or write data to or from addressed port
on the data bus.
7. The AIOWC* and AMWTC* are advanced I/O and memory write commands which are similar
to IOWC and MWTC except that they are activated one clock signal before them.
8.8086 and 8288 are synchronized to the same clock frequency.
9. Bus request is done using RQ*/GT* lines interfaced with 8086.

4. Timing Diagrams:
It is the graphical representation of what actually happens inside the processor at different
instants of time.

Viva question: What is an instruction cycle?

It is the combination of fetching an opcode and executing an instruction.
INSTRUCTION CYCLE=FETCH CYCLE+EXECUTION CYCLE
Each instruction cycle has N no. of machine cycles which either fetches an opcode or may be
an I/O read or I/O write or memory read or memory write. Each machine cycle has N no. of
T- states where each T-state is 1 clock cycle.

Timing Status of Minimum-mode 8088 memory interface:

- Since a memory read or write should be complete within one bus-cycle (4-CLK pulses, T1 -
T4), related timing states as follows:
o T1 (or the 1st clock pulse)- starts the bus cycle. Actions include setting control signals to
give the required logic values for IO/M*, ALE, DT/R* and a valid address onto the address bus.
o T2 - the RD* or WR* control signals are issued, DEN* is asserted and in the case of a write,
data is put onto the data bus. The DEN* turns on the data bus buffers to connect the CPU to
the external data bus. The READY input to the CPU is sampled at the end of T2 and if READY is
low, wait state (TW) is inserted before T4 begins.
o T3 - this clock period is provided to allow memory to access the data. If the bus cycle is a
read cycle, the data bus is sampled at the end of T3 or the 3rd clock pulse of the bus-cycle.
o T4 - all bus signals are deactivated in preparation for the next clock cycle. The 8088 also
finishes sampling the data (in a read cycle) in this period. For the write cycle, the trailing
edge of the WR* signal transfers data to the memory.

a. Minimum Mode Memory Read Cycle (for 8088):

- To complete the minimum-mode memory-read bus-cycle, the required control signals with
appropriate active logic levels are :
o IO/M* = ‘logic 0’, to select memory interface
o MN/MX* = ‘logic 1’, to select minimum-mode of operation
o DT/R* = ‘logic 0’, to activate the data-receive mode of ‘Data-bus-buffer’
o Valid Physical-address of memory-location via address-bus (A19 to A0)
o ALE-pulse, to latch the valid Physical-address.
o RD* = ‘logic 0’, to initiate reading data into CPU. Note, WR = ’logic 1’
o DEN* = ‘0’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
o Reset RD*=DEN*=’logic1’, to END the read-bus-cycle.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

b. Minimum Mode Memory Write Cycle (for 8088):

To complete the minimum-mode memory-write bus-cycle, the required control signals with
appropriate active logic levels are :
o IO/M* = ‘logic 0’, to select memory interface
o MN/MX* = ‘logic 1’, to select minimum-mode of operation
o DT/R* = ‘logic 1’, to activate the data-transmit mode of ‘Data-bus-buffer’
o Valid Physical-address of memory-location via address-bus (A19 to A0)
o ALE-pulse, to latch the valid Physical-address.
o WR *= ‘logic 0’, to initiate memory data writing. Note, RD* = ’logic 1’
o DEN* = ‘0’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
o Reset WR*=DEN*=’logic1’, to END the write-bus-cycle.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

c. Maximum Mode Memory Read Cycle (for 8086):

To complete the minimum-mode memory-read bus-cycle, the required control signals with
appropriate active logic levels are:
o IO/M* = ‘logic 0’, to select memory interface
o MN/MX* = ‘logic 0’, to select maximum-mode of operation
o DT/R* = ‘logic 0’, to activate the data-receive mode of ‘Data-bus-buffer’
o Valid Physical-address (A0 to A19) and BHE* signal is generated by CPU
o ALE-pulse, to latch the valid Physical-address.
o Proper status code S0 to S2 is generated by CPU to initiate data reading (MRDC) from the
desired memory bank.
o DEN = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass.
o Reset MRDC and DEN signals to END the read-bus-cycle.

d. Maximum Mode Memory Write Cycle (for 8086):

To complete the maximum-mode memory-write bus-cycle, the required control signals
with appropriate active logic levels are:
o IO/M* = ‘logic 0’, to select memory interface
o MN/MX* = ‘logic 0’, to select maximum-mode of operation
o DT/R* = ‘logic 1’, to activate the data-transmit mode of ‘Data-bus-buffer’
o Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
o ALE-pulse, to latch the valid Physical-address.
o Proper status code S0 to S2 is generated by CPU to initiate data writing (MWTC) from the
desired memory bank

o DEN = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass

o Reset MWTC and DEN signals to END the read-bus-cycle.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

Viva Question: Why do the signals don’t start at the start of each T-state?
All digital circuits have some propagation delay time due to which the signals start little late.

Viva Question: Why during the read cycles the multiplexed address/data bus floats after the
address is given out?
During read operations transfer of data is from memory(slower device) to processor(faster
device),hence during read operation data is pushed on the data bus after sometime.

5. Exercise on modes of 8086/8088:

1. For the given timing diagram of a 8086 memory read bus-cycle, find the errors in the
diagram (T1 - T4 are clock pulses that constitute one bus-cycle)

2. For the given figure below, if 8088 is performing a minimum mode memory write bus cycle,
which logic levels must be applied to DEN*, DT/R* and RD* pins.
 MICROPROCESSOR
Lecturer: Sejal M Chopra

3. What is the duration of machine cycle in the 8086 based micro-computer if the clock is 8
MHz and the two wait states are inserted.

Answers to above questions:

1. Waveform M/IO* is correct. Waveform multiplexed address/status lines is correct.
Waveform AD0-AD7 is incorrect as it should have data in T3 state. There should be
multiplexed AD0-AD15 lines. Waveform ALE is incorrect as it should be active in T1 state.

2.DEN*=0
DT/R*=1
RD*=1

3. The duration of one T-state in one machine cycle is: 1/8 MHz=125 nsec.
Thus, duration of a machine cycle (having 4 T-states) with 2 wait states is:
(125nsec *4) + (125nsec*2)=750 nsec