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Lecture 32 - Array Logic and FPGA

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3 views

Lecture 32 - Array Logic and FPGA

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Akahay Verma
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE370A: DIGITAL ELECTRONICS

ARRAY LOGIC AND FPGA


Dr. Shubham Sahay,
Assistant Professor,
Department of Electrical Engineering,
IIT Kanpur
➢ The contents of the slides and videos are meant for the students registered for EE370A.
➢ Attempts have been made to acknowledge the source of any material used in these
lectures. The purpose of reproducing them is purely academic. No copyright violation is
intended. In case there is any inadvertent copyright violation, please bring it to the
notice of the instructor for rectification.
➢ These slides and video are not meant to be shared or posted in public spaces
including any web-site. The students having access to these slides/video lectures are
requested to ensure this.
WAYS OF IMPLEMENTING BOOLEAN LOGIC
➢ Logic Gates: the most popular method
➢ Alternate implementation of logic blocks:
➢ MUX
➢ Memory based look-up tables
➢ Can you think of any other way?
➢ Recently: in-memory logic implementation.
➢ In-memory: perform logic operations in memory itself.
➢ Logic computed where the data is stored.
➢ Reduces data transfer between memory and processing units: highly energy-efficient
➢ Array Logic
MEMORY BASED LOGIC IMPLEMENTATION
➢ Also called Look-up table (LUT) based approach.
➢ Memory acts like the dictionary.
➢ Control inputs enable addressing a particular memory location.
➢ Reading memory location gives the output.
➢ We may store different functions as different columns and then
select a particular column to implement a particular logic.
➢ Multiple multivariable functions may be realized easily
➢ Re-write memory content: different gates may be realized during
runtime.
➢ Same hardware: variety of logic: reconfigurable logic
➢ LUT + programmable interconnect forms the basis for FPGAs
ARRAY LOGIC IMPLEMENTATION

➢ Two level implementation of Boolean logic


➢ Any SOP Logic: AND plane followed by OR plane
➢ Total product terms are 2n
➢ Not all Minterms are included in any logic (if included output is 1)
➢ POS logic: OR plane followed by AND
➢ SOP can be transformed to NOR-NOR or NAND-NAND planes (CMOS implementation is easy)
➢ Single MOSFETs can’t pass perfect 1 or 0. Hence, CMOS is advantageous.
ARRAY-LEVEL PROGRAMMABLE LOGIC
FUSE-BASED PROGRAMMING
➢ Fuse connections: all connected initially, blow fuse to
disconnect
➢ Anti-fuse: all open initially, short fuse to connect lines.
➢ Current flows and blows fuse due to heating.
➢ Anti-fuse: E-field leads to dielectric breakdown and
connects.
➢ Intermetal dielectric breakdown
➢ Fuse: Al wire or other wire having less melting point and
heat them using laser or electrical pulse (joule heating)
ARRAY-BASED PROGRAMMABLE WIRING
➢ Similar to ROM: has a memory which dictates which WLs and BLs are connected.
➢ Forms integral part of FPGAs.
➢ Program memory to change the wiring of circuit
OTHER PROGRAMMABLE ARCHITECTURES
FIELD PROGRAMMABLE GATE ARRAY (FPGA)
➢ Capability to program in the field.
➢ LUTs and programmable interconnects are used.
➢ VHDL or Verilog code is synthesized to generate the gate level netlist.
➢ The FPGA algorithm generates a series of bitstream
➢ This bitstream is written into serial registers (memory) of FPGA.
➢ Helps to configure: connect and program LUTs to realize the required gate level schematic
on FPGA.
➢ For small circuits, we make generic blocks and instead of making dedicated hardware use
FPGA.
➢ Programmable logic block with programmable interconnect
➢ Consumes more power and area than ASICs: have to deal with more transistors.

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