Unit 6

Syllabus :

1. Study of MOSFETs:
a. Structure and Operation of n-channel enhancement MOSFET,
b. MOSFET Current-Voltage Characteristics,
2. CMOS Inverter-
a. DC Characteristics, Voltage Transfer Characteristics,
3. Noise Margin
4. Combinational MOS Logic Circuits:
a. Pass Transistors/Transmission Gates;
b. Designing with transmission gates.
5. MOS Layers Stick/Layout Diagrams:
a. Layout Design Rules,
b. Issues of Scaling,
c. Scaling factor for device parameters.

Questions :

1. Sketch the Voltage Transfer characteristics of CMOS inverter and explain in detail (include all the regions:
Region A, B, C, D, E).
2. Explain in detail with suitable diagram:
a. Dynamic Power dissipation
b. Noise Margin
c. Transmission Gate
3. Sketch the Schematic and Stick Diagram of the following circuits:
a. CMOS NOR Gate
b. CMOS OR Gate
c. CMOS EX-OR Gate
d. CMOS Inverter
e. Y = (A.B) + C
4. Explain the concept of constant-field scaling and constant voltage scaling in detail.
5. Describe the following:
a. Layout Design rule
b. Device Modelling
6. Explain the circuit extractors and hierarchical circuit extractors in detail.
7. Describe Lambda-based and Micron-based layout design rules in detail. Justify the answer with the example
of NMOS.
8. What is Scaling and Scaling Factor?
9. Draw Layout of CMOS inverter and mention at least 6 design rules.
10. With Diagram explain Modelling and extraction of circuit parameters from physical layout.

11. Explain Body effect and Channel length modulation in detail. [4]
12. Explain controllability measure with an example. [9]

CMOS Inverter- DC Characteristics, Voltage Transfer Characteristics

13. Explain CMOS inverter transfer characteristics in detail. What is Bn/Bp ratio? How to achieve this? [8]
14. Draw and Explain I-Ve characteristics of PMOS.[7]
15. Draw the CMOS digital design of the given equation. (A.B) + (C.D.E.) .[6]
16. Prove that to achieve completely symmetric input output characteristics for a CMOS inverter, the design
requires to have (W/L)P =2.5(W/L)N. Assume that the gate oxide thickness tox and hence the gate oxide
capacitance Cox, have the same value for both NMOS and PMOS transistors.[7]
17. What is DRC? Explain in detail design rules in CMOS VLSI DESIGN.[8]
18. Explain in detail static and dynamic power dissipation. what are the components which makes power
dissipation in CMOS circuit? [8]
19. Implement 4 : 1 multiplexer using [10] i) CMOS Logic ii) Pass Transistor logic
20. Explain different Power dissipation in CMOS circuit designs. [10]
21. Draw the CMOS digital design of nand gate. [6]
22. Draw and Explain Ids - Vds characteristics of NMOS. [5]
23. Draw CMOS inverter and explain voltage transfer curve ip detail. [6]
24. Derive the expression for voltage threshold (Vth) of CMOS. [6]

Noise Margin
25. Explain noise margin. Give it expressions. [4]
26. Describe Noise Margin, Power Delay Product, Energy dissipation, channel modulation. [8]

Combinational MOS Logic Circuits: Pass Transistors/Transmission Gates;

27. Describe Combinational MOS Logic Circuits : Pass Transistors/ Transmission Gates by using 2:1 MUX. [6]

Designing with transmission gates.

28. Write a short note on Transmission gates. [4]

MOS Layers Stick/Layout Diagrams: Layout Design Rules,

29. Draw stick diagram and layout of 2 input NAND gate. [8]
30. Draw Stick Diagram for a CMOS Inverter. List down different layout editors/tools available in VLSI Design. [9]
31. Describe design rules available in Layout Design. Explain design rules for NMOS. [9]
32. Draw Stick Rule Diagram for a CMOS Inverter.
33. What are the design rules available in Layout Design? Explain design rules for NMOS

Issues of Scaling, Scaling factor for device parameters.

34. What is Scaling? Explain the effect of any one type of scaling on various parameters like channel length,
width power dissipation, capacitances.[9]
35. Define scaling. Explain the scaling technique in detail. [9]
36. What is technology scaling? What are types. Explain each in detail.[10]
1. Study of MOSFET :
a. Fundamentals :
i. A Metal Oxide Semiconductor Field-effect Transistor (MOSFET) is a field-effect transistor (FET
with an insulated gate) where the voltage determines the conductivity of the device. It is
used for switching or amplifying signals. The ability to change conductivity with the amount
of applied voltage can be used for amplifying or switching electronic signals.
ii. It is a four-terminal device with Source (S), Drain (D), Gate (G), and body (B) terminals. The
body (B) is frequently connected to the source terminal, reducing the terminals to three. It
works by varying the width of a channel along which charge carriers flow (electrons or
holes).
iii. The charge carriers enter the channel at the source and exit via the drain. The width of the
channel is controlled by the voltage on an electrode called Gate which is located between
the source and the drain. It is insulated from the channel near an extremely thin layer of
metal oxide
iv. FOUR types of MOSFET :
1. N – Channel & P – Channel ( Based on Type of current carriers )
2. Enhancement Mode & Depletion Mode ( Based on type of working of depletion layer
)
v. PMOS :
1. The drain and source are heavily doped p+ region and the substrate is in n-type. The
current flows due to the flow of positively charged holes, and that’s why known as p-
channel MOSFET.
2. When we apply negative gate voltage, the electrons present beneath the oxide layer
experience repulsive force and are pushed downward into the substrate, the
depletion region is populated by the bound positive charges which are associated
with the donor atoms. The negative gate voltage also attracts holes from the P+
source and drain region into the channel region.
3.
vi. NMOS :
1. The drain and source are heavily doped N+ region and the substrate is p-type. The
current flows due to the flow of negatively charged electrons and that’s why known
as n-channel MOSFET.
2. When we apply the positive gate voltage, the holes present beneath the oxide layer
experience repulsive force, and the holes are pushed downwards into the bound
negative charges which are associated with the acceptor atoms. The positive gate
voltage also attracts electrons from the N+ source and drain region into the channel
thus an electron-rich channel is formed.
3.

vii. Working :
1. The working principle of a MOSFET depends upon the MOS capacitor. The
semiconductor surface at the below oxide layer is located between the source and
drain terminals. It can be inverted from p-type to n-type by applying positive or
negative gate voltages.
2. When we apply positive gate voltage, the holes present under the oxide layer
experience a repulsive force, and holes are pushed downward with the substrate.
The depletion region is populated by the bound negative charges that are associated
with the acceptor atoms. The electrons reach, and the channel is formed.
3. The positive voltage also attracts electrons from the n+ source and drain regions into
the channel. Now, if a voltage is applied between the drain and source, the current
flows freely between the source and drain and the gate voltage controls the
electrons in the channel. If we apply negative voltage, a hole channel will be formed
under the oxide layer.
b. Characteristics :
i. The characteristics of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) refer to
the electrical properties and behaviours of the device under different operating conditions.
ii. Threshold Voltage (Vth):
1. The threshold voltage (Vth) is the minimum gate-to-source voltage required to
induce an inversion layer in the semiconductor channel and turn on the MOSFET.
2. It determines the point at which the MOSFET transitions from the off state to the on
state.
iii. Operation Region :
1. Cut-off Region:
a. In the cut-off region, the MOSFET is turned off, and no significant current
flows between the drain and source terminals.
b. Operating point: Both gate-to-source voltage (Vgs) and drain-to-source
voltage (Vds) are below the threshold voltage (Vth).
c. Behaviour: The MOSFET's channel is depleted, preventing the flow of current
from the drain to the source.
d. Characteristics: Drain current (Id) is very small or negligible, and the MOSFET
behaves like an open switch.
e. Application: The cut-off region is used to ensure that the MOSFET is fully
turned off when not in use, minimizing power consumption and preventing
unintended current flow.
2. Saturation Region:
a. In the saturation region, the MOSFET is fully turned on, and significant
current flows between the drain and source terminals.
b. Operating point: The gate-to-source voltage (Vgs) is sufficiently high to
create an inversion layer in the channel, and the drain-to-source voltage
(Vds) is relatively low.
c. Behaviour: The MOSFET's channel is fully enhanced, allowing current to flow
freely from the drain to the source.
d. Characteristics: Drain current (Id) remains relatively constant with changes in
drain-to-source voltage (Vds), and the MOSFET behaves like a voltage-
controlled current source.
e. Application: The saturation region is used in switching applications, where
the MOSFET acts as a closed switch, conducting current between the drain
and source terminals.
3. Linear (Triode) Region:
a. In the linear region, the MOSFET operates between cut-off and saturation,
exhibiting a linear relationship between drain current (Id) and drain-to-
source voltage (Vds).
b. Operating point: The gate-to-source voltage (Vgs) is sufficiently high to
create an inversion layer in the channel, and the drain-to-source voltage
(Vds) is moderate.
c. Behaviour: The MOSFET's channel is partially enhanced, and the drain
current (Id) varies linearly with changes in drain-to-source voltage (Vds).
d. Characteristics: Drain current (Id) is proportional to drain-to-source voltage
(Vds), and the MOSFET behaves like a variable resistor.
e. Application: The linear region is used in amplification and signal processing
applications, such as voltage amplifiers and analog circuits.
iv. Input Characteristics / Transfer Characteristics (Id vs Vgs):
1. Transfer characteristics describe the relationship between drain current (Id) and
gate-to-source voltage (Vgs) at a constant drain-to-source voltage (Vds).
2. They show how the MOSFET's conductivity varies with changes in the gate voltage,
providing insights into its input behaviour and control.
3. In the enhancement mode, the MOSFET starts conducting significant drain current
when Vgs exceeds Vth. The drain current then increases with further increases in
Vgs.
4. In the depletion mode, the MOSFET initially conducts significant drain current when
Vgs is below Vth, and the drain current decreases with further increases in Vgs.
v. Output Characteristics/ Drain Characteristics (Id vs Vds):
1. Output characteristics illustrate the relationship between drain current (Id) and
drain-to-source voltage (Vds) at a constant gate-to-source voltage (Vgs).
2. They depict the MOSFET's behaviour in different operating regions, including
saturation, linear, and cut-off.
3. NMOS MOSFET:
a. Saturation Region: Drain current (Id) remains relatively constant with
changes in drain-to-source voltage (Vds), and the MOSFET behaves like a
voltage-controlled current source.
b. Linear (Triode) Region: Characteristics: Drain current (Id) is proportional to
drain-to-source voltage (Vds), and the MOSFET behaves like a variable
resistor.
4. PMOS MOSFET:
a. Saturation Region: Drain current (Id) remains relatively constant with
changes in drain-to-source voltage (Vds), and the MOSFET behaves like a
voltage-controlled current source.
b. Linear (Triode) Region: Drain current (Id) is proportional to drain-to-source
voltage (Vds), and the MOSFET behaves like a variable resistor.
2. CMOS Inverter :
a. A CMOS (Complementary Metal-Oxide-Semiconductor) inverter is a device that consists of both
NMOS (N-channel Metal-Oxide-Semiconductor) and PMOS (P-channel Metal-Oxide-Semiconductor)
transistors configured in a complementary manner to achieve low power consumption, high noise
immunity.
b. Components of a CMOS Inverter:
i. NMOS Transistor (nMOSFET):
1. The NMOS transistor is an enhancement-mode MOSFET with a positive threshold
voltage (Vth).
2. It acts as the "pull-down" device and conducts when the input is logic LOW (0).
3. The NMOS transistor has its source connected to ground (GND) and its drain
connected to the output node.
ii. PMOS Transistor (pMOSFET):
1. The PMOS transistor is an enhancement-mode MOSFET with a negative threshold
voltage (Vth).
2. It acts as the "pull-up" device and conducts when the input is logic HIGH (1).
3. The PMOS transistor has its source connected to the supply voltage (VDD) and its
drain connected to the output node.

c. Operation of a CMOS Inverter:

i. When the input signal is logic LOW (0), the PMOS transistor is in the ON state, the NMOS
transistor is in the OFF state since its gate-to-source voltage (Vgs) is below its threshold
voltage (Vth), allowing the flow of electrons throughout the gate terminal & generating high
logic output voltage.
ii. When the input signal is logic High (1), the NMOS transistor is in the ON state, the PMOS
transistor is in the OFF state since its gate-to-source voltage (Vgs) is below its threshold
voltage (Vth), allowing the flow of electrons throughout the gate terminal & generating low
logic output voltage.
d. Features of a CMOS Inverter:
i. High Noise Immunity: The complementary operation of NMOS and PMOS transistors ensures
high noise immunity, as any noise present at the input is effectively rejected when
transitioning between logic states.
ii. Low Power Consumption: In steady-state conditions, CMOS inverters consume very little
static power because there is no DC path between VDD and GND.
iii. Rail-to-Rail Output Swing: CMOS inverters offer a wide output voltage swing from VDD to
GND, providing robust logic levels compatible with other digital circuits.
iv. High Input Impedance: The input impedance of a CMOS inverter is very high, minimizing
loading effects on preceding stages.
e. Characteristics of CMOS Inverter :
i. Voltage Transfer Characteristics :
1. The Voltage Transfer Characteristic (VTC) of a CMOS inverter describes the
relationship between the input voltage (Vin) and the output voltage (Vout) over the
entire range of input voltage values.
2. The VTC graphically illustrates how the inverter responds to changes in the input
voltage and provides insights into its operating regions
f. Advantages
i. The CMOS inverter’s steady-state power dissipation is negligible virtually, apart from small
power dissipation because of leakage currents.
 ii. The VTC (voltage transfer characteristic) exhibits a complete o/p voltage swing in between 0
& VDD, and the transition of voltage transfer characteristic is normally very sharp. Thus, the
characteristics of the CMOS inverter look like an ideal inverter.
iii. These inverters use electricity once they are switched ON & OFF resulting in less power
consumption. As a result, these inverters generate extremely less waste heat to make them
highly efficient, so used in small and delicate electronic devices.
iv. These inverters include high noise immunity, which lets them block both incoming &
outgoing frequency spikes.
v. These are low-cost to produce mass.
g. Disadvantages
i. The CMOS inverter disadvantages include the following.
ii. As compared to other inverters, the switching speed of the CMOS inverter is high.
iii. These are very difficult to fabricate due to both the transistors used on the same Silica piece.
iv. It uses two transistors to make an inverter, so it uses more space on the IC as compared to
the NMOS inverter.
h. Applications
i. The applications of CMOS inverters include the following.
ii. CMOS inverters are used in different ICs (integrated circuits) like microprocessors, static
RAM, microcontrollers, data converters, image sensors & transceivers.
iii. These are found in mobile devices, digital cameras, home computers, cell phones, routers,
network servers, modems & virtually each other electronic device that needs logic functions.
3. Noise Margin :
a. Noise margin is representing the tolerance of a digital system to noise in voltage levels. It quantifies
the amount of noise that a circuit can withstand without causing errors in logic levels.
b. Definition: Noise Margin is the difference between the minimum acceptable input voltage for a given
logic level (LOW for logic 0 and HIGH for logic 1) and the actual input voltage at which the output of
the gate switches from one logic level to the other. It ensures that the logic levels remain well-
defined even in the presence of noise.
c. Types of Noise Margin:
i. Low Noise Margin (NM_L): The difference between the minimum acceptable LOW input
voltage and the actual LOW input voltage at which the output switches from HIGH to LOW.
ii. High Noise Margin (NM_H): The difference between the actual HIGH input voltage at which
the output switches from LOW to HIGH and the maximum acceptable HIGH input voltage.
d. Importance:
i. Noise margin is essential for ensuring reliable operation of digital circuits in real-world
environments where noise is inevitable. It helps prevent false triggering and errors in logic
levels caused by noise-induced voltage fluctuations.
ii. A larger noise margin provides better immunity to noise, allowing the circuit to operate
reliably in noisy environments.
e. Calculation:
i. For LOW input voltage (NM_L): NM_L = V_IL - V_OL
ii. For HIGH input voltage (NM_H): NM_H = V_OH - V_IH

where V_IL is the maximum LOW input voltage,

V_IH is the minimum HIGH input voltage,

V_OL is the output voltage at logic LOW,

V_OH is the minimum HIGH output voltage

f. Factors Affecting Noise Margin:

i. Threshold Voltages: The threshold voltages of the transistors in the logic gates determine the
voltage levels at which the gate switches between logic levels.
ii. Power Supply Variations: Fluctuations in the power supply voltage can affect the noise
margin of a circuit.
iii. Signal Propagation Delay: Signal propagation delays can introduce timing uncertainties that
affect the noise margin.
iv. Load Capacitance: The capacitive load connected to the output of the gate can affect its
noise margin.
g. Design Considerations:
i. Designers aim to maximize noise margin by selecting appropriate transistor sizes, biasing
conditions, and operating voltages to ensure reliable circuit operation.
ii. Increasing transistor sizes or operating voltages can improve noise margin but may also
increase power consumption and chip area.
4. Combinational MOS Logic Circuits :
a. A pass transistor, also known as a transmission gate or analog switch, is a basic electronic component
used in digital and analog circuits to selectively allow or block the flow of signals between two nodes.
It acts like a switch controlled by a digital or analog control signal, enabling the passage of signals
when the switch is turned on and isolating the nodes when the switch is turned off. Pass transistors
are commonly implemented using MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors)
due to their low ON resistance and fast switching speed. Let's explore the operation and
characteristics of pass transistors:
b. 1. Structure:
c. A pass transistor typically consists of a single MOSFET connected between two nodes: the input node
and the output node.
d. For NMOS pass transistors, the source terminal is connected to the input node, and the drain
terminal is connected to the output node.
e. For PMOS pass transistors, the source terminal is connected to the output node, and the drain
terminal is connected to the input node.
f. The gate terminal of the MOSFET serves as the control input, determining whether the transistor is
conducting (ON) or non-conducting (OFF).
g. 2. Operation:
h. When the control signal at the gate terminal is at a logic HIGH or positive voltage (for NMOS) or logic
LOW or negative voltage (for PMOS), the pass transistor is turned ON, allowing signals to flow
between the input and output nodes.
i. When the control signal is at a logic LOW or negative voltage (for NMOS) or logic HIGH or positive
voltage (for PMOS), the pass transistor is turned OFF, isolating the input and output nodes and
preventing signal flow.
j. Pass transistors operate bidirectionally, meaning they can pass signals in both directions between the
input and output nodes.
k. 3. Characteristics:
l. Low ON Resistance (Ron): Pass transistors typically exhibit low ON resistance when conducting,
minimizing voltage drop and signal attenuation.
m. High OFF Resistance: Pass transistors have high OFF resistance when non-conducting, ensuring
minimal leakage current and signal isolation.
n. Bidirectional Operation: Pass transistors can pass signals bidirectionally between input and output
nodes, making them versatile for various applications.
o. Fast Switching Speed: Pass transistors offer fast switching speeds, enabling rapid signal propagation
through the circuit.
p. 4. Applications:
q. Signal Routing: Pass transistors are commonly used for signal routing and switching in digital and
analog circuits.
r. Level Shifting: Pass transistors can be used for level shifting, converting signals between different
voltage domains.
s. Multiplexing/Demultiplexing: Pass transistors are employed in multiplexers and demultiplexers to
selectively route signals between multiple input/output channels.
t. Analog Switching: Pass transistors are used in analog circuits for analog signal switching and routing.
5. Clock Distributions :
a. Clock distribution refers to the process of distributing clock signals across the entire chip to
synchronize the operation of different components and circuits. A well-designed clock distribution
network is crucial for ensuring proper timing and reliable operation of digital circuits.
b. There are several techniques for distributing clock signals, including two complementary approaches:
H-tree and Balanced Tree.
c. H-tree:
i. Description: The H-tree topology is a hierarchical clock distribution network commonly used
in large VLSI chips. It resembles the shape of the letter "H" and consists of multiple levels of
clock buffers and repeaters interconnected in a tree-like structure.
ii. Operation:
1. The clock signal is first generated at a central point, typically the clock source or a
clock generation circuit.
2. The clock signal is then distributed to multiple branches, forming the horizontal
segments of the "H."
3. Each branch is further divided into smaller segments, forming the vertical segments
of the "H."
4. Clock buffers and repeaters are inserted at various points along the tree to maintain
signal integrity and compensate for signal delays.
iii. Advantages:
1. Hierarchical structure allows for efficient distribution of clock signals across large
chip areas.
2. Reduces skew and delay variations by balancing the lengths of clock paths.
3. Provides scalability for accommodating chips with varying sizes and complexities.
iv. Disadvantages:
1. Requires careful design and analysis to ensure proper synchronization and timing
closure.
2. Can introduce additional power consumption and area overhead due to the insertion
of clock buffers and repeaters.
d. 2. Balanced Tree:
i. Description: The Balanced Tree topology is another common approach for clock distribution,
particularly in smaller and less complex VLSI chips. It resembles a binary tree structure with a
single clock source at the root and multiple clock buffers at each level branching out to leaf
nodes.
ii. Operation:
1. The clock signal is generated at the root of the tree and distributed to multiple
branches, each representing a level of the tree.
2. At each level, clock buffers are inserted to drive the clock signals to the next level of
branches.
3. The process repeats recursively until reaching the leaf nodes, where the clock signals
are distributed to individual circuit blocks or regions.
iii. Advantages:
1. Simple and straightforward topology suitable for smaller chip designs.
2. Provides uniform distribution of clock signals with minimal skew and delay
variations.
3. Requires less area and power overhead compared to more complex distribution
schemes.
iv. Disadvantages:
1. Limited scalability for large chip designs due to the hierarchical nature of the tree
structure.
2. May suffer from higher skew and delay variations compared to H-tree in larger
designs.
e. In summary, H-tree and Balanced Tree are two complementary approaches to clock distribution in
VLSI design, each offering advantages and disadvantages depending on the size, complexity, and
performance requirements of the chip. Designers need to carefully evaluate and select the
appropriate clock distribution topology based on the specific constraints and objectives of their
design.
6. Packages :
a. a package refers to the physical enclosure that houses and protects the integrated circuits (ICs) and
other electronic components mounted on a printed circuit board (PCB). Packages serve several
essential functions in the overall electronic system:
i. Protection: One of the primary functions of a package is to protect the delicate
semiconductor components from environmental factors such as moisture, dust, mechanical
shock, and electromagnetic interference (EMI). The package acts as a barrier, shielding the
ICs from external influences that could affect their performance or reliability.
ii. 2. Interconnection: Packages provide a means of electrically connecting the ICs to the
external circuitry on the PCB. They typically feature metal leads, pins, or solder balls that
establish electrical connections between the ICs and the PCB traces, enabling signal
transmission, power distribution, and communication with other devices.
iii. 3. Thermal Management: Packages play a crucial role in dissipating heat generated by the ICs
during operation. Many packages incorporate thermal management features such as heat
sinks, thermal pads, or exposed metal surfaces to facilitate efficient heat transfer away from
the ICs and into the surrounding environment.
iv. 4. Electrical Isolation: Packages provide electrical isolation between individual ICs and
components mounted on the PCB, preventing short circuits and electrical interference
between adjacent devices.
b. Types of Packages:
i. Dual In-line Package (DIP): DIP packages are among the oldest and most widely used types of
IC packages. They feature two parallel rows of leads or pins extending from the sides of the
package, which can be inserted into a socket or soldered directly onto the PCB.
ii. Quad Flat Package (QFP): QFP packages have a square or rectangular shape with leads
arranged in a grid pattern around the periphery of the package. They offer higher pin
densities and are commonly used in microcontrollers, processors, and other high-density ICs.
iii. Ball Grid Array (BGA): BGA packages feature an array of solder balls arranged on the
underside of the package, allowing for direct mounting onto the PCB surface. BGAs offer
excellent electrical performance, thermal characteristics, and mechanical reliability, making
them suitable for high-performance applications.
iv. Small Outline Integrated Circuit (SOIC): SOIC packages are similar to DIP packages but have a
smaller form factor and surface-mount design. They are commonly used in consumer
electronics, networking devices, and industrial applications.
v. Quad Flat No-Lead (QFN) Package: QFN packages have leads arranged on the underside of
the package, similar to BGAs, but without the solder balls. Instead, the leads are exposed
metal pads that are soldered directly to the PCB surface, offering a compact and cost-
effective solution for many applications.
vi. Chip-Scale Package (CSP): CSP packages are designed to be as small as possible, with the IC
die and package dimensions closely matched. They offer high integration density and are
commonly used in mobile devices, wearable electronics, and other space-constrained
applications.
c. Overall, packages are essential components in VLSI design, providing protection, interconnection,
thermal management, and electrical isolation for integrated circuits and electronic systems.
Designers must carefully select the appropriate package type based on the specific requirements and
constraints of their design, considering factors such as size, pin count, thermal performance, and
cost.