PDPM Indian Institute of Information Technology Design and Manufacturing Jabalpur

B.Tech. I Year (Common to all the branches)

End-Term Examination, April 2023
OE2E03: Digital System Design
Max Marks:50 Time Duration: 3 hours

Note: (i) Attempt all the questions. There are four sections in the question paper.
(ii) Give the suitable assumption whenever required. No marks will be given for the answers
without proper explanation/solution steps.
Section-1(Each question carries 2 marks) TotalMarks:2x4-8
Q.l(a) Define the terms Macro-cell and Interconnect Array used in CPLDs.
(b) Write the significance of the keyword ALIAS in VHDL using one example.
(c) Discuss merits and demerits of Antifuse programming technology.
(d) In what type of applications shoulda designer use a CPLD rather than an FPGA?
Section-2 (Each question carries 3 marks) Total marks:3x2=6
Q. 2(a) Explain two address microcode and one address microcode with the help of diagram.
(b) Discuss the terms Mapping, Placement, and Routing in VHDL.
Section-3 (Each question carries 4 marks) Total marks: 4x4=16
Q3(a) Explain control path and data path in detail for the implementation of controller.
(b) Ilustrate the concept of microprogramming? Write how it is different from hardwire control
logic.
(c) How many logic blocks are required to create a8:1 Multiplexer as in Figurel? Also show
the data path using the same figure.
(d) What is an FPGA technology? How it is different from traditional gate arrays? Write its
advantages and disadvantages over it.

Section-4 (Each question carries 5 marks) Total marks:5x4-20

Q.4 (a) Use Shannon's expansion theorem around e and f for the function Y, so that it can be
implemented using a minimum number of four-variable functions.
Y= ab'cdef +a'bc'd'e + b'c'ef'+ abcde'f
(b) Discuss in detail the SRAM programming technology available in FPGA.
(c) Design ASM chart for the FSM shown in Figure 2.
(d) Prepare a microprogrammed table for the ASM chart shown in Figure 3. Calculate the size
of the microprogram ROM for the same.

0/0 1/0
,1XFutctiong
gencralor
X,1 LUT4
00

4 YFusction
generatar
SIZ3 S2/Z4
LUTA
0

Fig.1 Fig. 2 Fig.3

**** End of the question paper****

TA
 PDPM Indian Institute of Information Technology Design and Manufiacturing Jabalpur
B.Tech. II Year (Common to all the branches)
Mid-Term Examination, Feb 2023
OE2E03: DigitalSystem Design Time Duration: 2 hours
Max Marks:40

question paper.
Note: (1) Attempt all the questions. There are four sections in the marks will be given for the answers
assumption whenever required. No
(1) Give the suitable
without proper explanation/solution steps.
Total Marks:1x4=4
Section-1(Each question carries 1mark)
synthesis in VHDL.
Q. 1(a) Write down the difference between simulation and
(b Write the role of CAD tools in VHDL.
VHDL. Give the examples
(c) How sequential andconcurrent statements differ to each other in
of both. VHDL?
(d Which design style of modelling is best suitable for hardware implementation in
Why?
Section-2 (Each question carries 2 marks) Total marks:2x4=8
Q. 2(a) Write a VHDL code using process statement that generates a clock with a different on-off
period. Figure shows the generated waveform.
CLK
20 32 52 64 84 96 ns assumption
(b) What is the use of keyword port map in VHDL. Brief with the help of one example.
(c) Write the two-two examples of relational and shift operators.
(d) Explain for loop with one example in VHDL.
Total marks: 3x4-12
Section-3 (Each question carries 3 marks)
Attempt any four questions from this section.
Q.3 (a) Enlighten the significance of data path design in digital system design flow step.
Write the VHDL code for Toggle (T-flip flop). Include entity declaration and process
(b)
statements for the same.
What is the significance of delay in VHDL? Write down the difference between inertial
(c)
and transport delay?
(d) What do you understand by PLDS? Write its types and difference amongst them in brief.
(e) How constant, variable and signals differ in VHDL? Write the application of the same.
Total marks:4x4=16
Section-4 (Each question carries 4 marks)
Attempt any four questions from this section.
Q.4(a) If A=111, B =101 and C =110", then what will be the values of the following statements?
(i) (A & B) or (B & C) (ii) Aror 2 (ii) A sla 2 (d) A & not B (e) A or B and C.
Draw the diagram and write a VHDL code for 2:4 decoder. Include entity and architecture
(b)
declaration. Also write which modelling style you have utilized.
(c) Compute the size of the ROM needed to implement the 4-bit binary parallel adder? Justify
your answer with proper explanation. Also draw the diagram of 4-bit binary parallel adder.
(d) Write a VHDL code for 4:I multiplexer. Include entity and architecture declaration. Also
write which modelling style you have utilized.
(e) What do the following statements represent? Explain.
type assumption is array downto 0) of bit;
signal data zero: assumption;
variable data alt: assumption:= "10101010";
constant data one: assumption:= (others=> 1);