Digital Design And Computer Organisation SSSE,Tumkur

SRI SIDDHARTHA
SCHOOL OF ENGINEERING
A CONSTITUENT COLLEGE OF SRI SIDDHARTHA ACADEMY OF HIGHER EDUCATION
(“DEEMED TO BE UNIVERSITY”)

Department of Computer Science and

Engineering
DIGITAL DESIGN AND COMPUTER ORGANIZATION
LABORATORY MANUAL
Subject Code: BCS302
Prepared by

Mrs. Sushma B N
Assistant Professor, Dept. Of ECE

and

Mr. MD Tanveer
Assistant Professor, Dept. Of EEE

Affiliated to Visvesvaraya Technological

University, Belagavi, Karnataka -

590018 2024-2025

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DIGITAL DESIGN AND COMPUTER ORGANIZATION

LABORATORY SEMESTER – III (CS)
[As per Choice Based Credit System (CBCS) scheme
Experiments
1. Design and implement Half Adder using basic gates NAND gates.
2. Design and implement Full Adder using basic gates NAND gates.
3. Design and implement Half subtractor using basic gates NAND gates.
4. Design and implement Full subtractor using basic gates NAND gates.
5. Realize Binary to Gray code conversion using Ex-OR gates.
6. Realize Gray to Binary code conversion using Ex-OR gates.
7. Design and implement half adder using basic gates.
8. Design and implement Full adder using basic gates.
9. Design and implement 4-bit BCD to excess-3 code converter
10. Design and implement 4-bit excess-3 to BCD code converter
11. Realize the (i) Master-Slave JK Flip-Flop (ii) D Flip-Flop (iii) T Flip-
Flops
using NAND Gates.

Conduct of Practical Examination:

● All laboratory experiments are to be included for practical examination.

● Students are allowed to pick one experiment from the lot.

● Strictly follow the instructions as printed on the cover page of answer
script for breakup of marks.
● Change of experiment is allowed only once and Marks allotted to the procedure
part to be made zero
Reference Books:
1. David A Bell, “Fundamentals of Electronic Devices and Circuits Lab Manual”,
5th Edition, 2009, Oxford University Press.
2. Albert Malvino, David J Bates, Electronic Principles, 7th Edition, McGraw
Hill Education, 2017.
3. Fundamentals of Logic Design, Charles H Roth Jr., Larry L Kinney, Cengage
Learning, 7th Edition.

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Laboratory Session: Introduction to Analog Electronic components.

Laboratory Session. Logic design components

Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR are known as universal gates. Basic
gates form these gates.
AND GATE:

The AND gate performs a logical multiplication commonly known as AND function. The output
is high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The output is low
when the input is high.
NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
X- OR GATE:

The output is high when any one of the inputs is high. The output is low when both the inputs are
low and both the inputs are high.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

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AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

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NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE:

SYMBOL: PIN DIAGRAM:

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2- INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3- INPUT NAND GATE:

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NOR GATE

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EXPERIMENT: 1

Design and implement Half Adder using NAND gates

AIM: To realize Half Adder using Basic gates NAND gates.

COMPONENTS REQUIRED:
1) IC 7400
2) Patch Cords.
3) IC Trainer Kit.
THEORY:
Half-Adder: A combinational logic circuit that performs the addition of
two data bits, A and B, is called a half-adder. Addition will result in two
output bits; one of which is the sum bit, S, and the other is the carry bit, C.
The Boolean functions describing the half-adder are: S =A ⊕ B and C = A B

HALF ADDER:
i) Basic Gates ii) NAND Gates

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PROCEDURE:
● Check the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT: 2

Design and implement Full Adder using NAND gates

AIM:
To realize Full Adder using Basic gates NAND gates.

COMPONENTS REQUIRED:
1) IC 7400.
2) Patch Cords.
3) IC Trainer Kit.

THEORY:
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry
bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits,
A and B, and a carry-in bit, Cin , is called a full-adder.

The Boolean functions describing the full-adder are: S = (x ⊕ y) ⊕ Cin and C = xy + Cin (x ⊕ y)

FULL ADDER:

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From Full Adder Truth Table

ii) BASIC GATES

f
iii) NAND GATES

PROCEDURE:
● Check the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT: 3

Design and implement Half Subtractor using NAND gates

AIM:
To realize Half subtractor using Basic gates NAND gates.

COMPONENTS REQUIRED:
1) IC 7400.
2) Patch Cords.
3) IC Trainer Kit.

THEORY:

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to
realize it is called a half subtractor.
The Boolean functions describing the half- Subtractor are: S =A ⊕ B and C = A’ B

HALF SUBTRACTOR:
TRUTH TABLE BOOLEAN EXPRESSIONS

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iv) Basic Gates ii) NAND Gates

PROCEDURE:
● Check the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT: 4

Design and implement Full Subtractor using NAND gates

AIM:
To realize Full subtractor using Basic gates NAND gates.

COMPONENTS REQUIRED:
1) IC 7400.
2) Patch Cords.
3) IC Trainer Kit.

THEORY:

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out Br bit. This is called full subtraction.
The Boolean functions describing the full-subtractor are:
D = (x ⊕ y) ⊕ Cin and Br= A’B + A’(Cin) + B(Cin)

FULL SUBTRACTOR
TRUTH TABLE

From above Truth table

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BASIC GATES
i) NAND

PROCEDURE:
● Check the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT-5

Realize Binary to Gray code conversion using Ex-OR gates

AIM:
To realize Binary to Gray code converter using EX-OR gates and verify the truth table.

COMPONENTS REQUIRED:
1.IC 7486
2. Patch Cords
3. IC Trainer Kit.
Theory:
Binary information has two weighted codes. The gray code is the unwieghted code. The conversion is
used for transferring the information in communication system. The gray code is also called as weight
less code.
Binary to Gray Conversion:-

Decimal B3 B2 B1 B0 G3 G2 G1 G0
no.

0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

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K-map:-
For G0 B1 B0For G1

B1 B0 B3 B2 B3 B2 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1
G0=B1⊕Β0 G2= B2⊕Β3

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G1= B1⊕Β2 FOR G3

B3 B2

BINARY TO GRAY CODE USING EX-OR GATES:-

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REALIZATION USING NAND GATES:-

RESULT:Binary to gray code conversion is realized using EX-OR gates and

NAND gates.

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EXPERIMENT-6

Realize Gray to Binary code conversion using Ex-OR gates

AIM:
To realize Gray to Binary code converter using EX-OR gates and verify the truth table.

COMPONENTS REQUIRED:
1.IC 7486
2. Patch Cords
3. IC Trainer Kit.
Theory:
Binary information has two weighted codes. The gray code is the unwieghted code. The conversion is
used for transferring the information in communication system. The gray code is also called as weight
less code.

GRAY BINARY
Decimal G3 G2 G1 G0 B3 B2 B1 B0
no.

0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
14 1 1 1 0 1 0 1 1
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0

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8 1 0 0 0 1 1 1 1

K-map:-
FOR B0:- G1 G0

FOR B1:- FOR B2:-

G1 G0 FOR B3:

B3=G3

1 1 1 1
1 1 1 1

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RESULT: Gray to Binary code conversion is realized using EX-OR gates and
NAND gates.

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EXPERIMENT-7
Design and implement half adder using basic gates
AIM:
To design and implement half adder using basic gates.

COMPONENTS REQUIRED:
1.IC 7486 , IC 7408
2. Patch Cords
3. IC Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is
called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other
is the carry bit, C.
The Boolean functions describing the half-adder are: S =A ⊕ B and C = A B

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PROCEDURE:
● Check the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT-8
Design and implement Full adder using basic gates

AIM:
To design and implement Full adder using basic gates.

COMPONENTS REQUIRED:
1.IC 7400.
2.Patch Cords.
3. IC Trainer Kit.

THEORY:
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry
bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits,
A and B, and a carry-in bit, Cin , is called a full-adder.

The Boolean functions describing the full-adder are: S = (x ⊕ y) ⊕ Cin and C = xy + Cin (x ⊕ y)

FULL ADDER:

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From Full Adder Truth Table

v)BASIC GATES

PROCEDURE:
● Check the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT-9

Design and implement 4-bit BCD to excess-3 code converter

AIM:
To design and implement 4-bit BCD to excess-3 code converter.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be
inserted between the two systems if each uses different codes for same information. Thus,
code converter is a circuit that makes the two systems compatible even though each uses
different binary code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as G3, G2, G1, G0. from the truth table, combinational circuit is designed.
The Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

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K-Map for E3: K-MapforE2:

E3 = B3 + B2 (B0 + B1)
K-Map for E1: K-Map for E0:

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TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1

LOGIC DIAGRAM:
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables

RESULT: The truth table of the above circuits is verified.

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EXPERIMENT-10

Design and implement 4-bit excess-3 to BCD code converter

AIM:
To design and implement 4-bit excess-3 to BCD code converter.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be
inserted between the two systems if each uses different codes for same information. Thus,
code converter is a circuit that makes the two systems compatible even though each uses
different binary code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as G3, G2, G1, G0. from the truth table, combinational circuit is designed.
The Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

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EXCESS-3 TO BCD CONVERTOR

K-Map for A: K-Map forB:

A = X1 X2 + X3 X4 X1

K-Map for C: K-Map for D:

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TRUTH TABLE:| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

PROCEDURE:
(iv) Connections were given as per circuit diagram.
(v) Logical inputs were given as per truth table
(vi) Observe the logical output and verify with the truth tables
RESULT: The truth table of the above circuits is verified.

EXPERIMENT-11
Realize the (i) Master-Slave JK Flip-Flop (ii) D Flip-Flop (iii) T
Flip- Flops using NAND Gates.

AIM:
Truth Table verification of Master-Slave JK, D & T Flip-Flops using NAND Gates.

COMPONENTS REQUIRED:
i) IC 7400, IC 7420
ii) Patch Cords
iii) IC Trainer Kit
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THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values. Sequential
logic circuits often require a timing generator (a clock) for their operation. The latch (flip-flop) is
a

basic bi-stable memory element widely used in sequential logic circuits. Usually there are two
outputs, Q and its complementary value. Some of the most widely used latches are listed below.
Flip flops are the basic building blocks in any memory systems since its output will remain in its
state until it is forced to change it by some means. JK FF: The indeterminate output state of SR
FF when S=R=1 is avoided by converting it to a JK FF. When flip flop is switched on its output
state is uncertain. When an initial state is to be assigned two separate inputs called preset and clear
are used. They are active low inputs.
Master Slave FF: The race around condition of JK FF is rectified in master slave JK FF. Racing
is toggling of output more than ones during the positive clock edge. MSJK FF is created by
cascading two JK FF. The clock is fed to the first stage (Master) and is inverted and fed to the
second stage (slave). This ensure that the master is always followed by the slave and eliminate the
chance of racing
D FF: It has only one input called as D input or Data input. The input data is transferred to the
output after a clock is applied. D FF can be derived from JK FF by using J input as D input and J
is inverted and fed to K input
T FF: T stands for Toggle. The output toggles when a clock pulse is applied. T FF can be derived
from JK FF by shorting J and K input

1) Master-Slave JK

Circuit Diagram & Truth Table

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2) D FF:

Circuit Diagram & Truth Table

3)T FF:
Circuit Diagram & Truth Table

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Note: Preset and Clear always equal to 1 for verifying the Truth Tables of MS JK, T FF, D FF.

PROCEDURE:
● Check all the components for their working. Insert
the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Verify the Truth Table and observe the outputs.

RESULT: Verification truth table of Flip-Flop done

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