A Universal Quasi Linear Circuit Analysis Program

and its applications. (Written in late 2003 by Gerhard A. Hofbauer, Graz)

Abstract - A fast universal applicable circuit analysis technique based on Kirchhoff’s laws will be
presented and stepwise implemented. The Z-Parameter based circuit description will be solved with
respect to device currents. An arbitrary number of multiport devices, nonlinear components like BJT’s or
diodes as well as controlled and fixed sources can be used to form a complex network which will be
transformed to a symbolically composed matrix. The matrix will be solved using direct and iterative
methods, and the results will be small-signal AC and bias-point DC currents. Through the symbolical
character of the matrix fast tuning is possible without repetitive circuit-to-matrix transformations.

I. Introduction

Kirchhoff formulated two general applicable rules, describing the distribution of discrete voltages and currents in
arbitrary complex linear or nonlinear circuit networks. The first rule further called “node rule” describes the
current distribution in an ideal connection of an unrestricted number of lossless conductors.

I1
I4

I2
I3

Fig.1 General network node

Figure 1 shows a connection of four conductors in one node. As there can be no charge stored in a node, the total
charge in the connection will be constant. This assumption does also imply that the charge-carriers can not be
compressed in the node and so accumulated. This simplification does normally not affect circuit design, because
effects in physical nodes can be modeled by parasitic circuit elements. As electrical current is the derivation of
the charge with respect to time, the current in the node must be zero (as the charge Q is constant over time).
So rule I. states:

∑I
n
n = 0 (0.1)
For the node in Figure 1, equation (0.1) reduces to

I1 + I 3 − I 4 − I 2 = 0 (0.2)

where positive signs are dedicated to currents flowing to the node and negative signs for currents flowing out of
a node. This is an arbitrary assumption, and can be changed without influence to analysis. If the direction of a
current has been assumed to point in the wrong direction, the calculated current will be simply negative.
Although current direction plays no significant role in linear circuit analysis, nonlinear elements like diodes do
greatly depend on it.

The second rule, further called “loop rule”, concerns voltages in a closed loop. As in electrical-field-theory the
potential over an arbitrary closed loop in a curl-free electrical field is zero, the same is true for electrical
networks, which are curl-free from obvious reasons.
 V3 V01
I3 R3

I1 I2

V1 R1 R2 V2

V4
V02
R4
I4

Fig.2 General network loop.

Figure 2 shows a typical network loop including two voltage sources. The second rule of Kirchhoff states now,
that the voltage sum around a loop must be zero, or mathematical formulated:

∑V
n
n = 0 (0.3)

For the network in Figure 2 this reduces to,

V1 − V02 + V4 + V2 − V01 + V3 = 0 (0.4)

or in terms of currents, using Ohm’s law to:

I1 R1 + I 2 R2 + I 3 R3 + I 4 R4 − V02 − V01 = 0 (0.5)

If the voltage sources are moved to the right side of equation (1.5) it transforms to:

I1 R1 + I 2 R2 + I 3 R3 + I 4 R4 = V02 + V01 (0.6)

This gives a hint, how equ. (1.3) can be converted to a sum of currents like in the node rule.
So equation (1.3) changes to:

∑I R
n
n n = − ∑ V0 m (0.7)
m

The left side of equation (1.7) defines the loop voltage drops on the resistors and the right side the source
voltages. The same Transformation can be made with (1.1) and it changes to:

∑I
n
n = −∑ I 0 m (0.8)
m

The right side of equ. (1.8) indicates the sum of current sources which are connected to a node.
While normally the values of voltage- and current-sources are given for analysis, the currents are unknown.
That for a linear equation system can be set up from several terms like (1.7) and (1.8). As for computational
processing matrix representations are advantageous, above expressions will be transformed in such one. The
number of unknowns are given by the amount of unknown currents. To further generalize the achieved results,
several additions must be made. As until now only one port devices has been investigated, multiport devices
should now be considered. Another more simple transition is the change from real-valued resistors to complex
valued, frequency dependent impedances Z. The formal underscore of complex variables will be omitted for sake
of better understandability and used for matrix indication.
One port devices like capacitors, inductors, resistors etc. can be described by whether frequency- or time
domain-parameters. However, as this paper concerns with AC analysis, the frequency domain representation will
be used. So, for linear conditions, a one port device can be described by one frequency dependent parameter.
The parameter used here for analysis is the frequency dependent impedance Z(jω).

V Z

Fig.3 Simple one port-device.

A general one port-device is shown in Figure 3. The one-port has two terminals, which will be further called as
“ports”. Port 0 is the common port, which makes no sense for one port devices, aside current flow direction
specification. Current is assumed to flow into port 1 and out of port 0. The equation for V-I-relation is given by
Ohm’s law:

V = Z ⋅ I (0.9)
From study of Figure 3 it is obvious that the current out of port 0 is the same as into port 1.
Things become a little bit more complicated, as a second port is added to the one port device of Figure 3.

I1 1 2 I2

V1
Z V2
0 I0

Fig.4 Simple two port-device.

Figure 4 shows a simple two port-device. As in the example above it has a common port 0 and two general ports
1 and 2. Out of two port theory, the voltage-current relation is given by:

V1 = I1Z11 + I 2 Z12
V2 = I1Z 21 + I 2 Z 22 (0.10)
I 0 = I1 + I 2

While Z11 and Z22 describe the pen-circuit input- and output-impedances and so the relations of V1 to I1 and V2 to
I2, the (trans-)impedances Z12 and Z21 are interrelated. As voltages and currents can be described by vectors:

  V   I 
V =  1  and I =  1  (0.11)
 V2   I2 

The impedances Zmn can be displayed in matrix representation as:

Z Z12 
Z =  11  (0.12)
 Z 21 Z 22 

With the different formal representation, above results can be used with the equations in (1.10) and will give:

 
V = Z ⋅ I (0.13)

which can be seen as generalized Ohm’s law.

Equation (1.13) is also valid for multiport devices with more than two ports. Matrix-size will rise with the square
of the port voltages or currents (without the common port of course).
A general N-port-device has following characteristics:

a) A N-port-device has N+1 port-terminals

b) A N-port-device introduces N unknown currents
c) A N-port-device has N port voltages.
d) The Z-matrix of a N-port has N2 Z-Parameters
e) The current out of the common terminal (port 0) is the sum of the currents flowing into the other general ports.

As the amount of unknowns in a complex circuit network is very easy defined as:

M
N = ∑ N i (0.14)
i =1

where M is the number of multiport devices in the network and Ni the number of unknowns for the multiport
with the number i. With all the above derived relations following matrix equation can be set up:



 D    I0 
  ⋅ I = 

  (0.15)
Z   V0 

where D represents a (m x N) submatrix consisting of ones and zeros which are extracted out of the node rule
with m nodes, and Z represents a ((N-m) x N) submatrix generated from the loop rule, out of N-m linear





independent voltage loops. The vectors I 0 and V 0 represent the fixed voltage- and current-sources.

The quest is now to find the unknown vector I , which represents the unknown port-currents.
The solution can be easily found by matrix inversion and can be written formally as:



  D  −1  I 0 
I =   ⋅ 

  (0.16)
 Z   V0 

which can be solved by several numerical techniques. However some questions still remain. How many node
equations have to be extracted? How many loop voltage equations? Can the matrix be singular? And if yes, how
can this be circumvented?

II. Focus
As in chapter I. defined, the total of unknown currents is N, further let C be the number of current-sources and U
be the number of voltage sources in the circuit. It can be shown that a circuit with E = N+C+U ports will have a
maximum of E nodes. This means that the number of nodes n is :

2 ≤ n ≤ N + C + U (2.1)
The lower border of 2 is logical, as the minimum circuit is a source connected to a one-port-device.
One thing that is not obvious is that only a maximum of N+C+U-1 nodes can be used for setting up equations, as
the last remaining node can be composed of linear combination of the other.
1

I01
R1

I1
2
Fig.5 Simple network with current source.
Figure 5 illustrates this observation. The circuit contains a current source with driving a current I01 and a resistor
R1 with a current I1 flowing through it. Two nodes can be extracted and numbered as shown in circles in Figure
5. For these two nodes the node equations can be set up as:

Node 1: I1 - I01 = 0 and

Node 2: I01 - I1 = 0

It is obvious that these two equations are linear dependent. That for it can be stated, that it is possible to create m
useful nodes out of a circuit with the limits:

0 ≤ m ≤ N + C + U − 1 (2.2)
and as the maximum number of unknowns is N (2.2) can be reformulated as:

0 ≤ m ≤ min (number of nodes in the circuit – 1, N ) (2.3)

Just the lower limit of zero has to be explained.
1

V01 R1

I1
2
Fig.6 Simple network with voltage source.

Figure 6 shows a simple network containing a voltage source V01 and a resistor R1. It is not possible to set up any
node current equation. That for this circuit contains no useful nodes and so m = 0.

Similar considerations have to be made for the number of voltage loops. The limits for the maximum number of
possible loops l lies at:

( N + C + U − 1)( N + C + U )
0≤l ≤ (2.4)
2
The lower limit of l is zero as shown in Figure 5, there is no loop equation possible.
The upper limit can be calculated from parallelizing a voltage source with N resistors. This will give the
maximum of variations of different loop-equation as stated in (2.4). As stated in equation (2.3) a maximum of N
loops is useful so (2.4) can be reformulated to:

0 ≤ l ≤ N (2.5)
As it can be seen from equ.(2.4) more voltage loop equations than unknowns are possible in general. This
automatic leads to the problem of the proper selection of loop equations out of the pool of the possible, while
keeping the loop equations linear independent. This problem does not occur with the node equations. So it is a
good point to start with setting up as many node equations as possible, and then filling the remaining matrix
positions with the loop values. However, this procedure does not preserve from linear dependent matrix ill
conditioning, but it lowers the probability. For the right loop equation setup, a more sophisticated approach is
needed, as it will be shown later. As seen in Figure 5 and 6 it is not possible to build a node equation, if a voltage
source is connected to that node, and it is not possible to build a loop equation if a current source is in the loop.
This consequence reduces the number of useful nodes and loops, and can be even lower in sum as N. That
means, that insufficient equations can be found to solve for the unknown currents.
 1

V01 R1

I3
I1
2
I01
R3

V02 R2

I2
4
Fig.7 Advanced electrical network

Figure 7 shows such a circuit. Neither for node 1 ,2, 3 nor node 4 a corresponding equation can be found, as all
nodes are connected to voltage sources. Only two loop equations can be found with V01 and I1.R1, as well as V02
and I2.R2. As no loop can be made over R3, only 2 equations can be set up for 3 unknown currents. To solve such
a circuit, a new concept must be introduced, which will be called further “collapsed nodes”.
The main idea behind the concept is, that Kirchhoff’s first rule can be applied to more than one node. It is
possible to collapse several nodes into one, and the rule must also be fulfilled, as there can be no charge stored in
the nodes. So a tree of voltage sources can be collapsed to one single node, and additional node equations can be
set up.

IE1
I1 1
I2

R1 V01 R2

IE4 I1 I2 IE2
2 I4
4 I3
V02
R3 V03 R4

I4

I3 3
IE3

Fig.8 Application of the “collapsed” node method.

Figure 8 shows a typical example on which the collapsed node method can be applied. It is not possible to set up
a conventional node equation, as a voltage source is connected to each node, and the current through a voltage
source is not defined. If we assume now that no additional voltages source is connected through the nodes 1 to 4,
which means that the currents IE1 to IE4 are from either current sources or passive components, the tree1
consisting of the voltage sources V01, V02 and V03 can be collapsed to one single node. As the nodes 1 to 4 sum
now in one single equation, following term can be drawn:

I E1 − I1 − I 2 + I 2 + I 4 + I E 2 + I E 3 − I 4 − I 3 + I 3 − I E 4 + I1 = 0 (2.6)

This equation can be simplified to:

I E1 + I E 2 + I E 3 − I E 4 = 0 (2.7)

Which shows that this “collapsed” circuit can be seen as a single node.
The same procedure can be applied on the circuit in Figure 7. If we collapse node 1 and node 2, it comes
apparent that I3 =-I01, which was the missing equation to solve for all circuit currents. Relation 2.3 stays still true,
only the “number of nodes in the circuit” changes to the “number of nodes plus the number of collapsed nodes”.
Voltage loops can not be found that easy as node equations. As loops must be closed, several possibilities exist
to go from the start node through the network back to this point. Many traps lurk in the voltage loop setup, as it
can be seen in this paragraph. The first problem is to find a suitable startnode. A startnode must have at least two
connections, as the graph must take one connection into the network and one connection to come back. Also
current sources are not suitable for voltage loops, as the voltage across them is not defined. That means:

Total connections – current-sources connected to node > 1 (2.8)

If this relation is accomplished, a suitable node has been found. For better visibility, a graph diagram will be
used, which consists of nodes, and appropriate voltages between them. The nodes will be shown as circles with a
number in it, the voltages between them as arrows from the general node to the common node. Figure 9 shows
the graphs for a one-port device in a) and for a four port device in b). As the voltage between general nodes is
not defined by multiport-parameters, no voltage connections between them exist.

1 1 2 3 4

Vn+1 Vn+2
Vn+3
Vn
Vn

0 0

a) b)
Fig.9 Simple graphs for a one-port- and a four-port-device.

Now, from these basic considerations a network for loop analysis, consisting of nodes and arrows, can be
sketched.
V1
1 2

V2 V3

V4
3 4

V6 V7

V5
5 6

Fig.10 Simple voltage loop network.

Figure 10 shows a simple network consisting of 6 nodes and 7 voltages between the nodes. Node 1 has two
connections which satisfies equation (2.8) and is therefore suitable as startnode. A total of three loop equations
can be set up, but only two of them are linear independent. Beginning with node 1 the path through one complete
loop-equation setup should be traced.
V1 V1 V1 V1 V1
1 2 1 2 1 2 1 2 1 2

V2 V3 V2 V3 V2 V3 V2 V3 V2 V3

V4 V4 V4 V4 V4
3 4 3 4 3 4 3 4 3 4

V6 V7 V6 V7 V6 V7 V6 V7 V6 V7

V5 V5 V5 V5 V5
5 6 5 6 5 6 5 6 5 6

Fig.11 Tracing the loop of the network of Figure 10.

As it can be seen in Figure 11, the loop goes over V1, V3, V7, V5 and V6 to node 3, from this node some
additional considerations must be done as presented in Figure 12.
V1
1 2

V2 V3

V4
3 4

V6 V7

V5
5 6

Fig.11 Wrong loop condition through shortcut

It is not apparent for an algorithm where a voltage edge leads to, so it is possible that the loop closes not with the
start node, but with a shortcut like in Figure 11, where the loop is closed over V4, where V1 and V3 remain
outside the loop, and so no correct loop equation can be formulated. To prevent such “shortcuts” the algorithm
must remember all visited nodes, and edges leading to nodes which are already in the visited node lists must be
omitted. Such a feature can be easily implemented in recursive algorithms.

Get_Voltage_Loop(Current Node, Visisted node list, Start Node)

Add current node AND used Edge to Visited node list
IF Current Node = Start Node AND Visited node list has more than one entry
THEN RETURN with STATUS = FINISHED
DO{ get next edge (En) from current node
Nn = the node connected En
IF Nn is not in the visited node list AND node Nn has more than one
Edges connected to it AND Nn is not equal to the current node
THEN DO{
Status = Get_Voltage_Loop(Nn, Visisted node list, Start Node)
IF Status = FINISHED THEN RETURN FINISHED
}
}UNTIL all edges has been used
Remove current node from Visited node list.
RETURN Status = ERROR
Table 1. Simple Pseudo-Code Algorithm for formulating loop equations.

Table 1 presents a simple algorithm for setting up the loop equations. It is used with following call-up
parameters:

Get_Voltage_Loop(Start Node, Visisted node list, Start Node)

This algorithm walks beginning with the start-node through the network and quits if the loop equation has been
found properly with Status = FINISHED or if no loop equation can be found with status = ERROR.
In the beginning the program adds the current node and the edge used to come to the current node to a list which
is called “Visited node list”. This list contains all the nodes which have been visited by the loop tracer. The next
line give the FINISHED criterion, if the current node is the start node and if there are more then one entry in the
“Visited node list”. As otherwise the program would finish with its first cycle, as in the beginning the current
node is the start node. The next program-loop tries all edges En connected to the current node to get a new node
Nn, and calls itself recursively. If all possibilities had no success the program removes the current node from the
“Visited node list” and quits with status = ERROR.
 V1
1 2

V2 V3

V4
3 4

V6 V7

V5
5 6
Fig.12 Correct loop determination

Figure 12 shows how a possible loop can look like. Here the loop equation would be:

V1+V3+V7-V5-V6-V2=0 (2.8)

After one equation has been found successfully, normally many more must follow. The next problem which
must be discussed is how to continue to extract the loop equations. Or more specific: How can it be prevented to
get the same loop equation over and over again. How to get all linear independent equations, which are
necessary to solve the circuit-matrix. It is clear that some information about previous loop equation setups must
be stored somehow to prevent repeating the same equation. One way could be to mark nodes, after they were
visited. Then when looking for a new start node, a node must be selected, which hasn’t been visited yet, so one
can be sure that the equation would be linear independent. But what if there were no untouched nodes, but a new
loop equation must be found. This problem is also visible in Figure 12. All six nodes have been visited, but
another linear independent equation must be found. Another much more successful way is to give edges a
weight. That means: Every time if a voltage edge is used for a loop equation, its weight is increased by one. The
startnode will be the node connected to an edge with the lowest weight. The lowest possible weight is zero,
which means that the corresponding edge has not been used before, so it is a suitable candidate for starting. All
nodes must have a list of edges connected to it, which must be sorted by weight beginning with the edge with the
lowest weight. So one can be sure that the selection of the next node will be done over the voltage edge with the
lowest possible weight.

V1
1
1 2

V2 V3
1 1

V4 0
3 4

1
V6 V7
1
V5
5 6
1
Fig.13 Electrical network with edge weights.

Figure 13 shows the network from Figure 10 with voltage edge weights, which are from a previous loop setup, as
shown in Figure 12. Possible nodes for starting are node 3 and 4, as they have edges connected to them with zero
weight.
V1
1
1 2

V2 V3
1 1

V4 1
3 4

2
V6 V7
2
V5
5 6
2
Fig.14 A new loop setup with updated weights.
Figure 14 shows now the new loop equation which will be:

V4+V6+V5-V7=0 (2.9)

The algorithm from Table 1 must be updated to deal with weights and will be the following:

Get_Voltage_Loop(Current Node, Visisted node list, Start Node)

Add current node AND used Edge to Visited node list
Sort List of edges connect to current node beginning with lowest weight
IF Current Node = Start Node AND Visited node list has more than one entry
THEN RETURN with STATUS = FINISHED
DO{ get next edge (En) from current node
Nn = the node connected En
IF Nn is not in the visited node list AND node Nn has more than one
Edges connected to it AND Nn is not equal to the current node
THEN DO{
Increase weight of current selected edge by one
Status = Get_Voltage_Loop(Nn, Visisted node list, Start Node)
IF Status = FINISHED THEN RETURN FINISHED
ELSE DECREASE weight of current selected edge by one
Get next edge in list
}
}UNTIL all edges has been used
Remove current node from Visited node list.
RETURN Status = ERROR
Table 2. Simple Pseudo-Code Algorithm for formulating loop equations using edge weights.

The modification of the weight algorithm compared to the algorithm from Table 1 has been marked with italic
characters. This algorithm and the proper selection of a startnode as discussed above, will result in as many
linear independent voltage loop equations as possible. As it could be observed, it is much easier to setup node
equations, than loop equations. That for it is recommended to find as many node equations as possible and to fill
the rest of the matrix with loop equations. This will significantly reduce the total time consumption, as time
intense recursive program-calls will be minimized. The next step will be a matrix optimization for fast circuit
tuning possibilities. The circuit matrix equation was:



 D    I0 
  ⋅ I = 

  (2.9)
Z   V0 

Because the equation system is linear, all the current- and voltage-terms do only exist in their first order, which
means that no squared or higher order products exist. If we take the simple equation:

I1Z1 + I 2 Z 2 − I1Z 3 + V01 − V02 = 0 (2.10)

where In are component currents and U0n are voltage sources, the corresponding row in the Z submatrix would
be:

[(Z1-Z3) Z2] (2.11)

and the row in the V0 vector would be:

[(V02-V01)] (2.12)

This shows that the elements in the submatrices D and Z as well as the source vectors V0 and I0 consist of sums
of impedances, voltage sources, etc. If these sums are calculated numerically, the resulting values will give no
insight which component value a.e. impedance has influenced it. So it is much more valuable if each element
preserves its original symbolical constellation. In the case of equation (2.11) one matrix element would be Z1-Z3
instead of its numerical result. Only if the equation system is being solved, the matrix elements are numerically
evaluated. A way to store such matrix elements is a list. So every matrix element is not a number, it is a list of a
special structure. A structure element could look like:

Name Type
Next Pointer to structure
Value Pointer to number
Sign +1 or -1
Table 3. Simple matrix list element.

The variable Next in the structure stores the address of the next structure element in the chained structure list.
The variable Value is a pointer to a number a.e. to the value of Z3. The variable named Sign gives the sign for
the variable Value during summing up the list. To evaluate the list following procedure could be repeated until
the end of the list has reached:

Sum = 0
REPEAT UNTIL List ends:
Sum = Sum + Sign * value(Value)
Table 4. Simple summing algorithm.

The program in Table 4 simply evaluates the Sum of a matrix element structure list. The function value() extracts
the “real” value on which the variable Value points. The variable Sum will contain the total sum of all structure
elements and can be placed into a matrix or vector containing “real” complex number for matrix solution. This
detour will give following very important benefit:
As all the matrix and vector elements are lists of structures, the original contributors to the elements can simply
change their values and the matrix can be solved again using the sum-algorithm of Table 4 for every matrix and
vector element, and then using these results for a matrix solving technique like the chained Gauss algorithm.
Without this technique, the node and loop equations would have to be found always again, when one circuit
element changes. With the matrix list method using chained structures like in Table 3, just the sums must be
calculated again, and the matrix is ready for resolving. This will save a lot of processor-time, especially in AC-
frequency sweeps, where the whole circuit equations had to be setup on every frequency point.

III. Linear controlled sources

Up to now sources had been assumed to be constant. In many application like semiconductors equivalent
linearized models linear controlled voltage- and current-sources are required. The following types should be
implemented:

a) Current controlled current source.

b) Current controlled voltage source.
c) Voltage controlled current source.
d) Voltage controlled voltage source.

Each of these sources should be of the form:

0 n , I 0 n + ∑ Vi , I i ⋅ Ci (3.1)
V0 n , I 0 n = V 
i

which means that each controlled source consists of a constant term V  and a sum of with constants Ci
0n , I 0n
factorized device currents or voltages.

1 1
I 01 = 10mA + I1 + I 2 (3.2)
2 8
Equation (3.2) shows an example where a current controlled current source has a constant term of 10 mA and is
also dependent on I1 and I2, where the constants C1 = ½ and C2 = 1/8. To implement linear controlled sources,
another closer look to circuit equations must be done. If we have a look at the node current equations, we saw
that the first rule of Kirchhoff can be applied.
 If we look back to equation (1.8) we saw that:

∑I
n
n = −∑ I 0 m (3.3)
m

The total current sum must be zero. Equation (3.3) can be shown as a row of the matrix and source vector of the
circuit equation:



 D    I0 
  ⋅ I = 

  (3.4)
Z   V0 


( Dn1 Dn 2 ... Dnm ) I = I n 0 (3.5)

Equation (3.5) represents the nth row of the node current equations in equ. (3.4). The vector elements Dni give the
current direction, and the vector I consists of the device currents I1 to Im. The scalar value In0 is the sum of all
current sources connected to the investigated node. For example the current equation:

I1 − I 2 + I 3 − I 01 = 0 (3.6)

will give following representation:


(1 −1 1) I = I 01 (3.7)

The controlled sources equation of (3.1) can be also expressed in matrix form as:

 
I n 0 = I nconst + C n I (3.8)

If equation (3.8) is used in equation (3.5) this will give:


 
(D n )
− C n I = I nconst (3.9)

The same can be done for current controlled voltage sources, an the total current controlled circuit equation will
be:


  D   Ci     I 
 −    ⋅ I = 

0  (3.10)
  Z   Cv    V0 
  

Where the submatrix Ci denotes current controlled current sources and the submatrix Cv current controlled
voltage sources. If more than one controlled source is connected to a node, all the coefficients and constants
from equation (3.1) need to be simply added, which means that every element in the submatrices Ci and Cv are
the sum of all the controlled sources at one node or in one loop. However, voltage controlled sources can not be
implemented directly. A high impedance resistor has to be added to the network, which will not influence circuit
behaviour. The current through this resistor multiplied with the resistors value will give the required voltage. To
high values of this resistors will give an ill conditioned circuit matrix, and so solving problems, a to low value
will influence the circuit behaviour, and “short-circuit” the voltage-graph.
 V3 V01
R3 1
2 I3

I1 I2
I5

1
V1 R1 R2 V2
V
R

0
V4
R4
I4

4 V02=(1+3*V) =(1+3*R*I5) 3

Fig.15 A circuit with voltage controlled voltage source.

Figure 15 shows now an example circuit using a resistor for voltage sensing. The voltage-source V02 is
controlled by the voltage between node 1 and node 4, where a resistor R has been put in between. The voltage
drop across R will give the current I5 which is multiplied by R the control voltage. This shows clearly that all
controlled sources are in fact current controlled, but can be transformed by additional resistors to voltage
controlled sources.

IV. Nonlinear elements

Nonlinear elements offer a new problem to the solution of electrical networks. As their V/I-behavior is non-
linear, the circuit can not be solved by linear methods, furthermore the solution can only be numerically
evaluated. First of all, the definition of a nonlinear element should be defined. Every element in a circuit can be
expressed by a controlled current- or voltage-source. In the case of the nonlinear elements, the control function
becomes nonlinear.

V2 = f ( I1, I 2 , V1 ) (4.1)

Equation (4.1) gives an example for a multiple controlled voltage source. The input parameters are two currents
and one voltage. Now it is from great advantage to find a solution algorithm, to solve a network consisting of
multiport devices defined by Z-parameters with nonlinear elements connect to them, using a representation like
in equation (4.1). As it is clear, that the nonlinear function can be of any complexity, only a numerical solution
algorithm is applicable. The network matrix equation changes to:














  D   Ci     I 0 + FI ( I1....I n ) 
 −    ⋅ I = 













  (4.2)
  Z   Cv    V + F ( I ....I ) 
    0 V 1 n 

with:

 ∑ f j ( I1....I n ) 
 












  j  (4.3)
FI ( I1....I n ) =  .... 
 ∑ f k ( I1....I n ) 
 k 
 
and
  ∑ f l ( I1....I n ) 












  l 
FV ( I1....I n ) =  ....  (4.4)
 
 ∑ f m ( I1....I n ) 
 m 

























where FV ( I1....I n ) and FI ( I1....I n ) represent the vectors containing the nonlinear functions of the
corresponding elements. As there can be more than one nonlinear element in one voltage loop or connected to
one node, the sum of all nonlinear functions must be calculated for one vector element. There can be also no real
voltage control of nonlinear elements like with the linear controlled sources, because the matrix is defined
through currents. Voltage control can be simulated by placing a high impedance resistor between the desired
nodes and using the current through the resistor as a replacement for the node-to-node voltage. If right term in
equation (4.2) is moved to the left, it will become to:














  Ci   D     I   FI ( I1....I n ) 
  −  ⋅ I + 

0  + 











  = 0 (4.5)
  Cv   Z    V0   FV ( I1....I n ) 
  
The equation (4.5) can now be used with the Newton method to locate zeros. The Newton method is iterative and
normally converges very quickly to the zero, but can however fail to converge by following reasons:

a) A inflection point of the function is near the zero.

b) The function has multiple zeros which are located very or infinite near.
c) The algorithm is started in a region of a local minimum.

All these possibilities of failure must be taken into account and eliminated. Many solutions to these problems has
been reported in [3], and should not be a topic of this paper. The one-dimensional Newton method is defined at
the iteration step k as:

x ( k +1)
=x (k )
−
( ) (4.6)
f x( k )
f ( x( ) )
' k

As it can be seen in equation (3.16) , Newton’s method uses the derivation of the function f, which allows the
algorithm to find it’s way to the zero very quick. Now this algorithm can be extended to multidimensional zero
determination:






 −1












x ( k +1)  (k ) 
( ) ( )
= x − J  f x  f x ( k ) (4.7)
(k )
 

Equation (4.7) shows now the multidimensional Newton iteration. The derivation of the function which is a
vector now, results in the Jacobian matrix, which contains all derivation of all vector elements with respect to all
input ( x(k) ) vector elements. The jacobian has a form like:

 df1 df1 df1 

 dx ...
dxn −1 dxn 
 1 
 ... ... ... ... 
 
 df m −1 ... ...
df m −1  (4.8)
 dx1 dxn 
 
 df m ...
df m df m 
 dx dxn −1 dxn 
 1
As the division through a matrix is not defined the division changes into a matrix inversion which is denoted
through the operator (-1). If equation (4.7) is now applied to equation (4.5) the result will be:

 −1


















   FI ( I1....I n )   Ci   D      Ci   D  


  I   FI ( I1....I n )  
I ( k +1) = I ( k ) −  J 











  +   −    x     −    ⋅ I ( k ) + 

0  + 











   (4.9)
   C  Z  C  Z   V0   FV ( I1....I n )  
  FV ( I1....I n )   v        v    

To proof the equivalence to the linear solution will be now to set the nonlinear elements to zero.

−1










   Ci   D      Ci   D  


  I  
I ( k +1)
= I −  0 +   −    x     −    ⋅ I + 

0  + 0  (4.10)
(k ) (k )
 C  Z  C  Z   V0  
  v     v   

If we set now the starting current vector I(0) of the iteration to zero (4.10) becomes:

−1





   Ci   D     I  
I = −    −    x  

0   (4.11)
(1)
  Cv   Z     V0  
    

which is definitely the solution to equation (4.1). This shows that the iteration solves the network equation in one
step, if there are no nonlinear elements in the circuit. The next question is now, when to end the iteration.
For this purpose equation (4.5) can be used as:



















  Ci   D  


  I   FI ( I ( k )1....I ( k ) n ) 




   −    ⋅ I ( k ) + 

0  + 

















 = E (4.12)
  Cv   Z    V0   FV ( I ( k )1....I ( k ) n ) 
    

If the current calculated in the iteration step (k) is inserted in equation (4.5) the equation will not be true, which
means that the sum on the left side will not be zero. The total sum will be called error vector denoted with E in
equation (4.12). One can end the iteration if the length of the error vector is beyond a certain limit, or a lower
limit for each element of the error vector is reached. Also combinations of these methods are applicable.

This nonlinear solution method, presented above, can only be used for the DC solution. For AC solution of the
currents, all the harmonic of each source and nonlinear element must also be taken into account. The method
using all the harmonics is then called harmonic balance simulation []. Now for this quasi-linear approach, at first
the DC-solution of the circuit will be calculated, and once the bias point is known, the values for the small-signal
AC models can be calculated. The AC- small signal model is derived from the DC I/V characteristics of the
nonlinear element by calculating the first taylor-series element at the given bias-point. Now a simple circuit
should illustrate the nonlinear circuit solver:

R1
V1

I1
V01 I2
I3
D1 V2 R2
DIODE

Fig.15 Simple nonlinear circuit.

The current through the diode is defined through the simple equation as:

 kT
V2 e

I 3 = I s  e η − 1 (4.13)
 
 

For explanation of the diode parameters [] will give some interesting ideas.

The equation (4.5) will transform to:














  Ci   D     I   FI ( I1....I n ) 
   −    ⋅ I + 

0  + 











  = 0 (4.5)
  Cv   Z    V0   FV ( I1....I n ) 
  

  IkT
2 R2 e

 0  1 −1     0   I s  e η − 1  
  −  ⋅ I +   +   
  = 0 (4.14)
  0   R1 R2    −V01   
 0 

And the Newton iteration from (4.9) will transform to:

( k +1) (k )  I Re
2 2
I s R2 kT   (k )
  IkT 2 R2 e
η

 I1  I  0 e η  1 −1     1 −1    I1   0   I s e − 1  (4.15)
  = 1 −  kTη −R  −  ⋅  +  +   

 I2   I2    1 R2     R1 R2    I 2   −V01   
0 
 0    0 

The small signal AC equivalent impedance of the diode will be then:

kT
dV3
η
Z3 = = e (4.16)
dI 3 I 3( DC ) + I s

And as I3 can be calculated out of equ.(4.15) the value of Z3 can be calculated then easily out of equation (4.16).
With the results out of the Newton iteration, all necessary DC bias points can be calculated to define the values
of the small signal models of the AC analysis (also the nonlinear capacitors can be linearized).
V. Application
The here addressed application of the circuit simulator should be the complex deembedding of parts of a circuit,
which S-Parameters should be determined by a vector network-analyzer. Before the problem is defined in more
detail, the method to determine the S-parameters through the circuit simulator should be enlightened. As S-
Parameters are defined rather by terms of waves than voltages and currents, the S-parameters can not be directly
calculated by the circuit simulator. However a simple setup will be used to determine all the needed parameters.

50 I1 1 2 I2 50

V1
Z V2 V02
V01

0 I0
Fig.16 Setup to determine S-parameters.

The measurement will be performed in two steps.

1) V01 will be set to any voltages beside zero, and V02 to zero volts. Out of that I1 ,V1 and V2 will be
calculated. Out of these values the necessary wave a1 , b1 and b2 can be calculated, as out of the
definition of the S-parameters:

1 V  1  V1 
a1 =  1 + I1 Z 0  and b1 =  − I1 Z 0  (5.1)
2  Z 0 
 2  Z 0 


1 V 
aswell as: b2 =  2 − I 2 Z 0  (5.2)
2  Z 0 


As in the first case V2 = − I 2 Z o , (5.2) simplifies to

b2 = − I 2 Z o (5.3)
and with the relation: V1 = V01 − I1Z c reduces (5.1) to:

V01 1  V01 
a1 = and b1 =  − 2 I1 Z 0  (5.4)
2 Z0 2  Z 0 

As the two-port S-Parameter are defined by:

 b1   S11 S12  a1 
 =   (5.5)
 b2   S21 S22  a2 

following parameters can be determined:

b1 V01 − 2 I1Z 0
S11 = = (5.6)
a1 V01

and

b2 −2 I 2 Z 0
S 21 = = (5.7)
a1 V01
 2) 2) V01 will be set to zero, and V01 to any voltage different from 0volts. Out of that I2 ,V2 and V1 will be
calculated. From these values the necessary wave a2 , b2 and b1 can be calculated, and with the
definition of 1) this will give:

b2 V02 − 2 I 2 Z 0
S 22 = = (5.8)
a2 V02

and

b1 −2 I1Z 0
S12 = = (5.9)
a2 V02

Now as all four S-parameters can be calculated out of two simulation-runs, the problem of deembedding can be
defined:
S
d

S
2
S
1

a1 b2

b1
a2

Fig.17 Definition of the deembedding problem.

When measuring certain circuits with a vector network analyzer, the point of calibration cannot be placed at the
desired points where the to measured circuit is positioned. So in the most cases connectors and transmission lines
as well as passive discrete components may lie between the calibrated point and the to be measured component.
The deembedding problem is also illustrated in Figure 17, where the desired component has the S-Parameters Sd
and lies between the networks S1 and S2, which represents all the connectors and components between the
calibration point and the component Sd. The idea of deembedding is now to synthesize the S-parameters of the
networks S1 and S2 and “subtract” them from the measured result to obtain the pure S-parameters of the network
Sd. So it is obvious that the modelling of the networks S1 and S2 must be very accurate to get good results for
the network Sd. So, all parasitics can be included into the networks, which could form a quite large circuit.
A possible application would be to measure a packaged transistors S-parameter, and deembedd all the
transmissionlines and package parasitics to obtain the pure die characteristics. Another application would be, if
the die characteristics are known, to calculate the parasitics.

The deembedding itself is very simple, when the transmission parameters instead of the S-parameters are used
for describing the networks. The S-Parameters can be transformed to the transmission parameter by following
equations:

The S-Parameter are defined by:

 b1   S11 S12  a1 
 =   (5.10)
 b2   S21 S22  a2 

and the transmission parameters as

 b1   T11 T12  a2 
 =   (5.11)
 a1   T21 T22  b2 
The identities are:

 S12 − S11S21−1S22 S11S21−1   T12T22 −1 T11 − T12T22 −1T21 

T = −1  and S =  (5.12)
 − S21 S22 S21−1   T22
−1
−T22 −1T21 
The great advantage of the transmission-parameters is that the total T-matrix of chained two-ports is simply the
ordered matrix multiplication of the single two ports. In the case of Figure 17 this would be:

Ttotal = T 1 ⋅ T s ⋅ T 2 (5.13)

The operators:

T = FS →T ( S ) and S = FT → S (T ) (5.14)

will be a shortcut for the transformation of equation (5.12)

The total S-Matrix of Figure 17 can now be formulated as:

( ( ) ( )
S total = FT →S FS →T S1 FS →T Sd FS →T S2 ( ) ) (5.15)
Now to deembedd the matrix Sd out of Stotal the matrices S1 and S2 will be synthesized through the procedure
(5.6) to (5.9) and then following deembedding equation will be applied:

(
Sd = FT → S FS →T ( S1 ) FS →T ( Stotal ) FS →T ( S2 )
−1 −1
) (5.16)
which will calculate the real S-parameters of the intrinsic desired circuit. The equation (5.16) denotes the actual
deembeding procedure.

VI. References
[1] Zinke, O.; Brunswig H.: Hochfrequenztechnik 1,
Springer Verlag, Heidelberg 1995

[2] R.W. Hamming: Numerical Methods for Scientists and Engineers,

Dover publications, Inc., New York 1973

[3] Stephen A. Maas : Nonlinear Microwave and RF Circuits,

Artech House, Norwood MA 2003

[4] G. Massobrio.; P. Antognetti: Semiconductor Device Modeling with SPICE,

McGraw Hill, 1993

[5] Kupfmüller; Kohn: Theoretische Elektrotechnik und Elektronik,

Springer Verlag,Heidelberg 1993

[6] T.S.Blyth, E.F.Robertson: Basic Linear Algebra,

Springer Verlag, London 2002

[7] H.Freitag: Einführung in die Zweitortheorie,

Teubner Studienskripten, Stuttgart 1990