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Direct Memory Access - GeeksforGeeks

Direct Memory Access (DMA) allows peripherals to communicate directly with main memory, bypassing the CPU to enhance data transfer speed and overall system performance. The DMA controller manages data transfers through various components, including control logic, registers, and buses, and can operate in different modes such as burst, cycle stealing, block, and demand mode. This technique improves efficiency by enabling simultaneous operations between the CPU and peripherals.

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120 views4 pages

Direct Memory Access - GeeksforGeeks

Direct Memory Access (DMA) allows peripherals to communicate directly with main memory, bypassing the CPU to enhance data transfer speed and overall system performance. The DMA controller manages data transfers through various components, including control logic, registers, and buses, and can operate in different modes such as burst, cycle stealing, block, and demand mode. This technique improves efficiency by enabling simultaneous operations between the CPU and peripherals.

Uploaded by

leviak218
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Direct Memory Access

Last Updated : 20 Jan, 2025

Direct Memory Access (DMA) is a technique used in computers and


other electronic devices to allow peripherals (like hard drives, network
cards, and sound cards) to communicate directly with the main memory
(RAM) without involving the CPU. This process speeds up data transfer
and frees up the CPU to perform other tasks, improving overall system
performance.

The peripheral device sends a request to the DMA controller to


initiate a data transfer.
The DMA controller takes control of the system’s memory bus and
accesses memory directly, either reading data from it or writing data
to it.
After the transfer is complete, the DMA controller signals the CPU
that the task is finished, and the CPU can continue with other tasks.

Working of DMA Transfer


Below diagram represents a Direct Memory Access (DMA) controller
and its components in a typical DMA system.

Open In App
Working of DMA System

DMA Controller Components

1. Control Logic: The Control Logic is the central component that


manages the overall DMA operation. It processes control signals and
directs data transfers between the peripherals and memory. It
receives commands from other components and determines how
and when data should be moved.
2. DMA Select and DMA Request: DMA Select is used by the DMA
controller to select the appropriate data transfer request. DMA
Request is initiated by a peripheral device when it needs to perform a
data transfer. The request tells the DMA controller that the device is
ready to either read or write data.
3. DMA Acknowledge: The DMA Acknowledge signal is sent back from
the control logic to the peripheral device to confirm that the DMA
operation has been initiated and the device can proceed with the data
transfer.
4. Bus Request and Bus Grant: Bus Request is generated by the DMA
controller when it needs access to the system's bus for data transfer.
The Bus Grant signal is sent from the CPU or the system’s bus
controller to give the DMA controller permission to use the bus for
transferring data.
5. Address Bus and Data Bus: The Address Bus and Data Bus are used
to transfer data and memory addresses between the DMA controller,
memory, and peripherals. The Data Bus Buffer temporarily holds data
Aptitudebeing transferred,
Engineering while
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Discrete Bus Buffer
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addresses.
6. Registers:
Address Register: This stores the memory address where data will
be written or read from.
Word Count Register: This keeps track of the number of words or
units of data that need to be transferred.
Control Register: This contains control information, including the
direction of data transfer (read or write), and any other control
Open In App
signals necessary to manage the DMA operation.
7. Internal Bus: The Internal Bus connects all the components inside the
DMA controller, allowing them to communicate and pass data
efficiently.
8. Interrupt: The Interrupt signal is used to inform the CPU once the
DMA operation is completed. After the data has been transferred, the
DMA controller sends an interrupt to notify the CPU, so the CPU can
resume processing or handle other tasks.

Working:

The DMA controller facilitates the transfer of data between memory


and peripherals without involving the CPU for each individual data
operation, as mentioned in the article.

The DMA Select and DMA Request initiate the process when a
peripheral wants to transfer data, similar to how DMA allows
peripherals to operate independently of the CPU.

Address Bus and Data Bus handle the flow of data and memory
addresses during the transfer, improving system efficiency by
bypassing the CPU.

The Registers (Address Register, Word Count Register, Control


Register) store the necessary information to control the transfer, as
described in the article, where DMA controls the movement of data
between the device and memory.

The Interrupt is triggered once the transfer is completed, similar to


how the CPU is notified in the article that DMA operations have been
finished.

Types of DMA
There are several types of DMA, each with its own way of transferring
data:
Open In App
1. Burst Mode DMA:
In this mode, the DMA controller takes control of the memory bus
and transfers a block of data in one go.
The CPU is temporarily locked out of memory access while the
DMA controller completes the data transfer.
2. Cycle Stealing DMA:
In this mode, the DMA controller transfers one data item at a time
but allows the CPU to access memory between each transfer.
This allows the CPU and DMA controller to share the memory bus
and work more collaboratively.

3. Block Mode DMA:


The DMA controller transfers a block of data without interruption,
but it uses a more organized approach than burst mode, allowing
for more efficient transfers.
The CPU is locked out of memory access during the transfer.

4. Demand Mode DMA:


In this mode, the DMA controller transfers data only when the CPU
is not using the memory bus, essentially waiting for an idle time to
perform the transfer.

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