Unit-IV

Interfacing (Data Transfer) with Microprocessor: Data Transfer

Schemes: Introduction, handshaking signals, Types of transmission,
8255 (PPI), Serial Data transfer (USART 8251), memory interfacing,
8257 (DMA), programmable interrupt Controller (8259).

Data transfer schemes:

 In microprocessor-based systems, digital information can be
transmitted from one system to another system either by parallel or
serial data transfer scheme.

 In parallel data transfer, a group of bits (for eg., 8 bits) are transmitted
from one device to another at any one time

 When data has to be transmitted over longer distances (i.e., greater

than 0.5 m), we require high current signals to drive the data for
longer distance. In such cases data are transmitted bit by bit through
a single data line(serial data transfer).

Parallel Data Transfer Schemes:

 It is a method of data transfer between the processor and peripheral

devices.
 In typical microcomputer data transfer takes place between any two
devices: microprocessor and memory, microprocessor and IO
devices, memory and IO devices
 For effective data transfer between these devices, the timing
parameters of the devices should be matched. But most of the
devices have incompatible timings. For example, an IO device may
be slower than the processor due to which it cannot send data to the
processor at the expected time
  The semiconductor memories are available with compatible timings.
Moreover, slow memories can be interfaced using additional
hardware to introduce wait states in machine cycles

The data transfer schemes have been broadly classified into the following
two categories :
1. Programmed data transfer.
2. Direct Memory Access (DMA) data transfer.

Programmed data transfer.

 In programmed data transfer, a memory resident routine (subroutine)
requests the device for data transfer to or from one of the processor
register.

 Programmed data transfer scheme is used when relatively small

amount of data are to be transferred. In these schemes, usually one-
byte or word of data is transferred at a time. Examples of devices
using programmed data transfer are ADC, DAC, Hex-keyboard, 7-
segment LEDs, etc.

 The programmed data transfer scheme can be further classified into the following
three types:
1. Synchronous data transfer scheme.
2. Asynchronous data transfer scheme.
3. Interrupt driven data transfer scheme.

Direct Memory Access (DMA) data transfer:

 In DMA data transfer, the processor is forced to HOLD state (high

impedance state) by an IO device until the data transfer between the
device and the memory is complete. The processor does not execute
any instructions during the HOLD period.

 The DMA data transfer is used for a large block of data transfer
between the IO(input-output) device and memory. Typical examples
of devices using DMA are CRT controller, floppy disk, hard disk, high
speed line printer, etc.
The DMA data transfer schemes are :
a) Cycle stealing DMA or Single transfer mode DMA.
b) Block or Burst mode DMA.
c) Demand transfer mode DMA.

Figure given below shows the various types of data transfer scheme. All
the data transfer schemes discussed above require both software and
hardware for their implementation

Synchronous Data Transfer Scheme

 It is the simplest of all data transfer schemes.
 In this scheme, the processor does not check the readiness of the
device.
 The IO device or peripheral should have matched timing parameters.
Whenever data is to be obtained from the device or transferred to the
device, the user program can issue a suitable instruction for the
device. At the end of the execution of this instruction, the transfer
would have been completed.

 The sequence of operations for synchronous data transfer scheme is

shown in Fig.(a). The mode-0 input/output in 8255 is an example of
synchronous data transfer
 Fig. (a) Synchronous data transfer scheme
Asynchronous Data Transfer Scheme
 The asynchronous data transfer scheme is used when the speed of
the processor and IO device do not match.

 In this scheme, the processor sends a request to the device for read/
write operation. Then the processor keeps on polling the status of the
device. Once the device is ready, the processor executes a data
transfer instruction to complete the process.

 To implement this scheme, the device should provide a signal which

may be tested by the processor to ascertain whether it is ready or
not.

 The sequence of operations for asynchronous data transfer is shown

in Fig. (b). The mode-1 and mode-2 handshake data transfer of 8255
without interrupt is an example of asynchronous data transfer.
 Fig.(b) Asynchronous data transfer scheme

Interrupt Driven Data Transfer Scheme

 It is the best method of data transfer for efficient utilization of
processor time.
 In this scheme, the processor first initiates the IO device for data
transfer. After initiating the device, the processor will continue the
execution of instructions in the program.
 Also at the end of every instruction the processor will check for a valid
interrupt signal. If there is no interrupt then the processor will continue
the execution

Fig.(a) Main program Fig.(b) ISS execution sequence

execution sequence
 When the IO device is ready, it will interrupt the processor. On receiving an
interrupt signal the processor will complete the current instruction execution and
save the processor status in stack.

 Then the processor call an Interrupt Service Subroutine (ISS) to service the
interrupting device.

 At the end of ISS, the processor status is retrieved from stack and the processor
starts executing its main program. The sequence of operations for an interrupt
driven data transfer scheme is shown in above Fig.(a) and (b).
Programmable Peripheral Inter face - INTEL 8255:

The INTEL 8255 is a device used to implement parallel data transfer

between processor and slow peripheral devices like ADC, DAC, keyboard,
7-segment display, LCD, etc.

 The 8255 has three ports: Port-A, Port-B and Port-C. The ports A and
B are 8-bit parallel ports.
 Port-A can be programmed to work in any one of the three operating
modes as input or output port. The three operating modes are :

 Mode-0 → Simple IO port.

 Mode-1 → Handshake IO port.
 Mode-2 → Bidirectional IO port.

 Port-B can be programmed to work either in mode-0 or mode-1

as input or output port.
 Port-C pins (8 pins) have different assignments depending on
the mode of ports-A and B. If ports-A and B are programmed in
mode-0, then port-C can perform any one of the following
functions :

i. As 8-bit parallel port in mode-0 for input or output.

ii. As two numbers of 4-bit parallel port in mode-0 for input or
output.
iii. The individual pins of port-C can be set or reset for various
control applications.

 If port-A is programmed in mode-1/mode-2 and port-2 is programmed

in mode-1 then some of the pins of port-C are used for handshake
signals and the remaining pins can be used as input/ output lines or
individually set/reset for control applications.

IO Modes of 8255

Mode-0 : In this mode all the three ports(A,B and C) can be programmed either
as input or output port.
  In mode-0, the outputs are latched and the inputs are not latched. The
ports do not have handshake or interrupt capability.
 The ports in mode-0 can be used to interface DIP switches, Hexa-keypad,
LEDs and 7-segment LEDs to the processor.

Mode-1 : In this mode, only ports A and B can be programmed either as input or
output port.
 In mode-1, handshake signals are exchanged between the processor and
peripherals prior to data transfer.
 The port-C pins are used for handshake signals. Input and output data are
latched. Interrupt driven data transfer scheme is possible.

Mode-2 : In this mode the port will be a bidirectional port (i.e., the processor can
perform both read and write operations with an IO device connected to a
port in mode-2).
 Only port-A can be programmed to work in mode-2. Five pins of port-C are
used for handshake signals.
 This mode is used primarily in applications such as data transfer between
two computers or floppy disk controller interface.
Pins, Signals and Internal Block Diagram of 8255
Pins, Signals and Internal Block Diagram of 8255
 The pin description of 8255 is shown in fig(a) given below.
 It has 40 pins and requires a single +5-V supply.
 The internal block diagram of 8255 is shown in Fig.(b)
Fig.(a) The pin description of 8255

Fig.(b) Internal block diagram of 8255

 The ports are grouped as Group A and Group B. The group A has
port-A, port-C upper and its control circuit.

 The group B comprises port-B, port-C lower and its control circuit.

 The read/ write control logic requires six control signals. These
signals are given below:

𝑹𝑫 (Read): This control signal enables the read operation. When this signal
is low, the microprocessor reads data from a selected IO port of the 8255A.

𝑾𝑹 (Write): This control signal enables the write operation. When this signal
goes low, the microprocessor writes into a selected IO port or the control
register.

RESET: This is an active high signal. It clears the control register and set all
ports in the input mode.
𝑪𝑺 , A0 and A1: These are device select signals. The address lines A0 and A1
of 8255 can be connected to any two address lines of the processor to provide
internal addresses.
 A0 and A1 selects any one of the 4 internal devices as shown in Table-
 The 8255 will remain in high impedance state if the signal input to 𝑪𝑺 is
high and the device can be brought to normal logic by making the signal
input to CS as logic low.

Chip Select logic and Port Addresses of 8255:

Fig. Chip select logic and I/O port Addresses

Control word: The figure (a) shows a register called the control register.
 The contents of this register , called the control word.
 It specify an I/O function for each port.
 This register can be accessed to write a control word when A0 and A1
are at logic 1.

 Bit D7 of the control register specifies either I/O function or the Bit
Set/Reset function.
 If bit D7=1, bits D6-D0 determine I/O functions in different modes of
8255.

To communicate with peripherals through the 8255A, three steps are

required
i. Determine the addresses of ports A,B and C and of the control register
according to the Chip select logic and address lines A0 and A1.

ii. Write a control word in control register

iii. Write I/O instructions to communicate with peripherals through ports

A, B and C.

Figure (a)
Fig.(b) 8255 Ports and their modes

Fig. Format of I/O mode set control word for 8255

Mode-0 : In this mode all the three ports(A,B and C) can be programmed either
as input or output port.
 the outputs are latched and the inputs are not latched. The ports do not
have handshake or interrupt capability.
 The ports in mode-0 can be used to interface DIP switches, Hexa-keypad,
LEDs and 7-segment LEDs to the processor.

Problem Statement:
1. Identify the port addresses in fig. given below
2. Identify the Mode-0 control word to configure port A and port CU as output
port and port B and port CL as input port
3. Write a program to read the DIP switches and display the reading from port
B at port A and from port CL at port CU

Solution: Port Addresses: This is a memory mapped I/O; when the address
line A15 is high, the chip select line is enabled. Assuming all don’t care lines
are at logic 0, the port addresses are as follows
Port A = 8000H(A1=0, A0=0)
Port B = 8001H(A1=0, A0=1)
Port C = 8002H(A1=1, A0=0)
Control Register = 8003H (A1=1, A0=1)

BSR(Bit Set/Rest) mode:

BSR control word: This control word, when written in control register,
sets or resets one bit at a time, as given below

Problem: Write a BSR control word subroutine to set bits PC7 and PC3 and
reset them after 10ms. Assume that a delay subroutine is available.

Solution:

Port Address:
Control register address=83H
Mode-1 :.Input or Output with Handshake
 In mode-1, handshake signals are exchanged between the
processor and peripherals prior to data transfer.

 In this mode, only ports A and B can be programmed either as

input or output port

 The port-C pins are used for handshake signals. Input and
output data are latched. Interrupt driven data transfer scheme is
possible
 Input and output data are latched

MODE-1: INPUT CONTROL SIGNALS

 Figure shows the associated control signals used for

handshaking when ports A and B are configures as input ports.
 Port A uses the upper three signals: PC3, PC4 and PC5.
 Port B uses the upper three signals: PC2, PC1 and PC0.
The function of these signals are as given below

Control and Status word:

The figure (b) uses control word to setup port A and port B as input ports in
Mode 1.
The figure (c) shows the status word , which will be placed in the accumulator
if port C is read. control word to setup port A and port B as input ports in Mode
1.

USART (Universal Synchronous Asynchronous Receiver Transmitter)

- INTEL 8251A

 The 8251A is a programmable serial communication interface chip

designed for synchronous and asynchronous serial data
communication.
 It is a 28-pin DIP.
 The 8251A is the enhanced version of its predecessor, 8251 and it is
compatible with 8251. The pin description of
8251A is shown in Fig. 7.29.
Read/Write Control Logic

 The Read/Write control logic interfaces the 8251A with CPU,

determines the functions of the 8251A according to the control word
written into its control register and monitors the data flow. This
section has three registers and they are control register, status
register and data buffer.

 The signals 𝑅𝐷, 𝑊𝑅, C/𝐷 and 𝐶𝑆 are used for read/write operations
with these registers. When C/D is high, the control register is selected
for writing control word or reading status word. When C/D is low, the
data buffer is selected for read/write operation.

 A high on the reset input forces 8251A into the idle mode. The clock
input is necessary for 8251A for communication with CPU and this
clock does not control either the serial transmission or the reception
rate

Transmitter Section
 The transmitter section accepts parallel data from CPU and converts
them into serial data. The transmitter section is double buffered, i.e.,
it has a buffer register to hold an 8-bit parallel data and another
register called output register to convert the previous data into a
stream of serial bits.

 The processor loads a data into buffer register. When output register
is empty, the data is transferred from buffer to output register. Now
the processor can again load another data in buffer register. If buffer
register is empty, then TxRDY is asserted high and if output register
is empty then TxEMPTY is asserted high. These signals can also be
used as interrupt or status for data transmission.

 The clock signal, 𝑇𝑥𝐶 controls the rate at which the bits are
transmitted by the USART. The clock frequency can be 1.16 or 64
times the baud rate.

Receiver Section
 The receiver section accepts serial data and converts them into
parallel data. The receiver section is double buffered, i.e., it has
an input register to receive the serial data and convert it to
parallel, and a buffer register to hold the previous converted
data.

 Normally, RxD line is high, when the RxD line goes low, the
control logic assumes it as a START bit, waits for half a bit time
and samples the line again.

 If the line is still low, then the input register accepts the following
bits, forms a character and loads it into the buffer register. The
CPU reads the parallel data from the buffer register.

 When the input register loads a parallel data to the buffer

register, the RxRDY line goes high. This signal can be used as
an interrupt or status to indicate the readiness of the receiver
section to CPU.

 The clock signal RxC controls the rate at which bits are received
by the USART. In the asynchronous mode, the clock frequency
can be set to 1.16 or 64 times the baud rate.

 During the asynchronous mode, the signal SYNDET/BRKDET

will indicate the intentional break in the data transmission. If the
RxD line remains low for more than 2 character times then this
signal is asserted high to indicate the break in the transmission.

 During synchronous mode, the signal SYNDET/BRKDET will

indicate the reception of the synchronous character. If the 8251A
finds a synchronous character in the incoming string of data bits
then it asserts SYNDET signal as high.
 Fig: functional block diagram of 8251A

MODEM Control
The MODEM control unit allows to interface a MODEM to 8251A and
to establish data communication through MODEM over telephone
lines. This unit takes care of handshake signals for MODEM interface

Programming the 8251A

The 8251A is programmed by sending the mode word and command
word. First reset the 8251A and then send a mode word to control
register address. Next, the command word is sent to the same
address. The CPU can check the readiness of the 8251A for data
transfer by reading the status register.

The format of control and status words are shown in Fig. 7.31.
  The mode word informs 8251 about the baud rate, character
length, parity and stop bits. The command word can be sent to
enable the data transmission and/or reception. The information
regarding the readiness of transmitter/receiver and the
transmission errors can be obtained from the status word.

 If 8251A is programmed for a baud rate factor of 64x through

mode, word then the baud rate is clock frequency divided by 64.
If the baud rate factor is 16x, then the baud rate is clock
frequency divided by 16. If the baud rate factor is 1x, then the
baud rate is given by clock frequency.

Fig (a) Mode word Fig(b) Command word

Fig (c) Status Word

Fig. Format of 8251A mode, command and status words

Interfacing 8251A to 8086

 A simple schematic for interfacing the 8251A with 8086 processor

is shown in Fig. 7.32. The 8251A can be either memory-mapped or
IO-mapped in the system. In the schematic shown in Fig. 7.32, the
8251A is IO-mapped in the system, with even addresses.
 The chip select signals for IO-mapped devices are generated by
using a 3-to-8 decoder. The address lines A5, A6 and A7 are
decoded to generate eight chip select signals (IOCS-0 to IOCS-7)
and in this, the chip select signal IOCS-2 is used to select 8251A.
The address line A0 and the control signal M/IO are used as
enable for the decoder.
IO Addresses of 8251A:

The address line A1 of 8086 is connected to C/D of 8251A to provide the

internal addresses.
The IO addresses allotted to the internal devices of 8251A are as given in
above table The data lines D0-D7 are connected to D0-D7 of the
processor to achieve parallel data transfer. The RESET and
clock signals are supplied by 8284 clock generator. Here the
processor clock is directly connected to 8251A. This clock controls the
parallel data transfer between the processor and 8251A

The Peripheral Clock (PCLK) supplied by 8284, is divided by suitable

clock dividers and then used as clock for serial transmission and
reception (TxC and RxC). In 8251A, the transmission and reception
baud rates can be different or same. Usually a programmable timer,
8254 (which is discussed in Section 7.5) is used to divide the PCLK,
and supply to TxC and RxC at the required rate.

The TTL logic levels of the serial data lines (RxD and TxD) and the
control signals necessary for serial transmission and reception are
converted to RS232 logic levels using MAX232 and then terminated
on a standard 9 -pin D-type connector.

The device which requires serial communication with processor can

be connected to this 9-pin D-type connector using a 9-core cable. The
signals TxEMPTY, TxRDY and RxRDY can be used as interrupt
signals to initiate the interrupt driven data transfer scheme between
the processor and 8251A.