Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

Correction TD 2
VHDL : conception circuits numériques combinatoires

Avril 2025

1 Correction exercice 1 :
1.1 Buffer Unidirectionnel
1.1.1 Entité

Listing 1 – Entité

1 --Appel des bibliotheques

2 library IEEE;
3 use IEEE.std_logic_1164.all;

4 -- Definition Entite
5 entity Three_State_Unidir is
6 port ( E,Cde : in std_logic;
7 S : out std_logic);
8 end entity Three_State_Unidir;

1.1.2 Architecture 1

Listing 2 – Architecture 1

1 -- definition Architecture 1
2 architecture a1 of TriState_Unidir is
3 begin
4 S <= E when cde = '1' else 'Z';
5 end architecture a1;

1.1.3 Architecture 2

Correction TD 2 R.Hertelli : [email protected] 1/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

Listing 3 – Architecture 2

1 -- definition Architecture 2
2 architecture a2 of Thrree_State_Unidir is
3 begin
4 process (E,Cde)
5 begin
6 if (Cde = '1') then
7 S <= E ;
8 else
9 S<= 'Z';
10 end if ;
11 end process;
12 end architecture a2;

1.2 Buffer bidirectionnel

1.2.1 Entité

Listing 4 – Entité Buffer bidirectionnel

1 --Appel des bibliotheques

2 library IEEE;
3 use IEEE.std_logic_1164.all;

4 --Entite Definition
5 entity Three_State_bidir is
6 port ( E,Cde : in std_logic;
7 S : out std_logic;
8 IO : inout std_logic);
9 end entity Three_State_bidir;

1.2.2 Architecture

Listing 5 – Architecture Buffer bidirectionnel

1 -- definition Architecture Comportementale

2 architecture comport of Three_State_bidir is
3 begin
4 IO <= E when cde = '1' else 'Z';
5 S <= IO;
6 end architecture comport;

Correction TD 2 R.Hertelli : [email protected] 2/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

2 Correction exercice 2 :

Figure 1 – Multiplexeur Mux4

2.1 Équation

Q = A · B · I0 + A · B · I1 + A · B · I2 + A · B · I3

2.2 Entité

Listing 6 – Entité Mux4

1 Library IEEE;
2 use IEEE.std_logic_1164.all;

3 entity Mux4 is
4 port ( I0,I1,I2,I3,A,B : in std_logic;
5 Q : out std_logic);
6 end entity Mux4;

2.3 Architectures

Listing 7 – Architecture comportementale 1 de Mux4

1 architecture arch_comb1 of Mux4 is

2 begin
3
4 process(I0,I1,I2,I3,A,B)

Correction TD 2 R.Hertelli : [email protected] 3/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

5 variable sel : std_logic_vector(1 downto 0);

6
7 begin
8 sel := (A,B);
9 case sel is
10 when "00" => Q <= I0;
11 when "01" => Q <= I1;
12 when "10" => Q <= I2;
13 when "11" => Q <= I3;
14 when others => Q <= 'X';
15 end case;
16 end process;
17 end architecture arch_comb1;

Listing 8 – Architecture comportementale 2 de Mux4

1 architecture arch_comb2 of Mux4 is

2 begin
3
4 process (I0,I1,I2,I3,A,B)
5 begin
6 if ( A = '0' and B= '0') then Q<= I0;
7 elsif ( A = '0' and B= '1') then Q<= I1;
8 elsif ( A = '1' and B= '0') then Q<= I2;
9 elsif ( A = '1' and B= '1') then Q<= I3;
10 end if;
11 end process;
12 end architecture arch_comb2;

Listing 9 – Architecture flot de données 1 de Mux4

1 architecture arch_flotData1 of Mux4 is

2 begin
3 Q <= (not(A) and not (B) and I0) or (not(A) and B and I1)
4 or (A and not (B) and I2) or (A and B and I3) ;
5 end arch_flotData1;

Listing 10 – Architecture flot de données 2 de Mux4

1 architecture arch_flotData2 of Mux4 is

2 signal sel : std_logic_vector(1 downto 0);
3 begin
4 sel <= (A,B);
5
6 with sel select
7 Q <= I0 when "00",

Correction TD 2 R.Hertelli : [email protected] 4/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

8 I1 when "01",
9 I2 when "10",
10 I3 when "11",
11 'X' when others;
12 end architecture arch_flotData2;

2.3.1 Description structurelle

AND3
La figure suivante représente le composant logique AN D3

Figure 2 – AND3

Listing 11 – Conception AND3

1 library IEEE;
2 use IEEE.std_logic_1164.all;

3 entity AND3 is
4 Port (e0,e1,e2 : in std_logic ;
5 s : out std_logic);
6 end AND3;

7 architecture arch_DataFloat of AND3 is

8 begin
9 s <= e0 and e1 and e2 ;
10 end arch_DataFloat;

OR4
La figure suivante représente le composant logique OR4
Listing 12 – Conception OR4

1 library IEEE;
2 use IEEE.std_logic_1164.all;

3 entity OR4 is
4 Port (e0,e1,e2,e3 : in std_logic ;

Correction TD 2 R.Hertelli : [email protected] 5/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

Figure 3 – OR4

5 s : out std_logic);
6 end OR4;

7 architecture arch_DataFloat of OR4 is

8 begin
9 s <= e0 or e1 or e2 or e3 ;
10 end arch_DataFloat;

Structure interne Mux4

La figure suivante représente la composition interne de Mux4 à l’aide de AND3 et OR4.

Figure 4 – Mux4 vue externe

Listing 13 – Mux4 :architecture structurelle

1 architecture arch_struct of Mux4 is

2 component AND3 is
3 Port (e0,e1,e2 : in std_logic ;
4 s : out std_logic);
5 end component AND3;

6 component OR4 is
7 Port (e0,e1,e2,e3 : in std_logic ;
8 s : out std_logic);
9 end component OR4;

Correction TD 2 R.Hertelli : [email protected] 6/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

Figure 5 – Mux4 vue interne

10 --signaux internes
11 signal x0,x1,x2,x3 : std_logic ;
12 signal notA, notB : std_logic ;

13 begin
14 --Preparation des signaux inversees
15 notA <= not(A);
16 notB <= not(B);
17

18 --Instanciation et port mapping

19 UT0 : AND3 port map (notA,notB,I0,x0);
20 UT1 : AND3 port map (notA,B,I1,x1);
21 UT2 : AND3 port map (A,notB,I2,x2);
22 UT3 : AND3 port map (A,B,I3,x3);
23

24 UTT : OR4 port map (x0,x1,x2,x3,Q);

25 end architecture arch_struct;

2.4 Test et simulation

La figure suivante représente le principe de simulation :

Correction TD 2 R.Hertelli : [email protected] 7/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

Figure 6 – Simulation Mux4

Listing 14 – Test et simulation Mux4

1 library IEEE;
2 use IEEE.std_logic_1164.all;

3 --Entite vide sans Port

4 entity test_mux4 is
5 end entity test_mux4;

6 architecture testbench of test_mux4 is

7 --Importation de composant a tester

8 component Mux4 is
9 port ( I0,I1,I2,I3,A,B : in std_logic;
10 Q : out std_logic);
11 end component;

12 --Signaux interne de test

13 signal t_I0 , t_I1, t_I2,t_I3, t_A, t_B, t_Q :std_logic;

14 begin
15 --instatiation et port mapping
16 UT: Mux4 port map (t_I0,t_I1,t_I2,t_I3,t_A,t_B,t_Q);
17

18 --generation des tests

19 stimulus: process
20 begin
21 t_I0 <= '0';
22 t_I1 <= '0';
23 t_I2 <= '0';
24 t_I3 <= '0';
25
26 t_A <= '0';
27 t_B <= '0';
28 wait for 100 ns;
29

Correction TD 2 R.Hertelli : [email protected] 8/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

30
31 t_I0 <= '0';
32 t_I1 <= 'Z';
33 t_I2 <= '0';
34 t_I3 <= '1';
35 wait for 50 ns;
36 t_A <= '0';
37 t_B <= '1';
38 wait for 100 ns;

39 t_I3 <= '1';

40 wait for 50 ns;
41 t_A <= '1';
42 t_B <= '1';
43 wait for 100 ns;
44 end process;
45 end architecture testbench;
46
47 --selection architecture a tester
48 configuration config1 of test_mux4 is
49 for testbench
50 for UT : Mux4
51 use entity work.Mux4(arch_struct);
52 end for;
53 end for ;
54 end config1;
55
56

3 Correction exercice 3 :

Figure 7 – Demux 1 à 8

Correction TD 2 R.Hertelli : [email protected] 9/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

Listing 15 – Conception Demux

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;

4 entity Demux_1_To_8 is
5 port (G : in std_logic;
6 A : in std_logic_vector(2 downto 0);
7 Y : out std_logic_vector(7 downto 0) );
8 end Demux_1_To_8;

9 architecture arch1 of Demux_1_To_8 is

10 begin
11 PROCESS (G, A)
12 BEGIN
13 if (G = '0') then
14 Y <= (others => '0');
15 else
16 case A is
17 when "000" => Y <= "00000001";
18 when "001" => Y <= "00000010";
19 when "010" => Y <= "00000100";
20 when "011" => Y <= "00001000";
21 when "100" => Y <= "00010000";
22 when "101" => Y <= "00100000";
23 when "110" => Y <= "01000000";
24 when "111" => Y <= "10000000";
25 when others => Y <= "ZZZZZZZZ";
26 end case;
27 end if;
28 END PROCESS;
29 end architecture arch1;

30 architecture arch2 of Demux_1_To_8 is

31 begin
32 PROCESS (G, A)
33 variable temp : std_logic_vector(7 downto 0);
34 BEGIN
35 -- Initialisation temp
36 temp := (others => '0');
37 if (G = '1') then
38 case A is
39 when "000" => temp(0):= '1';
40 when "001" => temp(1):= '1';
41 when "010" => temp(2):= '1';
42 when "011" => temp(3):= '1';
43 when "100" => temp(4):= '1';
44 when "101" => temp(5):= '1';
45 when "110" => temp(6):= '1';
46 when "111" => temp(7):= '1';
47 when others => temp := (others =>'Z');
48 end case;
49 end if;

Correction TD 2 R.Hertelli : [email protected] 10/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

50 --Update Output
51 y<= temp;
52 END PROCESS;
53 end architecture arch2;

54 architecture arch3 of Demux_1_To_8 is

55 begin
56 process (A,G)
57 begin
58 Y <= (others => '0'); -- forcement en premier lieu
59 if (G = '1') then
60 Y(To_integer(unsigned(A))) <= '1';
61 --Le probleme avec cette description est que indice du bit dans Y
62 -- doit etre de type entier alors que A est de type std_logic_vector.
63 --Il faut donc utiliser une fonction de conversion definie dans le
64 -- package numeric_std, La conversion du
65 -- std_logic_vector en entier est obligatoire.
66 -- On passe par la conversion en unsigned puis integer
67 end if ;
68 end process;
69 end architecture arch3;

Listing 16 – Test Demux

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;

4 entity Test_Demux is
5 end entity Test_Demux;

6 architecture testbench of Test_Demux is

7 component Demux_1_To_8 is
8 port (G : in std_logic;
9 A : in std_logic_vector(2 downto 0);
10 Y : out std_logic_vector(7 downto 0) );
11 end component Demux_1_To_8;

12 signal t_G : std_logic;

13 signal t_A : std_logic_vector (2 downto 0);
14 signal t_Y : std_logic_vector (7 downto 0);

15 signal an : unsigned (2 downto 0):="000";

16 begin
17 UU : Demux_1_To_8 port map (t_G,t_A,t_Y);
18

19 process
20 begin
21 t_G<= '0';

Correction TD 2 R.Hertelli : [email protected] 11/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

22 t_A <= (others => '0');

23 wait for 100 ns;
24
25 bb : for i in 0 to 8 loop
26 t_A <= std_logic_vector (an);
27 an <= an +1;
28 wait for 50 ns;
29 t_G <='1';
30 end loop bb;
31 end process;
32 end architecture testbench;
33
34 --selection architecture a tester
35 configuration conf of Test_Demux is
36 for testbench
37 for UU : Demux_1_To_8
38 use entity work.Demux_1_To_8(arch1);
39 end for;
40 end for ;
41 end conf;

4 Correction exercice 4 :

Figure 8 – Encodeur de priorité 8 à 3

4.1 Encodeur de priorité 8 à 3 : Entité et architecture

Listing 17 – Encodeur de priorité 8 à 3

1 library ieee;
2 use ieee.std_logic_1164.all; -- std_logic
3 use ieee.numeric_std.all; -- Conversion

4 entity Priority_Encoder_8_To_3 is

Correction TD 2 R.Hertelli : [email protected] 12/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

5 port (E : in std_logic_vector(7 downto 0);

6 S : out std_logic_vector(2 downto 0);
7 GS : out std_logic);
8 end entity Priority_Encoder_8_To_3;

9 architecture comp1 of Priority_Encoder_8_To_3 is

10 signal zeros : std_logic_vector(7 downto 0) := (others => '0');

11 begin

12 process(E)
13 begin
14 --Calcul GS
15 if (E= zeros) then -- E = "0000 0000"
16 GS <= '1';
17 else
18 GS <= '0';
19 end if;

20 -- Determination de S
21 for I in E'range loop -- E'range :7,6,5,4,3,2,1,0
22 if E(I) = '1' then
23 S <= std_logic_vector(To_Unsigned(I,3));
24 exit ;
25 end if;
26 end loop;
27

28 end process;

29 end architecture comp1;

4.2 Encodeur de priorité 8 à 3 : Test et simulation

Listing 18 – Test Encodeur de priorité 8 à 3

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;

4 entity test_Priority_Encoder is
5 end entity test_Priority_Encoder;

6 architecture testbench of test_Priority_Encoder is

7 --Importation du composant
8 component Priority_Encode_8_to_3 is
9 port (E: in std_logic_vector (7 downto 0);
10 S : out std_logic_vector (2 downto 0);
11 GS : out std_logic);
12 end component Priority_Encode_8_to_3;

Correction TD 2 R.Hertelli : [email protected] 13/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

13 --signaux interne de test

14 signal t_E : std_logic_vector (7 downto 0);
15 signal t_S : std_logic_vector (2 downto 0);
16 signal t_GS: std_logic;

17 signal en : unsigned (7 downto 0);

18 begin
19 --instantiation et port mapping
20 UT : Priority_Encode_8_to_3 port map(t_E,t_S,t_GS);
21
22 process
23 begin
24 en <= (others => '0');
25 wait for 100 ns;
26
27 b0 : for i in 0 to 2**8 loop
28 t_E <= std_logic_vector (en);
29 en <= en +1;
30 wait for 100 ns;
31 end loop b0;
32
33 end process;
34 end architecture testbench;

4.3 Encodeur de priorité 2n à n :Entité et architecture

Listing 19 – Encodeur de priorité générique

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 use ieee.numeric_std.all; -- Conversion

4 entity Priority_Encode is
5 generic (n : positive);
6 port (E: in std_logic_vector ((2**n)-1 downto 0);
7 S : out std_logic_vector (n-1 downto 0);
8 GS : out std_logic);
9 end entity Priority_Encode;

10 architecture arch of Priority_Encode is

11 signal nul : std_logic_vector ((2**n)-1 downto 0) ;
12 begin
13 nul <= (others =>'0');
14 process (E)
15 begin
16 if ( E = nul) then
17 GS <= '1';
18 else

Correction TD 2 R.Hertelli : [email protected] 14/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

19 GS <= '0';
20 end if ;
21
22 S <= (Others => '0'); -- Faire sortir 0
23 cherche : for I in E'Range loop
24 if ( E(I) = '1' ) then
25 S <= std_logic_vector(To_Unsigned(I,n));
26 exit cherche; -- sortir de la boucle cherche
27 end if;
28 end loop cherche;
29 end process;
30 end architecture arch;

4.4 Encodeur de priorité 2n à n :Test et simulation

Listing 20 – Test Encodeur de priorité générique

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;

4 entity test_Priority_Encoder_Gen is
5 generic (m : positive := 8 );
6 end entity test_Priority_Encoder_Gen;

7 architecture testbench of test_Priority_Encoder_Gen is

8 component Priority_Encode is
9 generic (n : positive);
10 port (E: in std_logic_vector ((2**n)-1 downto 0);
11 S : out std_logic_vector (n-1 downto 0);
12 GS : out std_logic);
13 end component Priority_Encode;

14 signal t_E : std_logic_vector ((2**m)-1 downto 0);

15 signal t_S : std_logic_vector (m-1 downto 0);
16 signal t_GS: std_logic;

17 signal en : unsigned ((2**m)-1 downto 0);

18 begin
19 UT : Priority_Encode generic map (m) port map(t_E,t_S,t_GS);
20
21 process
22 begin
23 en <= (others => '0');
24 wait for 100 ns;
25
26 b0 : for i in 0 to 2**m loop
27 t_E <= std_logic_vector (en);
28 en <= en +1;

Correction TD 2 R.Hertelli : [email protected] 15/16

 Circuits Logiques Programmables (CPLD,FPGA,VHDL): 2024 / 2025 Iset Sousse

29 wait for 100 ns;

30 end loop b0;
31
32 end process;
33 end architecture testbench;

Correction TD 2 R.Hertelli : [email protected] 16/16