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Harvard Arch

The von Neumann model, attributed to John von Neumann, introduced stored-program computers with a central processing unit (CPU), memory system, and I/O system, allowing for sequential instruction processing. It operates on a fetch-decode-execute cycle but is limited by the von Neumann bottleneck, which is the single data path between the CPU and memory. Non-von Neumann models, including parallel processing architectures like data flow and systolic arrays, aim to overcome these limitations and enhance computational power.

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Sourav Chandra
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6 views14 pages

Harvard Arch

The von Neumann model, attributed to John von Neumann, introduced stored-program computers with a central processing unit (CPU), memory system, and I/O system, allowing for sequential instruction processing. It operates on a fetch-decode-execute cycle but is limited by the von Neumann bottleneck, which is the single data path between the CPU and memory. Non-von Neumann models, including parallel processing architectures like data flow and systolic arrays, aim to overcome these limitations and enhance computational power.

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Sourav Chandra
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© © All Rights Reserved
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The von Neumann Model

• On the ENIAC, all programming was done at


the digital logic level. Programming the
computer involved moving plugs and wires.

• A different hardware configuration was needed


to solve every unique problem type.

Configuring the ENIAC to solve a “simple” problem


required many days labor by skilled technicians.
The von Neumann Model

• The invention of stored program


computers has been ascribed to a
mathematician, John von Neumann.
• Stored-program computers has come to
known as von Neumann Architecture
systems.
The von Neumann Model

• Stored-program computers have the following


characteristics:
– Three hardware systems:
• A central processing unit (CPU)
• A memory system
• An I/O system
– The capacity to carry out sequential instruction
processing.
– A single data path between the CPU and main
memory.
The von Neumann Model

• This is a general
depiction of a von
Neumann system:

• These computers
employ a fetch-
decode-execute
cycle to run
programs as
follows . . .
The von Neumann Model

• The control unit fetches the next instruction from


memory using the program counter to determine where
the instruction is located.
The von Neumann Model

• The instruction is decoded into a language that the ALU


can understand.
The von Neumann Model

• Any data operands required to execute the instruction


are fetched from memory and placed into registers
within the CPU.
The von Neumann Model

• The ALU executes the instruction and places results in


registers or memory.
The von Neumann Bottleneck

The single path between CPU and main memory is


known as the von Neumann bottleneck.
The von Neumann Bottleneck

int sum = 0;
for ( int i =0;i< COL_SIZE ;i ++)
sum = sum + col [i];
Non-von Neumann Models

• Conventional stored-program computers have


undergone many incremental improvements
over the years.
• These improvements include adding
specialized buses, floating-point units, and
cache memories, to name only a few.
• But enormous improvements in computational
power require departure from the classic von
Neumann architecture.
• Adding processors is one approach.
Non-von Neumann or Harvard
Architecture

• Von Neumann
“alternative”
● Data memory and
program instructions
kept separate
● Parallel read/write from
program instructions
and data memory
○ Separate memory
buses
Non-von Neumann Models

• Parallel processing is only one method


of providing increased computational
power.
• DNA computers, quantum computers,
and dataflow systems. At this point, it is
unclear whether any of these systems
will provide the basis for the next
generation of computers.
Non-von Neumann Models

Two parallel architectures:


• Data flow - In the data flow architecture an instruction is ready for
execution when data for its operands have been made available.
Data availability is achieved by channeling results from previously
executed instructions into the operands of waiting instructions. This
channeling forms a flow of data, triggering instructions to be
executed. An outcome of this is that many instructions are executed
simultaneously, leading to the possibility of a highly concurrent
computation

• Systolic array - In a systolic array there are a large number of


identical simple processors or processing elements (PEs). The PEs
are arranged in a well-organized structure, such as a linear or two-
dimensional array. Each PE has limited private storage and is
connected to neighboring PEs.

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