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LAB 3 - Week3

The document discusses the behavior and applications of S-R, D, and J-K flip-flops in digital circuit design. It highlights the importance of clock signals in D flip-flops for data synchronization and the advantages of D flip-flops over R-S flip-flops. Additionally, it explains how to configure J-K flip-flops to behave like D flip-flops or toggle flip-flops.

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11 views7 pages

LAB 3 - Week3

The document discusses the behavior and applications of S-R, D, and J-K flip-flops in digital circuit design. It highlights the importance of clock signals in D flip-flops for data synchronization and the advantages of D flip-flops over R-S flip-flops. Additionally, it explains how to configure J-K flip-flops to behave like D flip-flops or toggle flip-flops.

Uploaded by

phatdinh171205.learn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LAB 3

S-R Flip-Flop:

Reset
Q

Set Q’

Set Reset Q Q’
1 0 1 0
1 1 0 0
0 1 0 1
1 1 0 0

Question 7: Describe in a sentence, the behaviour of the circuit when


one of the inputs is 1 (but not both) and why this is useful for digital
circuit design.
In an S-R flip-flop with a couple of NOR gates, the outputs will change Q =1 and
Q’ = 0 when S as 1. Moreover, when we continue to change S (Set) the outputs do
not change. On the other hand, when we turn on R as 1 the outputs are Q = 0 and
Q’ = 1. These outputs also do not change when we take R = 0.
This behaviour is useful for digital because it allows the circuit that can control and
hold one bit (binary information or sequential logic)
Question 8: What do you notice about the two times you set both
inputs to 1. Briefly explain what is happening here and why this is
an issue for digital circuit design?
When we set both inputs (SET and RESSET) to 1 the situation will not be defined
by the circuit. This is an indeterminant situation because of momentary
adjustments between states.
This is problematic for digital circuit design because it can result in signal glitches,
signal glitches, inconsistent circuit behavior, and incorrect data storage.

D-Flip Flop:

Q
Clock

Data
Q’

Clock Pin Q Q’
0 0 1 0
0 1 1 0
1 1 1 0
1 0 0 1
Truth table is based on the situation from circuit image.
Question 11: Briefly explain the behaviour of a D Flip Flop and how
it is useful for digital circuit design?
D-flip flop is commonly used in shift registers, memories, counters, and computer
registers. This circuit has only one input, Q is updated to be the same at D (Pin)
when the clock goes active. However, when the clock turns off (clock = 0), outputs
will maintain their value regardless of the change in the D input (Pin).
This is useful for digital because it can only be changed at the clock edge.
Question 12: What is the role of the clock? How does it impact the
changing of state of Q and Q’?
Timing and synchronization are important aspects of circuit design. The clock
signal plays a key role in determining when the flip-flop should capture data on its
D input. This signal synchronizes the flip-flop's operation with other components
in the circuit. The clock controls the state of the signal given to the circuit. When
the signal emitted by the clock is high the inputs get active, but if the signal
emitted by the clock gets low the output state of the circuit will not be affected
because the signal given to the input is low.

Question 13: Why is it generally preferred over the R-S Flip Flop?
D Flip-Flops are preferred over R-S Flip-Flops in digital circuits because for some
reasons such as D flip-flop is that it has a single data input, making it simpler to
design and implement in a circuit, invalid state prevention (such as both SET and
RESET are 1 in R-S flip flop) , stable timed operation because the input data (Pin)
is only stored when a clock signal is applied. This allows for more precise control
over when data is stored and retrieved, and lower power consumption.
JK-Flip Flop:

J
Q
Reset

Clock

Q’
K

J K Q(when clocked) Q’(when clocked)


0 0 No change No change
1 0 1 0
0 1 0 1
1 1 Toggle Toggle
Question 16: How can a J-K Flip Flop be made to behave like a D
Flip Flop?
To make a J-K flip-flop behave like a D flip-flop, tie both the J and K inputs of the
J-K flip-flop. It will need a specialized NOT gate for this where we can drive the
input J and K and connect it with the input D. This way J-K flip flop will be able to
be converted into a D flip flop.
Question 17: How can a J-K Flop be made to behave like a toggle (T
Flip Flop)?
Tie the J and K inputs together and apply the same input signal to both.
4 bit Register

Ox Input Binary Output Binary


0 0000 0000
1 0001 0001
2 0010 0010
3 0011 0011
5 0101 0101
A 1010 1010
B 1011 1011
C 1100 1100
D 1101 1101
E 1110 1110
F 1111 1111

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