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Efficient FPGA Implementation of RSA Algorithm Using Vedic Multiplier

Conference Paper · March 2023

DOI: 10.1109/WiSPNET57748.2023.10134210

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 Efficient FPGA Implementation of RSA Algorithm
Using Vedic Multiplier
Jegadish Kumar K J, Kaythry P, Gokhulesh V, Sudharsan K
2023 International Conference on Wireless Communications Signal Processing and Networking (WiSPNET) | 979-8-3503-0045-1/23/$31.00 ©2023 IEEE | DOI: 10.1109/WISPNET57748.2023.10134210

Department of Electronics and Communication

Sir Sivasubrmaniya Nadar College of Engineering
Chennai, India
,[email protected], [email protected]

Abstract—Technology cannot function effectively and recommended in this paper to decrease the delay and boost
securely without algorithms, which also enable integrity and efficiency.
encryption. To secure sensitive data, especially when it is
delivered over an unsecured network like the Internet, we Vedic mathematics simplifies the complex computations
employ the RSA (Rivest-Shamir-Adleman) Algorithm, which that are typically seen in traditional mathematics [2]. The
forms the backbone of the cryptosystem that permits public fact is that Vedic equations are centered on the same basic
key encryption. In a cryptosystem, multipliers are essential laws that govern how the human mind functions. Vedic
since they help to produce the desired results as efficiently as mathematics is a system of arithmetic principles that enables
possible. The enormous number of adders and other digital faster implementation. This is a fascinating topic that offers
circuits used in typical multipliers causes an increase in extremely powerful algorithms that can be used in many
propagation delay, which eventually reduces the multiplier's engineering disciplines, including computing. Vedic
efficiency. In contrast, the Vedic Multiplier can overcome this Multiplication is a branch of Vedic Mathematics where
issue and operates at high efficiency. The objective is to mathematical computation can be done is an easier way.
develop an effective 8 X 8 Vedic multiplier and implement it in Generally, Vedic Mathematics Formulae are called Sutras
the Field Programmable Gate Array (FPGA) using the and Sub-formulae are called as Sub-Sutras. There are 3
simulation tool Xilinx - ISE Design Suite 14.7. The effective Sutras and 2 Sub-Sutras for Vedic Multiplication in Vedic
performance metrics are compared with the pre-existing booth
Mathematics.
multiplier in terms of combinational path delay, number of
slices, and number of Look Up Table (LUT)s. Further, the The 3 Sutras used for multiplication are namely,
Modular exponentiation operation in RSA cryptosystem is
replaced with the proposed Vedic multiplier and booth • Ūrdhva Tiryagbhyāṃ
multiplier logics. The effectiveness of the RSA implementation
• Nikhilaṃ Navataścaramaṃ Daśataḥ
with these operator logics is compared in terms of delay and
area. • Ekādhikena Pūrveṇa
Keywords— Vedic multiplier, Booth multiplier, RSA The 2 Sub-Sutras used for multiplication are namely,
algorithm, Public Key Cryptography Introduction (Heading 1)
• Ānurūpyeṇa
I. INTRODUCTION • Antyayordaśake'pi
Building an integrated circuit (IC) with millions of Metal
Oxide Silicon (MOS) transistors on a single chip is known as Ūrdhva Tiryagbhyāṃ Sutra is chosen to implement as the
very large-scale integration (VLSI). Arithmetic circuits are vedic multiplier among the sutras and sub-sutras listed.
present in most computing devices and are used to conduct The Ūrdhva Tiryagbhyāṃ Sutra, a Vedic multiplication
specific arithmetic operations on binary data. These circuits formula, serves as the foundation for the created Vedic
are nothing more than a collection of gates coupled together multiplier. The multiplication of two numbers has been done
to perform arithmetic operations. The addition, subtraction, using this sutra. The sutra is adapted in the proposed work to
multiplication, or division of the following results in the gate make it compatible with digital hardware. A universal
circuit's outputs, whichever is specified as a function during multiplication formula that works in all situations is the
circuit design. In today’s world, the necessity of Arithmetic "Ūrdhva Tiryagbhyāṃ Sutra”, which signifies “Vertically
Circuits is inevitable in the VLSI Technology as it has and Crosswise". The two ends of the line's digits are
increased the efficiency of portable and embedded DSP multiplied, and the resulting sum is added to the carry from
systems[1]. So, the efficiency of these Arithmetic Circuits before. All outcomes are added to the previous carry when
decides the efficiency and performance of complex there are more lines in a step. The resultant number's least
integrated circuits. significant digit serves as one of the result digits, with the
A multiplier is a digital electronic circuit that multiplies remaining digits serving as the carry for the next step.
two binary values in electronic devices like computers. A Initially, the carry is assumed as zero.
digital multiplier is implemented using a variety of computer A good multiplier should be able to deliver a physically
arithmetic methods. The enormous number of adders and small, fast, and power-efficient device. Since multipliers are
other digital circuits used in general multipliers causes an a crucial component of mathematical processing units,
increase in propagation delay, which gradually reduces the demand for their speed and efficiency is sky-high. There are
multiplier's efficiency. Therefore, Vedic Multiplier is many methods for performing binary multiplication. The

979-8-3503-0045-1/23/$31.00 ©2023 IEEE

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 decision is typically made based on variables like delay, Algorithms have been extended to signed numbers by the
throughput, area, and design complexity. Some of the Urdhva Tiryagbhyam Sutra, which has been put into practise.
common methods for hardware implementation of binary The architecture of the 8 x 8 Vedic multiplier is based on the
multipliers that are appropriate for VLSI implementation at redundant binary representation theory. This was created on
the CMOS level are the array multiplier and the booth an FPGA using Xilinx ISE 14.4 and VHDL. The proposed
multiplier. architecture performs better in terms of power usage than the
conventional multiplier architecture.
This work aims to create a high-speed, efficient 8 x 8
Vedic multiplier using the " Ūrdhva Tiryagbhyāṃ Sutra " Nithesh Kumar Sharma et.al (2020) compared the
implementation on an FPGA. The aforesaid Vedic multiplier Nikhilam Navatacaramam Dasatah Sutra and Urdhva
is implemented in RSA cryptosystem by replacing Tiryagbhyam Sutra for VedPredryrgltic Multipliers [7]. This
conventional multipliers like Booth multiplier, Montgomery demonstrates unequivocally that the urdhva Tiryagbhyam
multiplier, etc. This increases the efficiency of an RSA Sutra-designed Vedic multiplier produces far less
cryptosystem in terms of processing speed and area. computational delay than the Nikhilam Navatacaramam
Dasatah Sutra design. The authors strongly recommend the
The rest of the paper is organized as follows. Section II Urdhva Tiryagbhyam Sutra for the Vedic Multiplier.
briefly notes the literature survey done to review related
works. The Vedic multiplier design is discussed in detail in A. Abdul Hayum et.al (2021) explained the different
section III. The proposed 8x8 Vedic multiplier types of adders used and compared their propagation delay
implementation in RSA algorithm is presented in section IV. and power comparison[1] It explains the importance of
The simulation and synthesis results are given in section V. power dissipation (i.e., heat produced) in the chip level.
The conclusion of the proposed Vedic Multiplier usage in the Nikhilaṃ Navataścaramaṃ Daśataḥ Sutra for their Vedic
digital multiplier is given in Section VI. Multipliers. They deal with using of various high speed and
low-power adders for the design of a 2 x 2 Vedic Multiplier
II. RELATED WORK and results are compared in some parameters like the delay,
Multiplier circuits can be designed and implemented in area utilized, power consumption and power dissipation.
application-specific integrated circuit (ASIC) technique or Y.G. Praveen Kumar et.al (2020) presented the design of
FPGA through Xilinx ISE. There are several multiplication different types of multiplier circuits like Array multiplier,
methods available in the literature to design multiplier Booth Multiplier, Wallace tree multiplier and Vedic
circuits. Each method has its own advantages in terms of Multiplier [8]. The authors analyzed the efficiency of
speed, power consumption, layout regularity and area. multipliers in terms of speed and power. Array, Booth,
Wallace tree architectures were proposed for implementing
Hui Chen et.al (2021) proposes the use of Vedic multiplier, but multiplier based on Vedic Mathematics (i.e.,
Multiplication techniques in multiplier circuits to reduce the Vedic Multiplier) results in high-speed computation.
delay [4]. The authors used the Vedic Multiplier built using
the Nikhilaṃ Navataścaramaṃ Daśataḥ Sutra Vedic T. Sravanthi Devi et.al (2017) presented the Vedic and
Multiplication Technique to compute XY Squaring. The Squaring multiplier architecture for analyzing the speed.
suggested multiplier architecture reduces the delay to 62.77 Authors explored the method to square bits using Vedic
%, the area utilization to 78.57% and the power Nikhilaṃ Navataścaramaṃ Daśataḥ logic. All of the partial
consumption to 81.89% . products are modified using the concatenation operation, and
they are all added using a single carry save adder instead of
Jin-Hua Hong et.al (2003) preferred RSA algorithm over using two adders. This shortens the computation delay. The
the AES algorithm for data encryption and security [5]. The architecture was created in Verilog HDL code, used
distinction between private key encryption and public key VIVADO 2015.2 to simulate it, and implemented it on a
encryption is implied. For RSA public key cryptosystem, ZYNQ board for hardware (FPGA). They used one Vedic
authors provided a fast radix-4 modular exponentiation multiplier, which significantly minimizes the area used, as
method and a radix-4 modular multiplication algorithm opposed to utilising four multipliers.
based on Montgomery's algorithm. The authors studied the
concept of pipelining to decrease the delay and increase the Sumit Vaidya et.al (2010) analysed Array multiplier,
speed by four times. Wallace Multiplier, Booth Multiplier, and Vedic Multiplier,
in terms of delay, area, power consumption, design
Nilam Gadda et.al (2020) compared the delay parameter complexity, and FPGA implementation [9]. A comparative
of several multipliers like Booth multipliers, Array study of the above-mentioned multipliers are done to achieve
multipliers, Karatsuba multipliers, and others [6]. They low power requirement and high speed (i.e., Reduced Delay).
concluded that the Vedic Multiplication Sutras made the Additionally, the number of iterations is reduced while
implemented arithmetic module the most effective in terms computing multiplication.
of reducing delay by 85%. In this instance, the Vedic
Multiplication Sutra known as "Urdhva Tiryagbhyam" was Sushanta Kumar Sahu et.al (2011) studied the flow of
employed. The delay of the created Vedic Multiplier RSA Algorithm and implemented Vedic Multiplier in
employing the "Urdhva Tiryagbhyam Sutra" is 4.014ns, encryption. Also, Square and Multiply Algorithm was used
which is very less when compared to the above-mentioned which simplifies the process of RSA encryption
multipliers. They compared this delay with that of other (exponentiation during encryption). Applying the Square and
multipliers such as booth multipliers, array multipliers, Multiply algorithm cuts down the delay and depicts the use
karatsuba multipliers, etc. in RSA cryptosystem.

Chennamadhava Mahitha et.al (2021) demonstrated a

space- and energy-efficient Vedic Multiplier. The Vedic

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 III. DESIGN OF VEDIC MULTIPLIER more than 8 bits, and it is written as ‘r’. The digits on each
Based on Vedic mathematics, the Vedic multiplier is side of the line are multiplied and added with the carry
developed and implemented in this study. The Vedas served from the previous step, just like in the preceding instance.
as a foundational source of information and an infinite This produces a carry as well as one of the result's bits.
repository of all knowledge. The four Vedas (books of The following step is adding this carry, and so forth all
knowledge) include the ancient Indian mathematical results are added to the previous carry if there are multiple
approach known as Vedic mathematics [2]. It utilizes a lines in one step. The least significant bit serves as the
special calculating method based on the 16 sutras (formulae). result bit for each step, and the other bits serve as the
It covers a variety of contemporary mathematical concepts, carry.
including factorization, quadratic equations, geometry,
trigonometry, and arithmetic. The Urdhva Triyakbhyam Step 1 Step 5
Sutra, an all-purpose multiplication formula, is the a3 a2 a1 a0 a3 a2 a1 a0
foundation upon which the Vedic algorithm is implemented
in the multiplier.
Literally, Urdhva Tiryakbyham means "vertical and b3 b2 b1 b0 b3 b2 b1 b0
crosswise." For NxN bit numbers, this formula is generalised c0r0 = a0b0 c4r4= a3b1+a2b2+ a1b3
by vertical and crosswise multiplication notion that worked
well with the parallel multiplication process, thus satisfying Step 2 Step 6
speedy multiplication process with decreased amount of
a3 a2 a1 a0 a3 a2 a1 a0
partial products [2]. Further, in the section the design of
vedic multiplier is examined.
A. 2 x 2 Vedic Multiplier
In the construction of the 2-bit Vedic multiplier, the 2-bit b3 b2 b1 b0 b3 b2 b1 b0
multiplier needs the fundamental AND gates and Half adder c1r1 = a1b0 + a0b1 c5r5= a3b2+a2b3
logic circuits to perform the vertical and crosswise algorithm.
Let A and B are the two numbers which are given to the 2×2 Step 3 Step 7
multiplier, where A= {a1, a0} and B= {b1, b0}. Four 2-input a3 a2 a1 a0 a3 a2 a1 a0
AND gates and two half adders are required for the creation
of the 2-bit Vedic multiplier. Vertical and crosswise
multiplication are used in the algorithm.
b3 b2 b1 b0 b3 b2 b1 b0
B. 4 x 4 Vedic Multiplier c2r2= a2b0+a1b1+ a0b2 c6r6= a3b3
The steps involved in 4-bit Vedic multiplier is shown in
figure 1. The fundamental Ripple Carry Adder (RCA) is used Step 4
though the combinational path delay is high. A single 6-bit a3 a2 a1 a0
ripple carry adder adds the partial products in a 4-bit Vedic
multiplier that uses the 2x2 Vedic multiplier as a
fundamental building block. Concatenation is utilised in this
multiplier to combine the partial product r3 [3:0] with the r0
[3:2] to avoid the number of adders so, that the remaining b3 b2 b1 b0
partial products r2 [3:0] and r1 [3:0] are given to the adder. c3r3= a3b0+a2b1+ a1b2+ a0b3
Fig.1 Steps involved in 4 x 4 Vedic multiplier
Let's multiply two 4-bit binary values, a3 a2 a1 a0 and b3
b2 b1 b0, as the multiplication algorithm. As this
multiplication produces a value with more than 4 bits, it is Fig.1 Steps involved in 4 x 4 Vedic multiplier
written as r3 r2 r1 r0. The digits on either side of the line are
multiplied by the carry from the previous step before being
added. This results in a carry and one of the bits of the result. IV. IMPLEMENTATION OF VEDIC MULTIPLIER IN RSA
As this carry is included in the subsequent steps, the process CRYPTOSYSTEM
continues. All outcomes are added to the previous carry if
A. RSA Algorithm
there are numerous lines in one step. The carry is represented
by the other bits, while the outcome bit for each step is the In RSA algorithm. the plaintext and ciphertext uses
least significant bit. For example, in intermediate step, for a integers between 0 and n-1, where n =1024 bits, or 309
result of 011, 1 (LSB) be the resultant bit and 01 as the carry. decimal digits, is a standard size for n is less than 21024. The
RSA Algorithm involves three steps namely, Key
C. 8 x 8 Vedic Multiplier
Generation, Encryption and Decryption. The generation of
The 8-bit Vedic multiplier using Ūrdhva Tiryagbhyāṃ Keys is shown in the figure 3.
sutra is illustrated in Figure 2. The designed 4-bit Vedic The RSA Encryption and decryption algorithm in the
multiplier using Ūrdhva Tiryagbhyāṃ sutra is used as a simplest form is expressed in equation (1) and (2). Plaintext
basic building block for the design of 8-bit Vedic block M is encrypted to a Cipher text block C by
multiplier. Let the multiplication of two 8-bit binary
values A and B be performed using the algorithm C = Me mod n (1)
described. The multiplication would produce a value of

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 Plaintext block is recovered(decrypted) by time. Further to minimize the computational delay in
exponentiation process in RSA encryption and decryption,
M = Cd mod n (2) the Vedic Multiplier is used instead of Booth Multiplier.

B. Square and Multiply Algorithm

The modular exponentiation operation in the RSA
encryption and decryption is performed using Square and
multiply algorithm. The multiplier in the square and
multiply algorithm is performed using Vedic multiplier. The
following is the pseudo code for square and multiply
algorithm.

Input: M, e, n
Output: C = Me mod n
Convert e from Decimal to Binary.
Let e contain k bits.
If ek-1 = 1 then C=M else C=1
For i = k-2 down to 0
C=CXC
if ei = 1 then C= C X M
V. SIMULATION AND SYNTHESIS RESULTS
After verifying the simulation results, the 8 x 8 vedic
multiplier and booth multiplier is synthesized. Then, the
RSA cryptosystem using the 8 x 8 vedic multiplier and
booth multiplier is simulated and synthesized. The
Fig. 2 8x8 Vedic Multiplier Architecture comparison of both Vedic Multiplier and Booth Multiplier
implemented in RSA cryptosystem is presented with various
parameters like Delay and Area. The proposed algorithm is
coded in Verilog and synthesized in Spartan 3E family with
Device XC3S1600E of Package FG484 in Xilinx ISE.
The table I presents the performance comparative study of
8-bit booth multiplier and vedic multiplier. In table I, it is
observed that the combinational path delay of vedic
multiplier logic is decreased by 35.05% with respect to
combinational path delay of booth multiplier logics. The
number of slices utilized by vedic multiplier is decreased by
12.39 % with respect to slices utilized by booth multiplier.
The number of LUTs utilized by vedic multiplier is
decreased by 20.83% with respect to LUTs utilized by the
booth multiplier. Thus, vedic multiplier logics are highly
Fig. 3 RSA Key Generation Flow Chart efficient than booth multiplier in terms of delay and area.

TABLE I. 8 X 8 VEDIC MULTIPLIER PERFORMANCE PARAMETER

An exponential expression is used in RSA to perform ANALYSIS
encryption and decryption. Each block of the plaintext
encryption process has a binary value that is less than some Performance parameter
number n. That is, the block size must be less than or equal Type of 8 x8 Area Utilization
to log2(n) + 1; in fact, the block size is i bits, where 2i < n Multiplier Combinational Number of Number of
<= 2i+1. Path Delay Slices ( out of LUTs (out of
14572) 29504)
Booth
Sender and recipient must both be cognizant of the value Multiplier
40.292 ns 121 240
of n. Only the recipient is aware of the value of d; the sender Vedic
26.169 ns 106 190
is aware of the value of e. Thus, this is a public-key Multip0lier
encryption algorithm with a public key PUB = {e,n} and a
private key of PRI = {d,n}. The table II presents the performance comparative study
of implementation of RSA cryptosystem with 8-bit booth
The RSA algorithm's encryption logic involves multiplier and vedic multiplier. In table II, it is observed
exponentiation on massively high numbers. When that the combinational path delay of RSA cryptosystem with
performing such calculations, the square and multiply vedic multiplier logic is decreased by 10.18% with respect
method is utilised to obtain the output without using to combinational path delay of booth multiplier logics.
conventional exponentiation that cost with high computation

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 The number of slices utilized by RSA cryptosystem with can be implemented using carry look ahead adder, carry
vedic multiplier is decreased by 16.54 % with respect to save adder and their performance can be analyzed.
slices utilized by booth multiplier. The number of LUTs
REFERENCES
utilized by RSA cryptosystem with vedic multiplier is
decreased by 14.89% with respect to LUTs utilized by the [1] A Abdul Hayum, G Sujatha, Mohd Naved, S Chinnapparaj, G
booth multiplier. Thus, RSA cryptosystem with vedic Thamarai Selvi and P Mohanraj, “Review of Vedic Multipliers using
various Full Adders" in Proceedings of the Fifth International
multiplier logics is highly efficient than RSA cryptosystem Conference on Computing Methodologies and Communication
with booth multiplier in terms of delay and area. (ICCMC 2021), India, March 2022.
[2] Bharati Krishna Tirtha, “Vedic Mathematics”, Motilal Banarsidass
TABLE II. PERFORMANCE PARAMETER ANALYSIS OF MULTIPLIER Publications, 1965
IMPLEMENTATION IN RSA CRYPTOSYSTEM [3] C.Mahitha, C.S. Saishree.C.S. Ayyar, Saandeep Dutta B, Aiswarya
Performance parameter Othayoth and Ramesh S R, “A Low Power Signed Redundant Binary
RSA Vedic Multiplier” in Proceedings of the Fifth International
Cryptosystem Conference on Trends in Electronics and Informatics, India , June
Area Utilization
with 2021.
Combinational Number of Number of
Type of 8 x8 [4] Hui Chen, Heping Yang, Wenqing Song, Zhonghai Lu, Yuxiang Fu,
Path Delay Slices (out of LUTs (out of
Multiplier Li Li and Zongguang Yu, “Symmetric- Mapping LUT-Based Method
14752) 29504)
Booth and Architecture for Computing XY Like Functions,” IEEE
97.814 ns 326 611 Transactions on Circuits and Systems, vol.68, no.3, pp.1231-1244
Multiplier
Vedic March 2021
87.849 ns 272 520
Multip0lier [5] Jin- Hua Hong, Cheng-Wen Wu, “Cellular-Array Modular Multiplier
for Fast RSA Public-Key Cryptosystem Based on Modified Booth’s
VI. CONCLUSION Algorithm,” IEEE Transactions on VLSI Systems. vol. 11, no. 3,
pp.474-484 June 2003.
Cryptography plays a major role in secure transactions in [6] Nilam Gadda and Dr.U.Eranna, “64-bit ALU Design Using Vedic
the banking sector. RSA cryptosystem is primarily used for Mathematics,” International Conference on Emerging Trends in
secure banking transactions constrained to speed. Hence, it Information Technology and Engineering, India, Feb. 2020
is essential to implement vedic multiplier in RSA [7] Nitesh Kumar Sharma, Deepesh Kumar Gautam and Dr. M. R. Khan,
cryptosystem to increase the speed and reduce the delay. In “Comparative Analysis on Multiplier,” 11th International
Conference on Computing Communication and Networking
this proposal, RSA cryptosystem is designed using both Technologies, India, July 2020.
vedic multiplier and booth multiplier and implemented in [8] Y.G. Praveen Kumar, B.S. Kariyappa, Basavaraj H Patil , Anil kumar
Spartan 3E family with device XC3S1600E of package Naik, Pavan kumar and M Z Kurian, “Power Efficient and High
FG484 in Xilinx ISE. Speed Multiplier based on Ancient Mathematics: A Review,” in
Proceedings of the International Conference on Electronics and
From the synthesis analysis of the implementation, the Sustainable Communication Systems (ICESC 2020), India, July 2020.
delay of RSA cryptosystem with Vedic multiplier is less [9] T.Sravanthi Devi, A. Madhu Sudhan, “FPGA Implementation of 32-
than that with a booth multiplier. Also, the area utilized by Bit vedic multiplier and square architectures,” Global Journal of
research analysis volume – 6, issue – 3 , pp-625-627, March -2017.
RSA cryptosystem using Vedic multiplier is less when [10] .Sumit Vaidya and Deepak Dandekar, “Delay-Power Performance
compared to the RSA cryptosystem using the booth Comparison of Multipliers in VLSI Circuit Design,” Int. J. of
multiplier. This proves the efficiency of Vedic multiplier Computer Networks & Communications (IJCNC), vol.2, no.4, pp 47-
56, July 2019.
logic compared to conventional and booth multipliers. In [11] S. K. Sahu and M. Pradhan, "Implementation of Modular
this work RCA is used in 8 x 8 vedic multiplier because of Multiplication for RSA Algorithm," 2011 International Conference on
its simple architecture. Further, the 8 x 8 vedic multiplier Communication Systems and Network Technologies, Katra, India,
2011, pp. 112-114, doi: 10.1109/CSNT.2011.30.

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