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Lecture 2

The document outlines the VLSI design flow, which includes front-end and back-end design processes, detailing steps from design entry to fabrication and testing. It introduces the Y-chart representing three design domains: behavioral, structural, and geometrical layout, emphasizing the importance of design hierarchy, regularity, modularity, and locality in VLSI design. The lecture is prepared by Tapas Tewary and Subham Pramanik from the ECE Department at the Academy of Technology.

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10 views5 pages

Lecture 2

The document outlines the VLSI design flow, which includes front-end and back-end design processes, detailing steps from design entry to fabrication and testing. It introduces the Y-chart representing three design domains: behavioral, structural, and geometrical layout, emphasizing the importance of design hierarchy, regularity, modularity, and locality in VLSI design. The lecture is prepared by Tapas Tewary and Subham Pramanik from the ECE Department at the Academy of Technology.

Uploaded by

sauravsamrat948
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 1: Introduction to VLSI Design

Lecture 2: VLSI Design flow, Y chart, Design Domain, Design Hierarchy, Concepts of Regularity,
Modularity, Granularity and Locality

2.1 VLSI Design Flow:


A design flow is a sequence of operations that transform the IC designers’ intention. A well-tuned
design flow can help designers go through the chip-creation process relatively smoothly and with
a decent chance of error-free implementation. And, a skilful IC implementation engineer can use
the design flow creatively to shorten the design cycle, resulting in a higher likelihood that the
product will catch the market window.

Front-end design (Logical design):


1. Design entry – Enter the design in to an ASIC design system using a hardware
description language (HDL) or schematic entry
2. Logic synthesis – Generation of net list (logic cells and their connections) from HDL code.
Logic synthesis consists of following steps: (i) Technology independent Logic optimization (ii)
Translation: Converting Behavioral description to structural domain (iii) Technology mapping or
Library binding
3. System partitioning - Divide a large system into ASIC-sized pieces

4. Pre-layout simulation - Check to see if the design functions correctly. Gate level unctionality
and timing details can be verified.

Back-end design (Physical design):


5. Floor planning - Arrange the blocks of the netlist on the chip

6. Placement - Decide the locations of cells in a block

7. Routing - Make the connections between cells and blocks

8. Circuit Extraction - Determine the resistance and capacitance of the interconnect

9. Post-layout simulation - Check to see the design still works with the added loads of the
interconnect

Simplified Design Flow: The VLSI design flow is a sequence of steps followed to translate the
idea of a system into a chip. The flow is based on the standard design automation tools. The basic
steps are shown in the following figure. It starts with system specifications such as area, speed,
and power. Then the functional design is done followed by functional verification to check if the
design is correct. In this phase, the design is described at the behavioral level. Next, the design is
implemented at the logic level and verified for its correctness. This is followed by the transistor
level or circuit design verification. Up to this step, the flow is known as logical design. The next
phase is the physical design which actually deals with the geometry of the chip. Once the physical
layout is generated, it must be verified to check if the layout really implements the actual design.
The last and final step is the fabrication and testing of the chip.
2.2 Y Chart and Design domains
The Y-chart (first introduced by D. Gajski) shown in Figure illustrates a design flow for most logic
chips, using design activities on three different axes (domains) which resemble the letter "Y." The
Y-chart consists of three domains of representation, namely
(i) Behavioral domain, ii) Structural domain iii) Geometrical layout domain.
In the behavioral domain, a circuit is described fully by its behavior without describing its physical
implementation or structure. In the structural domain, a circuit is described by its components and
their interconnections. The physical domain deals with actual geometry of the circuit and describes
the shape, size, and locations of its components.
[Detail Description: The design flow starts from the algorithm that describes the behavior of the
target chip. The corresponding architecture of the processor is first defined. It is mapped onto the
chip surface by floor planning. The next design evolution in the behavioral domain defines finite
state machines (FSMs) which are structurally implemented with functional modules such as
registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the
chip surface using CAD tools for automatic module placement followed by routing, with a goal of
minimizing the interconnects area and signal delays. The third evolution starts with a behavioral
module description. Individual modules are then implemented with leaf cells. At this stage the chip
is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a
cell placement and routing program. The last evolution involves a detailed Boolean description of
leaf cells followed by a transistor level implementation of leaf cells and mask generation. In the
standard cell based design style, leaf cells are pre-designed (at the transistor level) and stored in a
library for logic implementation, effectively eliminating the need for the transistor level design.]

Gajaski-Kuhn Y chart

2.3 Design Hierarchy, Concepts of Regularity, Modularity, Granularity and Locality


 Design Hierarchy: The use of the hierarchy, or "divide and conquer" technique involves
dividing a module into sub-modules and then repeating this operation on the sub-modules
until the complexity of the smaller parts becomes manageable.

 Regularity: Regularity means that the hierarchical decomposition of a large system should
result in not only simple, but also similar blocks, as much as possible.
 Modularity: Modularity in design means that the various functional blocks which make
up the larger system must have well-defined functions and interfaces. Modularity allows
that each block or module can be designed relatively independently from each other, since
there is no ambiguity about the function and the signal interface of these blocks. All of the
blocks can be combined with ease at the end of the design process, to form the large system.

 Locality: Hierarchical decomposition must also consider the locality of the functional
blocks. The decomposition should be such that the blocks, exchanging signals frequently,
must be close to each other in order to reduce the interconnect length. Again, the internal
wiring must be local and should not affect other modules.

----------------------------------------------------END OF LECTURE-------------------------------------------------

Reference:
1. CMOS Digital Integrated Circuit, S.M.Kang & Y.Leblebici, TMH.
2. VLSI Design, Debaprasad Das, OUP
-------------------------------------------------------------------------------------------------------------------
Prepared By
Tapas Tewary and Subham Pramanik, ECE Department, Academy of Technology

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