Embedded Systems

July 2021
Students are requested to refrain from using these learning resources outside this domain

Dr Binu Paul , Embedded System

9/6/2021 1
Lecture 5-6
 Module 1 – part 2

• Overview of the 8051 family. 8051 architecture- memory

organization, registers and I/O ports. Addressing modes,
instruction sets, and assembly language programming.
Programming timer/counter. Interrupts- handling and
programming. Introduction to C programming in 8051

9/6/2021 Dr Binu Paul , Embedded System Lecture 5-6 2

 TYPICAL EMBEDDED SYSTEM ( REVIEW- DAY4)
DR BINU PAUL - JULY 2020

• Typical embedded system-

• Core of the embedded system [ MCU 8051/8751/ 8951]

• Sensors and actuators
• Reset circuit, Brown-out protection circuit, oscillator circuit, Watchdog timer
• Memory
• Communication Interface

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 A TYPICAL CIRCUIT.. ( REVIEW- DAY4)

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 8051 MICROCONTROLLER _DAY 5

Block Diagram and Pin Description of the 8051

Registers
Memory mapping in 8051
Stack in the 8051
Timer
Interrupt
Addressing modes
Instructions
Programming

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 THE NECESSARY PARTS IN A MICROCONTROLLER

• Hardware :Interface to
 CPU: Central Processing Unit
the real world  I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
• Software : to handle  Parallel Port
with inputs  ADC/DAC

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 MICROPROCESSORS:
General-purpose microprocessor

 CPU for Computers

 No RAM, ROM, I/O on CPU chip itself
 Example：Intel’s x86, Motorola’s 680x0,AMD …

Many chips on mother’s board

Data Bus
CPU
General- Serial
Purpose RAM ROM I/O Timer COM
Micro- Port Port
processor
Address Bus

General-Purpose Microprocessor System

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 Microcontroller

 A smaller computer
 On-chip RAM, ROM, I/O ports...etc….
 Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and Microchip’s PIC16X

CPU RAM ROM

In a single chip
Serial
I/O Timer COM
Port Port Microcontroller

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 Comparison
Microprocessor Microcontroller

No on chip memory available on chip memory(ROM ,RAM, flash memory )

available
No built in peripherals Has built in i/o ports, serial ports, ADC/DAC, timer
etc.. On chip
No bit addressability (in earlier ones) Bit addressable RAM on chip

Expensive but versatile and supports general-purpose Ideal for stand alone dedicated applications where
applications . (ex. SLV control) cost, power and space are critical. (ex Washing
machine)
Several op codes for external memory access Limited instructions to access external memory

Complex but rich instruction set Simple lean instruction set (but increased programmer
overhead)
Involves rapid data /code movement between chip Involves rapid bit/byte movements inside chip
and external memory locations

Ex. 8086,icore7 etc… Ex. 8051,80960 etc..

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 BLOCK DIAGRAM(8051)
External
interrupts
INT 0 INT1 On-chip
ROM(4kB) Timer/Counter

Interrupt for On-chip

Timer 1 Counter
program RAM,
Control 128 bytes Inputs
Internal code Timer 0
interrupts To,T1

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD

Address/Data

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 Block Diagram 8051 contd…

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 Pin Description of the 8051

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 

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 PINS OF 8051（1/4）

 /EA（pin 31）：external access

 There is no on-chip ROM in 8031 and 8032 .
 The /EA pin is connected to GND to indicate the code is stored
externally.
 /PSEN ＆ ALE are used for external ROM.
 For 8051, /EA pin is connected to Vcc.
 “/” means active low.
 /PSEN（pin 29）：program store enable
 This is an output pin and is connected to the /OE pin of the ROM.

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 PINS OF 8051（2/4）

 ALE（pin 30）：address latch enable

◦ It is an output pin and is active high.

◦ 8051 port 0 provides both address and data.
◦ The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.(when external memory is connected)
 I/O port pins

◦ The four ports P0, P1, P2, and P3.

◦ Each port uses 8 pins.
◦ All I/O pins are bi-directional.

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 PINS OF I/O PORT(3/4)

 The 8051 has four I/O ports

 Port 0 （pins 32-39）：P0（P0.0～P0.7）
 Port 1（pins 1-8） ：P1（P1.0～P1.7）
 Port 2（pins 21-28）：P2（P2.0～P2.7）
 Port 3（pins 10-17）：P3（P3.0～P3.7）
 Each port has 8 pins.
 Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X
 Ex：P0.0 is the bit 0（LSB）of P0
 Ex：P0.7 is the bit 7（MSB）of P0
 These 8 bits form a byte.
 Each port can be used as input or output (bi-direction).


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 PINS OF I/O PORT(4/4)
 P1, P2, and P3 have internal
pull-up resisters.
◦ P1, P2, and P3 are not open drain.
 P0 has no internal pull-up
resistors and does not connects
to Vcc inside the 8051.
◦ P0 is open drain.
 However, for a programmer, it is
the same to program P0, P1, P2 Vcc
and P3. 10
 All the ports upon RESET are K
configured as output.
P0.0

Port
8051 P0.1
P0.2
8751 P0.3
P0.4 0
8951 P0.5
P0.6 
P0.7
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 PORT 3 ALTERNATE FUNCTIONS

P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17 

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 POWER-ON RESET CIRCUIT
Vcc

+
10 uF
31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST


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 Registers Address
A 0E0h
B 0F0h
PSW 0D0h
SP 81h
DPTR(h) 83h
DPTR(l) 82h
R0-R7 Depending on Banks

IP 0B8h
PSW format IE 0ABh

CY AC F0 RS RS OV x P P0-P3 80h,90h,0A0h,0B0h
1 0
SCON 98h
RS1 RS0 selection
00 Bank 0
SBUF 99h

01 Bank 1 PCON 87h

10 Bank2 Timer 89h-8Dh
registers(TCON,
TMOD,TH1,TH0,
11 Bank3
TL1,TL0 )
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DR BINU PAUL , EMBEDDED SYSTEM LECTURE 5-6
 RESET VALUE OF SOME 8051 REGISTERS:

Register Reset Value

PC 0000
A 00
B 00
PSW 00
SP 07
DPTR 0000
RAM are all zero.
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 20
 MEMORY MAPPING IN 8051
 ROM memory map in 8051 family

8k
1FFFH 32k
4k 7FFFH

0FFFH

0000H DS5000-32
0000H
8051, 8751
AT89C51
8752
0000H
AT89C52

from Atmel Corporation

from Dallas Semiconductor

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 PROGRAM MEMORY ARRANGEMENT
(ROM – EXTERNAL OR INTERNAL OR BOTH)

Ex: in MCU 51 family

64kbytes

60kb

4kb

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 RAM MEMORY ALLOCATION( 128 BYTES)
7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM
20H
1FH
Register Bank 3
Stack and Bank 1 18H
clash occurs on reset, 17H
10H
Register Bank 2
As SP on reset
0FH (Register Bank 1
points at 07h
08H
07H Register Bank 0
00H
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 STACK OF 8051 ( SP REGISTER HAS ADDRESS 81H)
 The register used to access
the stack is called SP (stack
7FH
pointer) register.
Scratch pad RAM

30H
 The stack pointer in the
2FH
8051 is only 8 bits wide, Bit-Addressable RAM
which means that it can 20H
take value 00 to FFH. 1FH Register Bank 3
When 8051 powered up, 18H
17H
the SP register contains 10H
Register Bank 2

value 07. 0FH (Stack) Register Bank 1

08H
07H
Register Bank 0
00H

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 Allocation of 128 bytes internal RAM
7FH

Scratch pad RAM Address of registers in the

128 bytes RAM
30H
A 0E0h
2FH
Bit-Addressable RAM B 0F0h

20H PSW 0D0h

1FH Register Bank 3
18H SP 81h
17H
Register Bank 2 DPTR(h) 83h
10H
0FH (Stack) Register
08H DPTR(l) 82h
Bank 1
07H
Register Bank 0 R0-R7 Depending on Banks
00H

PSW format IP 0B8h

CY AC F0 RS1 RS0 OV x P IE 0ABh
RS1 RS0 selection
P0-P3 80h,90h,0A0h,0B0h

00 Bank 0 SCON 98h

01 Bank 1
SBUF 99h
10 Bank2

11 Bank3 PCON 87h

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DR BINU PAUL , EMBEDDED SYSTEM LECTURE 5-6
PROGRAMMING MODEL
Numerical Bases Used in Programming

◼ Hexadecimal

◼ Binary

◼ BCD

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 ADDRESSING MODES

 Register addressing Mode

 Immediate Addressing Mode
 Direct Addressing Mode
 In Direct Addressing Mode
 Indexed Addressing Mode
 Register Specific Addressing mode

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ADDRESSING MODES

Register Addressing Mode

MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6

MOV DPTR, A
MOV Rm, Rn

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ADDRESSING MODES

Immediate Addressing Mode

MOV A,#65H

MOV R6,#65H

MOV DPTR,#2343H

MOV P1,#65H

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ADDRESSING MODES

Direct Addressing Mode.. contd

Although the entire of 128 bytes of RAM can be

accessed using direct addressing mode, it is most often
used to access RAM loc. 30 – 7FH.

MOV R0, 40H

MOV 56H, A
MOV A, 4 ; ≡ MOV A, R4
MOV 6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !

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ADDRESSING MODES
Direct Addressing Mode.. contd
SETB bit ; bit=1
CLR bit ; bit=0

SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR =1
SETB 05 ;set high D5 of RAM loc. 20h
Note:
CLR instruction is as same as SETB
i.e.:
CLR C ;CY=0 (CY flag)

But following instruction is only for Clearing A register:

CLR A ;A=0

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ADDRESSING MODES
Direct Addressing Mode.. contd

DEC byte ;byte=byte-1

INC byte ;byte=byte+1

INC R7
DEC A
DEC 40H ; [40]=[40]-1

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ADDRESSING MODES

Indirect Addressing Mode

MOV A, @R0
MOVX @DPTR, A

Indexed Addressing Mode

MOVC A, @A+PC
MOVX A, @A+DPTR,

Register Specific Addressing Mode

DA A
MUL AB
SWAP A

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 INSTRUCTIONS

Data Transfer

Arithmetic

Logical — Byte level/Bit level

Program Control

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PROGRAM CONTROL /BRANCH INSTRUCTIONS

Conditional Jumps
JZ addr Jump if A=0
JNZ addr Jump if A≠ 0
DJNZ Reg, addr Decrement and jump if Reg ≠0
CJNE A,byte,addr Jump if A≠ byte
CJNE reg, #data, Jump if byte ≠ #data
addr
JC addr Jump if CY=1
JNC addr Jump if CY=0
JB bit, addr Jump if bit=1
JNB bit, addr Jump if bit=0
JBC bit, addr Jump if bit=1 and clear bit

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CALL INSTRUCTIONS

ACALL addr for within +/- 2k range

LCALL addr for within +/- 64k range

RET - Subroutine return

RETI - Interrupt Subroutine Return
(ISR)
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 TIMERS/COUNTERS

Up counting
16 bit counters (can be configured as 13 bit or 8 bit also)

Count registers Address

TH0 8Ch

TL0 8Ah

TH1 8Dh

TL1 8Bh

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 Timers/ Counters

Steps To enable counting:

✓ Set Gate bit =1
✓ Ensure that INT0 and INT1 pins are at 1
✓ Configure Mode suitably
✓ Load Count properly
✓ Set TR1/TR0 bit (to initiate counting)

Now….The counter counts according to core clock or

T1/T0 clock depending on C/T ’

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 TCON REGISTER: (88H IS THE ADDRESS)

 TF1: Timer 1 overflow flag.

 TR1: Timer 1 run control bit.
 TF0: Timer 0 over flowflag.
 TR0: Timer 0 run control bit.
 IE1: External interrupt 1 Edge flag.
 IT1: External interrupt 1 Type flag.
(1- for -ve edge , 0- for low level types)
 IE0: External interrupt 0 Edge flag.
 IT0: External interrupt 0 Type flag.
(1 - for -ve edge , 0- for low level types)

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 TMOD REGISTER: (ADDRESS 89H)

 Gate : When set, timer only runs while INT(0,1) is high.

 C/T’ : Counter/Timer select bit.
 M1 : Mode bit 1.
 M0 : Mode bit 0.

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MODES OF TIMER/COUNTER - M1,M0 BITS OF TMOD REGISTER

Count Address
registers
TH0 8Ch
TL0 8Ah
TH1 8Dh
TL1 8Bh

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 INTERRUPT :

Interrupt
service
routine

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 INTERRUPT ENABLE REGISTER : (ADDRESS 0ABH)

 EA : Global enable/disable.
 --- : Undefined.
 ET2 :Enable Timer 2 interrupt.(in 8052/ reserved in 8051)
 ES :Enable Serial port interrupt.
 ET1 :Enable Timer 1 interrupt.
 EX1 :Enable External 1 interrupt.
 ET0 : Enable Timer 0 interrupt.
 EX0 : Enable External 0 interrupt.

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 INTERRUPT PRIORITY REGISTER : (ADDRESS 0B8H)
For Software selection of priority
- - - Ps PT1 Px1 PT0 Px0

 PS :Priority set bit for Serial port interrupt.

 PT1 : Priority set bit for Timer 1 interrupt.
 PX1 : Priority set bit for External 1 interrupt.
 PT0 : Priority set bit for Timer 0 interrupt.
 PX0 : Priority set bit for External 0 interrupt.

Note: Hard wired priority incase two interrupts with same s/w priority occurs is
Ps <PT1 <Px1 <PT0 <Px0

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 VECTOR ADDRESS OF INTERRUPTS:

INT0 0003h

INT1 0013h

Timer 0 overflow 000Bh

Timer 1 overflow 001Bh

Serial port 0023h

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 Q&A

Thank You

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