SEQUENTIAL Logic Circuits Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits. Moreover, in a combinational circuit, the output appears immediately for a change in input, except for the propagation delay through circuit gates. On the other hand, the logic circuits whose outputs at any instant of time depend on the present inputs as well as ‘on the past outputs are called sequential circuits. In sequential circuits, the output signals are fed back to the input side. A block diagram of a sequential circuit is shown in Figure below:= Inputs It consists of a combinational cireuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing binary information. The binary information stored in these elements at any given time defines the state of the sequential circuit at that time. The sequential circuit receives binary information from external inputs that, together with the present state of the storage elements, determine the binary value of the outputs. These extemal inputs also determine the condition for changing the state in the storage elements. The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also of the present state of the storage elements. The next state of the storage elements is also a function of external inputs and the present state. Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states. ‘There are two types of sequential circuits, and their classification is a function of the timing of their signals. Asynchronous sequential circuit: ‘A sequential circuit whose behavior depends upon the sequence in which the input signals change is referred to as an asynchronous sequential circuit. The output will be affected whenever the input changes. The commonly used memory elements in these circuits are time-delay devices. There is no need to wait for a clock pulse. ‘Therefore, in general, asynchronous circuits are faster than synchronous sequential circuits. However, in an asynchronous circuit, events are allowed to occur without any synchronization. And in such a case, the system becomes unstable. Since the designs of asynchronous circuits are more tedious and difficult, their uses are rather limited, The memory elements used in sequential circuits are flip-flops which are capable of storing binary information. Synchronous sequential circuit: ‘A sequential circuit whose behavior can be defined from the knowledge of its signal at discrete instants of time is referred to as a syachronous sequential circuit, In these systems, the memory elements are affected only at discrete instants of time. ‘The synchronization is achieved by a timing device known as a system clock, which generates a periodic train of lock pulses. The outputs are affected only with the application of a clock pulse. Inputs ——> Outputs Clock pulses ——— {a) Block diagram PLIJLJItJ1wy () Timing diagram of clock pulses Synchronous clocked sequential circult The storage elements (memory) used in clocked sequential circuits are called flipflops22:51 SEQUENTIAL LOGIC CIRCUITS Logic circuits may be classified into two categories. One is the combinational logic circuit which we have already described in details comprising different gates. The other one is the sequential logic circuit characterised by the ability to remember. They are said to possess ‘memory’, Such 7 device is called flip-flop. Hence the main difference between a gate and a flip-flop is that in gate the output changes wherever inputs are changed but in case of flip-flop the output will remain unchanged even if there is change in input once it has been set. The block diagram of a sequential circuit is shown Combinational circuit Inputs in fig. (22-77). Flip-flop are basically a part of the multivibrator family and generally bistable multivibrator is referred to as a flip-flop. Monostable multivibrator and Schmitt- trigger which are the other members of multivibrator family find applications as registers and counters. Fig. 22:77 22.52 FLIP-FLOP A flip-flop or bistable multivibrator has two stable states and can stay in one of the two possible states after an input has been applied. Since, the state does not change following the removal of the input, the flip-flop is a 1-bit memory or storage device as it can store either a logical '0' or a logical 1’. There are many types of flip-flop circuits such as RS flip-flop, clocked RS flip-flop, D flip-flop. JK flip-flop etc. RS flip-flop is the simplest and most basic of them all. We shall now discuss RS flip-flop and clocked RS flip-flop. 22-52-1 RS FLIP FLOP The symbol of a RS flip-flop is shown in fig. (22:78). There are two inputs to the flip-flop called Ss (set) and R (reset)..There are two outputs denoted by Q and Q. Here, one should remember that regardless of the value of Q its component is Q, RS flip-flop can bewry . 22-69 jructed by using two 2-input NOR con flop has also been given. sip” t ae Bate as shown in fig. (22-79). The truth-table of a RS R ‘> Q ww No change in last value oo 1 Get) ) > +2 0 (Reset) Not defined Fig. 22-79 ae aready know ome at any input of NOR gate forces its output to a logic 0. ence, S =0, ip- “Hi pula : P : ee 'p-flop will simply remain in its present state i.e. Q will remain Case-2. When R = 0 and S = 1, the output of NOR gate B i gate A become low, therefore Q = 1. Since Q=1 when S — tot aca fothes bene Set. Case-3. When R = 1 and S =0, the output of NOR gate A is low, i.e., Q = 0. Therefore, in this case, the signals at both input of gate A are high and signals of both inputs of gate B are: low. This a due to the fact that Q = 0 and Q = 1. This is another stable condition of flip-flop. We say that flip flop has been reset. Case-4. R = 1 and S = 1 is forbidden because this would mean Q = 0 and Q = 0 which is not possible. Hence this condition should never be imposed on RS flip-flop. But, if by mistake sucha situation arises, the output is not well defined as it can be a zero or a one. 22:52-2 CLOCKED RS FLIP-FLOP The basic RS flip-flop does not operate in step with a clock or timing device. When an input is set, the output is immediately activated just as it happens in case of combinational logic circuits i., this operates asynchronously. If we want that state of flip-flop should change only when a clock pulse is applied so that we can time at our will the change of state of the flip-flop, then clocked RS flip-flop is used. A RS flip-flop can be converted into a clocked RS flip-flop by using additional NAND/AND gates and providing a clock input. A clocked RS flip-flop operates in step with the clock or timing device. Thus, R Q it operates synchronously. Figure (22-80) shows the clocked RS flip-flop with sas a clocked (CLK) input (square wave). Oise » When the input signal labelled as CLK (clock Pulse) is low (0), both AND gates ai disable. In this case, the output is latched or remains in the last state s it was in or no change takes place regardless of the Fig. 22:80 Closed Rs flip-flop Conditions of R and S$ inputs. . When the clock input is high (1), both AND gates are enabled and R and S$ input can reach to the flip-flop. When clock input is high, the flip-flop will set ifR = QandS = 1. Further, when clock input is high and R = 1andS = 0, the flip-flop will reset. The truth table of clocked RS flip-flop is shown on next page. ol0 0 0 0 1 i 1 1 ee Oo Oo YY KF OC SDJK Flip-Flop: JK means Jack Kilby, Texas Instrument (TI) Engineer, who invented IC in 1958. JK Flip-Flop has two inputs J(set) and K(reset). A JK Flip-Flop can be obtained from the clocked SR Flip-Flop by augmenting two AND gates as shown below. cLK Fig : 3.15 -JK Flip Flop The data input J and the output Q’ are applied o the first AND gate and its output (J’) is applied to the S input of SR Flip-Flop. Similarly, the data input K and the output Q are applied to the second AND gate and its output (KQ) is applied to the R input of SR Flip-Flop. 4) Using SR Mipflop () Graphic symbol Fig : 3.16 — JK Flipflop using SR Flipflop Je K=O ), both AND gates are disabled. Therefore clock pulse have no effect, hence the Flip-Flop output is same as the previous output. J=0,K=1 When J= 0 and K= , AND gate 1 is disabled i.e., S= 0 and R= 1. This condition will reset the Flip-Flop to 0. J=1,K=0 When J= 1 and K= 0, AND gate 2 is disabled i.e., S= 1 and R= 0. Therefore the Flip-Flop will set on the application of a clock pulse. J=K=0 When J=K= 1, it is possible to set or reset the Flip-Flop. If Q is High, AND gate 2 passes on a reset pulse to the next clock. When Q is low, AND gate 1 passes on a set pulse to the next clock. Eitherway, Q changes to the complement of the last state ie., toggle. Toggle means to switch to the opposite state. The truth table of JK Flip-Flop is given below. CLK] Inputs | Output ‘State J] KY Qner 1/0) o0/] an No Change afofia 0 Reset1 1 1 Qu’ Toggle Fig : 3.17 - Input and output waveforms of JK Flip-Flop Characteristic table and Characteristic equation: The characteristic table for JK Flip-Flop is shown in the table below. From the table, K-map for the next state transition (Q,..) can be drawn and the simplified logic expression which represents the characteristic equation of JK Flip-Flop can be found. nti roo rR ROOF FRO Of & ror PPP ROCOCOoO°S kr oF OF OF Ol & » oO Characteristic table K-map Simplification: Characteristic equation: Q,.:= JQ’+ K’Q.Race-around condition of a J-K Flip-flop The inherent difficulty of an S-R flip-flop (i.e., S = R = 1) is eliminateq by usin feedback connections from the outputs to the inputs of gate 1 and gate 2 as discusseq = the flip-flop. Truth tables of JK flip-flop were formed with the assumption that the inputs do p change during the clock pulse (CLK = 1). But the consideration is not true because of ‘ feedback connections. Consider, for example, that the inputs are J = K = 1 and Q = baad pulse as shown in Fig. 7.19 is applied at the clock input. Trailing or Negative Edge Leading or Positive Edge —| a | ee 2 FIG. 7.19. Input clock pulse After a time interval At equal to the propagation delay through two NAND gates in series, the outputs will change to Q = 0. So now we have J = K = 1 and Q = 0. After another time interval of At the output will change back to Q = 1. Hence, we conclude that for the time duration of t, of the clock pulse, the output will oscillate between 0 and 1. Hence, at the end of the clock pulse, the value of the output is not certain. This situation is referred to as a race around condition.The initial state of the flip- lop can be assigned by addition of two inputs namely preset and clear. Pr Clear(Cr) (e) Fig. 3.7(e) : Logic circuit of J-K flip-flop. The initial state of the flip-flop can be assigned by addition of two inputs namely preset and clear as shown in Fig. 3.7(e) allows the initial state of the flip-flop to be assigned. The flip-flop can be cleared by setting C,=0, P=1, C,=0, as the output of gate 2 becomes | and the flip-flop can be preset with P=0, C=1, C,=0. The FF can be enabled with P=1, C=1. 92 Sequential Circuit These inputs are called asynchronous inputs, and are not in synchronism with the clock and may be applied any time in between clock pulses.JK Flip-Flop Truth Table The JK Flip-Flop truth table has the hold state, reset state, set state, and toggle state. As this is a refinement of SR flip flop, the truth table of SR flip flop is refined to make the truth table of jk flip flop. The truth table of the JK Flip-Flop has two inputs, J and K, Q, denotes the current state and Qy+4 denotes the next state in the table given below: