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ARM Module 4

The document provides an overview of the memory system features of the Cortex-M3, including memory maps, access attributes, and bit-band operations. It details the different bus interfaces and memory regions, highlighting attributes such as bufferable, cacheable, and executable memory. Additionally, it explains the advantages of bit-band operations for efficient data manipulation.

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6 views22 pages

ARM Module 4

The document provides an overview of the memory system features of the Cortex-M3, including memory maps, access attributes, and bit-band operations. It details the different bus interfaces and memory regions, highlighting attributes such as bufferable, cacheable, and executable memory. Additionally, it explains the advantages of bit-band operations for efficient data manipulation.

Uploaded by

manjunathvb18
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 4

• Memory System Features Overview


• Memory Maps
• Memory Access Attributes
• Bit-Band Operations
• The Pipeline
• A Detailed Block Diagram
• Bus Interfaces on the Cortex-M3: The I-Code Bus, The D-Code Bus,
The System Bus, The External PPB, The DAP Bus
Detailed Block Diagram
Memory System Features Overview
• Predefined memory map that specifies which bus interface is to be used when a
memory location is accessed.
• This feature also allows the processor design to optimize the access behavior when
different devices are accessed.
• Bit band support is another feature: This provides atomic operations to bit data in
memory or peripherals. The bit-band operations are supported only in special
memory regions.
• The Cortex-M3 memory system also supports unaligned transfers and exclusive
accesses.
Memory Maps
Cortex M3 has fixed memory map

Debugging Components are:


1. Fetch Patch and Breakpoint Unit (FPB)
2. Data Watchpoint and Trace Unit (DWT)
3. Instrumentation Trace Macrocell (ITM)
4. Embedded Trace Macrocell (ETM)
5. Trace Port Interface Unit (TPIU)
6. ROM table

Cortext M3 has 4GB of memory region


Program memory can be located in
• Code region
• SRAM region
• External RAM region

In code region, the instruction fetches and data


accesses are carried out simultaneously on two separate
bus interfaces.
• SRAM, Peripheral- System Memory Bus
• Bit band- only to data access
• AHB- Advanced high Performance Bus
• NVIC, FPB, DWT, ITM
• APB- Advanced Peripheral Bus
• NVIC- SCS(System Control Space)
System Control Space
Memory Access Attributes
• Bufferable:
• Write to memory can be carried out by a write buffer while the processor continues
on next instruction execution.
• Cacheable:
• Data obtained from memory read can be copied to a memory cache so that next
time it is accessed the value can be obtained from the cache to speed up the
program execution.
• Executable:
• The processor can fetch and execute program code from this memory region.
• Sharable:
• Data in this memory region could be shared by multiple bus masters. Memory
system needs to ensure coherency of data between different bus masters in
shareable memory region.
• Code memory region (0x00000000–0x1FFFFFFF):
WT(Write Through) – Bufferable
• SRAM memory region (0x20000000–0x3FFFFFFF):
Write transfers to this region are bufferable, and the cache attribute is write
back, write allocated (WB-WA).
• Peripheral region (0x40000000–0x5FFFFFFF):
The accesses are noncacheable, cannot execute instruction code in this region
• External RAM region (0x60000000–0x7FFFFFFF):The accesses are cacheable (WB-WA),
• External RAM region (0x80000000–0x9FFFFFFF): The accesses are cacheable (WT)
• External devices (0xA0000000–0xDFFFFFFF): needs ordering/nonbuffered accesses. It is
also a nonexecutable region.
• System region (0xE0000000–0xFFFFFFFF):This region is for private peripherals and
vendor-specific devices. It is nonexecutable.
Bit-Band Operations
• Bit-band operation support allows a single load/store operation to
access (read/write) to a single data bit.
• 2 bit band regions: first 1MB of SRAM and first 1MB of
Peripheral
• Can be accessed normally or bit band alias
• Instead of read, modify, write can be executed in single
instruction
• The terms for the bit-band memory addresses:
• Bit-band region: This is a memory address region that
supports bit-band operation.
• Bit-band alias: Access to the bit-band alias will cause an
access (a bit-band operation) to the bit-band region.
Advantages – Bit Band
• To simplify branch decisions
• if a branch should be carried out based on 1 single bit in a status register in a
peripheral, instead of
• Reading the whole register
• Masking the unwanted bits
• Comparing and branching
• Reading the status bit via the bit-band alias (get 0 or 1)
• Comparing and branching
Pipeline
Detailed Block Diagram
Detailed Block Diagram
Bus Interfaces on the Cortex M3
• I Code Bus : fetches in memory regions from 0x00000000 to 0x1FFFFFFF.
• D Code Bus; data access in memory regions from 0x00000000 to 0x1FFFFFFF.
• System Bus: for instruction fetch and data access in memory regions from 0x20000000 to
0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF. Similar to the D-Code bus, all the transfers on the system
bus are aligned.

• External PPB: for private peripheral accesses in memory regions 0xE0040000 to 0xE00FFFFF.
• DAP Bus

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