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The Switched Mode Power Amplifiers

Chapter · March 2010

DOI: 10.5772/8745 · Source: InTech

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The Switched Mode Power Amplifiers 359

18
x

The Switched Mode Power Amplifiers

Elisa Cipriani, Paolo Colantonio, Franco Giannini and Rocco Giofrè
University of Roma Tor Vergata
Italy

1. Introduction
The power amplifier (PA) is a key element in transmitter systems, aimed to increase the
power level of the signal at its input up to a predefined level required for the transmission
purposes. The PA’s features are mainly related to the absolute output power levels
achievable, together with highest efficiency and linearity behaviour.
From the energetic point of view a PA acts as a device converting supplied dc power (Pdc)
into microwave power (Pout). Therefore, it is obvious that highest efficiency levels become
mandatory to reduce such dc power consumption. On the other hand, a linear behaviour is
clearly necessary to avoid the corruption of the transmitted signal information.
Unfortunately, efficiency and linearity are contrasting requirements, forcing the designer to
a suitable trade-off.
In general, the design of a PA is related to the operating frequency and application
requirements, as well as to the available device technology, often resulting in an exciting
challenge for PA designers, since not an unique approach is available.
In fact, PAs are employed in a broad range of systems, whose differences are typically
reflected back into the technologies adopted for PAs active modules realisation. Moreover,
from the designer perspective, to improve PAs efficiency the active devices employed are
usually driven into saturation. It implies that a PA has to be considered a non-linear system
component, thus requiring dedicated non linear design methodologies to attain the highest
available performance.
Nevertheless, for high frequency applications it is possible to identify two main classes of
PA design methodologies: the trans-conductance based amplifiers with Harmonic Tuning
terminations (HT) (Colantonio et al., 2009) or the Switching-Mode (SM) amplifiers
(Grebennikov & Sokal, 2007; Krauss et al., 1980). In the former, the active device acts as a
nonlinear current source controlled by the input signal (voltage or current for FET or BJT
devices respectively). A simplest schematic view of such an amplifier for FET is reported in
Fig. 1a. Under this assumption, the high efficiency condition is achieved exploiting the
device nonlinear behaviour through a suitable selection of both input and output harmonic
terminations. More in general, the trans-conductance based amplifiers are identified also as
Class A, AB, B to C considering the quiescent active device bias points, resulting in different
output current conduction angles from 2 to 0 respectively.
The most famous solution of HT PA is the Class F approach (Gao, 2006; Colantonio et al,
2009), while for high frequency applications and taking into account practical limitations on
 Advanced Microwave and Millimeter Wave
360 Technologies: Semiconductor Devices, Circuits and Systems

the control of harmonic impedances, several solutions have been successfully proposed
(Colantonio et al., 2003).
Conversely, in the SM PA, the active device is driven by a very large input signal to act as a
ON/OFF switch with the aim to maximise the conversion efficiency reducing the power
dissipated in the active devices also. A schematic representation of a SM amplifier is
depicted in Fig. 1b. When the active device is turned on, the voltage across its terminals is
close to zero and high current is flowing through it. Therefore, in this part of the period the
transistor acts as a very low resistance, ideally short circuit (switch closed) minimising the
overlap between the current and voltage waveforms. In the other part of the period, the
active device is turned off acting as an open circuit. Therefore, the current is theoretically
zero while high voltage is present at the device terminals, once again minimising the
overlap between voltage and current waveforms. If the active device shows a zero on
resistance and an infinite off resistance, a 100% efficiency is theoretically achieved. The latter
is of course an advantage over Class A or B, where the maximum theoretical efficiencies are
50 % and 78 % respectively. On the other hand, Class C could achieve high efficiency levels,
despite a significant reduction in the maximum output power level achievable (theoretically
100% of efficiency for zero output power). Nevertheless, the HT PAs are intrinsically able to
amplify the input signal with higher fidelity, since the active device is basically represented
by a controlled current source (FET case) whose output current is directly related to the
input voltage. Instead, in SM PAs the active device is assumed to be ideally driven in the
ON and OFF states, thus exhibiting a higher nonlinear behaviour. However, this
characteristic does not represent a trouble when signals with constant-envelope modulation
are adopted.
On the basis of their operating principle, SM amplifiers are often considered as DC to RF
converter rather than RF amplifiers.

VDD VDD

LRFC LRFC

Output Output
Matching iDS Resonator
Input iDS Input
Matching Matching vDS
RL RL

HT PA SM PA
Fig. 1. Simplified view of a simple single ended HT (left) and SM (right) PA.

Different SM PA classes of operation have been proposed over the years, namely Class D, S,
J, F-1 (Cripps, 2002; Kazimierczuk, 2008), while the most famous and adopted is the Class E
PA (Sokal & Sokal, 1975; Sokal, 2001) that will be described in deep detail in the following.
As will be shown, these classes are based on the same operating principle while their main
differences are related to their circuit implementation and current-voltage wave shaping
only.
The applications of SM PAs principles have initially been limited to amplifiers at lower
frequencies in the megahertz range, due to the active device and package parasitics
practically limiting the operating frequencies (Kazimierczuk, 2008). They have also been
The Switched Mode Power Amplifiers 361

applied to DC/DC power converters that also operate at lower switch frequencies (Jozwik &
Kazimierczuk, 1990; Kazimierczuk & Jozwik, 1990). Recently, their principles of operation
have been extended and applied to RF and microwave amplifier design, made possible by
the high-performance active devices nowadays available based on silicon (Si), gallium
arsenide (GaAs), silicon germanium (SiGe), silicon carbide (SiC), and gallium nitride (GaN)
technologies (Lai, 2009).

2. Switching mode generic operating principle

The operating principle of every SM PA is based on the idea that the active device operates
in saturation, thus it can be represented as a switch and either voltage or current waveforms
across it are alternatively minimized to reduce overlap, so minimizing power dissipation in
the device itself. If the transistor is an ideal switch, a 100% of efficiency can be achieved by
the proper design of the output matching network. As reported in Fig. 1b, the output
resonator can be assumed, in the simplest way, as an ideal L-C series resonator at
fundamental frequency, terminated on a series load resistance (RL). The role of the resonator
is to shape the voltage and current waveforms across the switch in order to avoid power
dissipation at higher harmonics. In fact, an ideal L-C series resonator shows zero impedance
at resonating frequency (0=(LC)-1/2) and infinite impedance for every ω≠ω0. It follows that
fundamental current only is flowing into the output load and fundamental voltage only is
generated at its terminals. Consequently, 100% of efficiency is obtained (being zeroed the
overlap between voltage and current waveforms over the transistor, thus being nulled the
power dissipated in it) and no power is delivered at harmonic frequencies in the load, being
the latter not allowed to flow into the load RL.
In actual cases, several losses mechanisms, such as ohmic and capacitive discharge or
leakage, cause an unavoidable overlapping between the voltage and current waveforms,
together with power dissipation at higher harmonics, thus limiting the maximum achievable
efficiency levels.
The most relevant losses in SM PA are represented by:
 parasitic capacitors, such as the device drain to source capacitance Cds. The
presence of such capacitance causes a low pass filter behaviour at the output of the
active device, affecting the voltage wave shaping with a consequent degradation
in the attainable power and efficiency levels. In fact, considering the active device
as the parallel connection of a perfect switch and the parasitic capacitance Cds, the
higher voltage harmonics are practically shorted by Cds and only few harmonics
can be reasonably controlled by the loading network.
 parasitic resistance, such as the drain-to-source resistance when the transistor is
conducting RON (ON state). In fact, due to the non zero resistance when the switch
is closed, a relevant amount of active power will be dissipated in the transistor
causing a lowering in the achievable efficiency.
 non-zero transition time, due to the presence of parasitic effects, which increase the
voltage and current overlap.
 implementation losses due to the components (distributed or lumped elements)
employed to realise the required input and output matching networks.
 Advanced Microwave and Millimeter Wave
362 Technologies: Semiconductor Devices, Circuits and Systems

The entity of the parasitic components as well as the associated losses are strictly related to
the characteristics of the active device used, especially when designing RF PA
(Kazimierczuk, 2008; Lai, 2008).

3. The Class E Amplifier

Firstly presented in the early 70’s in (Sokal & Sokal, 1975), the Class E power amplifier
recently received more attention by microwave engineers with the growing demand of high
efficient transmitters in wireless communication systems.
It has been widely adopted in constant envelope based communication systems, but
represents a valid alternative if combined with envelope varying technique also, like
envelope elimination and restoration or Chireix’s outphasing technique (Cripps, 2002).
A complete analysis of the Class E amplifier is herein presented, making the assumption of a
very idealized active device switching action. The topology considered is the most common
one, firstly presented in (Sokal & Sokal, 1975), although different Class E topologies have
been conceived and studied during the past (Mader et al., 1998; Grebennikov, 2003;
Suetsugu & Kazimierczuk, 2005). In order to clarify Class E operation, a real device-based
design is also briefly presented.

3.1 Analysis with a generic duty cycle

The basic topology of a single ended Class E power amplifier is depicted in Fig. 2. The active
device is schematically represented as an ideal switch and it is shunted by the capacitance
C1, which include the output equivalent capacitance of the active device also. The output
network is composed by an ideal filter C0-L0 with a series R-L impedance.

OFF ON

1,0 1,0
VDD
0,8 0,8
IDC
Lchoke
0,6 0,6
iSW / IMax
vc / VMax

L0 L
iD
0,4 0,4
+ C0
isw
vC iout R 0,2 0,2
C1
- 0,0 0,0

Z1 ZE 0 I  V 2
 (rad)

(a) (b)
Fig. 2. Basic topology of a Class E amplifier (a) corresponding ideal waveforms (b).

Such a circuit is usually analyzed in time domain, which is a straightforward but tedious
process, requiring the solution of non linear differential equations. Anyway, some
hypotheses can be adopted to carry out a simplified analysis useful to understand the
underling operating principle.
Considering the series resonator C0-L0 to behave as an ideal filter, i.e. with an infinite (or
high enough) Q factor, harmonics and all frequency components different from the
fundamental frequency can be considered as filtered out and do not play any role in the
The Switched Mode Power Amplifiers 363

solution of the system. As a consequence, the current flowing into the output branch of the
circuit can be assumed as a pure sinusoidal, with its own amplitude IM and its phase 
(Raab, 2001):

iout  I M  sin     (1)

Where =t.
Consequently, from Kirchhoff laws the current iD (see Fig. 2), which flows entirely through
the switch during the ON period (iSW) or entirely through the capacitance C1 during the OFF
period, can be written as:

iD  I DC  I M  sin     (2)

Assuming for simplicity a 50% of duty cycle (the analysis for a generic duty cycle is
available in (Suetsugu & Kazimierczuk, 2007)), the current flowing into the switch iSW can be
expressed as:

0, 0    
isw     (3)
 I DC  I M  sin     ,     2

And analogously the current in the capacitor C1 becomes:

 I  I M  sin     , 0    
iC     DC (4)
0,     2

While the voltage across the capacitance vC can be easily inferred by integration of (4),
resulting in the following expression:

 1

vC       C1
 
 I DC  I M  cos      I M  cos   , 0    
(5)
0,     2


The resulting theoretical current and voltage waveforms are depicted in Fig. 2b.
It can be noted that current and voltage across the switch do not overlap, thus no power
dissipation exists on the active device. The unique dissipative element in the circuit is the
loading resistance R, which is active at fundamental frequency only. Then, from these
assumption it follows that the DC to RF power conversion happens without losses and the
theoretical efficiency is 100%.
The quantities IDC, IM and  have still to be determined as functions of maximum current and
voltage allowed by the adopted active device, IMax and VMax respectively, and of operating
angular frequency .
For this purpose, it has to note that the capacitance C1 should be completely discharged at
the switching turn on, which implies that the voltage vC has to be null in correspondence of
the instant  (see Fig. 2b):
 Advanced Microwave and Millimeter Wave
364 Technologies: Semiconductor Devices, Circuits and Systems

vC   0 (6)
 

Such condition is usually referred as Zero Voltage Switching (ZVS) condition, which implies
that the capacitance C1 should not be short circuited by the switch turn on when its voltage
is still high (Sokal & Sokal, 1975).
The second condition, namely Zero Voltage Derivative Switching (ZVDS) condition, or soft-
switching condition, implies that the current starts to flow from zero after the switch turn on
and then increases gradually, in order to prevent worsening in circuit performance due to
mistuning of the waveforms (Sokal & Sokal, 1975). This condition is written as:

d
iC    vC   0 (7)
  d  

Substituting (4) in the previous equations, from (6) it follows:

I DC    2  I M cos    0 (8)

While from (7) it follows:

I DC  I M  sin    0 (9)

Thus the following relationships can be inferred:

2
tan     (10)


I DC 2
  sin     cos   (11)
IM 

The maximum current flowing into the switch is given by:

I Max  I DC  I M (12)

And it occurs in correspondence of the angle

3
I     (13)
2

Similarly, for the voltage across the switch its maximum value occurs in correspondence of
the angle V (see Fig. 2b), which can be inferred nulling the derivate of vc given by (5).
Thus, accounting for (11), it follows:

V  2   (14)

and
The Switched Mode Power Amplifiers 365

I DC
VMax  2    (15)
C1

However, the value of the capacitance C1 is still an unknown variable. It appears in the
definition of the voltage waveform, and it is convenient to use voltage constraints in order to
obtain its expression. In fact, its average value must be equal to the supplied DC voltage
VDD; thus it follows:

1 
VDD 
2 0
vC   d (16)

Which solved lead to:

1 1  2 
VDD     I DC   2  I M sin    I M    cos    (17)
2   C1  2 


from which the value of C1 can be finally determined remembering (11)

I DC
C1  (18)
    VDD

This also suggests a simple relationship between DC current and bias voltage.
At this point, waveforms in Fig. 2b have been completely determined in the time domain,
without recurring to the frequency domain. However, the remaining elements of the circuit,
DC power, output power and output impedance have still to be determined.
As stated before, all the DC power is converted to RF power and dissipated into the load
resistance at fundamental frequency:

1
PDC  I DC  VDD   I M  VM  PRF (19)
2

where VM is the amplitude of fundamental component of the voltage across R which can be
obtained by (19) and replacing (11):

VDD  I DC
VM  2   2  VDD  sin   (20)
IM

The value of the resistance R is simply obtained as the ratio between VM and IM:

VM V 2
R  2  DD  sin   (21)
IM I DC

Clearly, if a standard 50 Ohm termination is required, an impedance transformer is

necessary to adapt such load to the required R value.
Finally, the inductance L is computed taking into account that its reactive energy is
exchanged, at every cycle, with the capacitance C1. Thus it follows:
 Advanced Microwave and Millimeter Wave
366 Technologies: Semiconductor Devices, Circuits and Systems

1 1  2 1

 I DC  I M  sin      d     L  I M 2
2   C1 0  2
(22)

where the expression in the integral represents the voltage across the capacitance C1 during
the OFF period. The value for the inductance L is therefore given by:

1  4 2
L    cos    (23)
  C1  2  

Alternatively, R and L can be found by calculation off in-phase and quadrature voltage
components, as elsewhere reported (Mader et al., 1998; Cripps, 1999).
The series impedance R-L can be put together in order to obtain a more compact and useful
expression for the output branch impedance (Mader et al., 1998) normalized to the shunt
capacitance C1:

0.28
ZE   e j 49 (24)
C1

With reference to Fig. 2, the impedance Z1 seen by the ideal switch is obtained by the shunt
connection of the capacitance C1 and ZE and is herein given in its simplified formulation
(Colantonio et al., 2005):

0.35
Z1   e j 36 (25)
C1

Remaining reactive components, L0 and C0, are easily calculated by means of:

1
2  (26)
L0  C0

Provided a high enough Q factor, the values of L0 and C0 are non uniquely defined and any
pair of resonant element can be used.
The analysis performed here was intended for the most common case of 50% duty cycle (i.e.
 conduction angle). In this case the relations are greatly simplified thanks to the properties
of trigonometric functions. However, Class E approach is possible for any value of duty
cycle: a detailed analysis can be found in (Suetsugu & Kazimierczuk, 2007; Colantonio et al.,
2009) where all electrical properties and component values are evaluated as a function of
duty cycle. It can be demonstrated that under ideal assumption the maximum output power
does not occur in correspondence of a 0.5 duty cycle, but for a slightly higher value (0.511).
Anyway, in terms of output power capability, this increment is extremely low (about 1‰)
and a standard 0.5 duty cycle could be assumed in the design, unless differently required.

3.2 A Class E design example

In order to illustrate the application of the relations obtained in the analysis, a simple Class
E design example is described, based on an actual active device, specifically a GaAs pHEMT.
The Switched Mode Power Amplifiers 367

The device exhibits a breakdown voltage of about 25 V and a maximum output current of
400 mA. From S-parameter simulation, an output capacitance of 0.35pF results at 2.5 GHz,
the selected operating frequency. Considering this capacitance as the minimum value for the
shunt capacitance C1, the network elements can be easily calculated through the previous
relationships.
From (20) and taking into account the maximum voltage, the bias voltage is set to VDD=6V.
Hence, from the inversion of (18), the DC component of drain current is determined,
resulting in IDC=105 mA.
At this point, using (21) and (23) or, alternatively, equation (24), the values of output
matching network are R=33 and L=1.67 nH. If considering a standard output impedance of
50, a transforming stage is necessary.

Fig. 3. Schematic of a 2.5GHz GaAs HEMT Class E amplifier.

Standing the value of optimum load, the impedance matching can be easily accomplished by
a single L-C cell. A series inductance - parallel capacitance configuration has been chosen.
Lumped elements for the filtering output network have then determined, selecting an
inductance L0=6nH and a resulting capacitance C0=0.68pF. The complete amplifier schematic
is depicted in Fig. 3, while the simulated output power, gain and efficiency versus input
power are shown in Fig. 4.

28 100
26
90
24
Outèut power (dBm) and Gain (dB)

22 80

20 70
Drain Efficiency (%)

18
60
16
Class E region
14 50
12
40
10
8 30

6 Drain Efficiency 20
4 Output power
10
2 Gain
0 0
2 4 6 8 10 12 14 16 18 20
Input power (dBm)

Fig. 4. Simulated performance of the 2.5GHz Class E amplifier.

It is worth to notice that, under a continuous wave excitation, Class E behavior is achieved
only at a certain level of compression, i.e. when the large input sinusoidal waveform implies
a “square-shaping” effect on the output current, due to active device physical limits, thus
 Advanced Microwave and Millimeter Wave
368 Technologies: Semiconductor Devices, Circuits and Systems

approaching a switching behavior. The output current and voltage waveforms and load line
are reported in Fig. 5, showing a good agreement with the theoretical expected behavior
(compare with ideal waveforms depicted in Fig. 2b).
300 22 300

20
250 18 250

16
200 200
14

12
150 150
Ids (mA)

Ids (mA)
Vds (V)
10

8 ON-OFF
100 100
6

50 4
50
2 OFF-ON
0 0 0
-2
0.0 0.2 0.4 0.6 0.8 0 5 10 15 20
time (ns) Vds (V)

(a) (b)
Fig. 5. Output current and voltage waveforms (a) and load line (b) of the 2.5GHz Class E
amplifier.

3.3 Drawbacks
As already outlined, Class E power amplifiers have some practical limitations, mainly due to
their maximum operating frequency. Such limitations are partially related to the cut-off
frequency of the active device, while are mainly due to the circuit topology and switching
operation. In fact, as reported in (Mader et al., 1998), a Class E maximum frequency can be
approximated by:

I DS I Max
f Max  2
 (27)
2  C1  VDD 56.5  C1  VDD

Practically the lower limit of C1 is given by the active device output capacitance Cds.
Consequently, the value of maximum operating frequency strongly depends on the device
adopted for the design, on its size and then on the maximum current it can handle. For RF
and microwave devices, the maximum frequency in Class E operation is generally included
between hundred of megahertz (for MOS devices) and few gigahertz (for small MESFET or
pHEMT transistors).
Additionally, at microwave frequencies higher order voltage harmonic components can be
considered as practically shorted by the shunt capacitance, and the Class E behavior has to
be clearly approximated. In particular, the voltage wave shaping can be performed
recurring to the first harmonic components only (Raab, 2001; Mader et al., 1998), while the
ZVS and ZVDS conditions cannot be longer satisfied.
Truncating the ideal voltage Fourier series at the third component, the resulting waveform is
reported in Fig. 6, from which it can be noted the existence of negative values. Thus it
becomes mandatory to prevent such negative values of drain voltage to respect active device
physical constraint and safely operations.
The Switched Mode Power Amplifiers 369

1,0

0,8

Vds / Vmax
0,6

0,4

0,2

0,0

0 1 2 3 4 5 6

rad
Fig. 6. Three harmonics reconstructed voltage waveform

As pointed out in (Colantonio et al., 2005), two solutions can be adopted. Obviously it is
possible to increase drain bias voltage, but it would mean a non negligible increase in the
DC dissipated power that in turn causes a decrease in drain efficiency levels. In addition, an
increasing on peak voltage value could exceed breakdown limitations of the transistor. The
other solution is based on the assumption of unaffected current harmonic components, thus
optimizing the voltage fundamental component, while keeping fixed the other harmonics
imposed by the network topology (i.e. the filter L0-C0 behavior and the device capacitance
Cds) (Cipriani et al., 2008). The optimization process must be implemented in a numerical
form in order to reduce complexity and computing effort. The main goal is to avoid negative
voltage values on drain voltage and, at the same time, maximize output power, hence
efficiency. Then, for every value of frequency exceeding the maximum one, the optimum
high frequency fundamental impedance, Z1,HF, is optimized in magnitude and phase.

0.90 1.0
100
  0.9
0.85 95
0.8
drain efficiency (%)

0.80 90
0.7
rad


0.75 0.6 85
0.5
0.70 80
0.4
0.65 75
0.3

0.60 0.2 70
1 2 3 4 5 1 2 3 4 5
k k

(a) (b)
Fig. 7. Class E optimum load impedance (a) and ideal efficiency (b) as a function of k

Obtained results are expressed as normalized to ideal load impedance at maximum

frequency given by (27) and depicted in Fig. 7a as a function of normalized frequency
k=f/fMax, defined as the ratio between the assumed operating frequency f and the maximum
 Advanced Microwave and Millimeter Wave
370 Technologies: Semiconductor Devices, Circuits and Systems

allowed one fMax, defined in (27). The plot shown in Fig. 7a can be considered as a “design
chart” for high frequency Class E development, once the maximum frequency is known.
A quasi monotonic decrease of magnitude of fundamental impedance is observed, leading
to a reduced voltage fundamental component and a reduced output power. At the same
time, the phase decreases tending to almost purely resistive values. The related drain
efficiency is reported in Fig. 7b, showing an increasing reduction with respect the ideal 100%
value due to non ideal operating conditions.
A high frequency Class E PA example is shown in Fig. 8.

Fig. 8. A 2.14 GHz LDMOS Class E PA

The amplifier is designed using a medium power LDMOS transistor for base station
application at 2.14 GHz. Once the bias point, maximum current and output capacitance of
the transistor are fixed, the maximum frequency in Class E mode is directly derived.
Considering a maximum current of 2.5 A, a bias voltage of 20 V and an output capacitance
of 4.2 pF (estimated by S- parameters simulation), the maximum frequency in Class E results
in 520 MHz, far below the frequency chosen for the design. If operating at 520 MHz, the load
impedance would be Z1=25.1ej36°. At 2.14 GHz (4.1 times above fMax), the load impedance is
directly obtained by the design chart of Fig. 7a resulting in Z1,HF=17.5ej17°. Since a very
simple equivalent model of the device is used, as Fig. 2 shows, this impedance is seen at the
nonlinear current source terminals, so that eventual parasitic and package effects should be
considered as belonging to the output load.

60 4

50
3
40
V (V)

I (A)

30 2
ds

ds

20
1
10

0 0
0 ,0 0 ,2 0 ,4 0 ,6 0 ,8
tim e (n s e c )

Fig. 9. Simulated voltage and current drain waveform of the designed PA

Simulated drain current and voltage waveform are depicted in Fig. 9, with reference to the
internal nodes of the model. A good agreement with typical Class E waveform is
The Switched Mode Power Amplifiers 371

remarkable, above the maximum frequency, although the perfect switching behavior cannot
be satisfied.

45 60

Output Power (dBm) & Gain (dB)

Measured Output power
Measured Gain

Drain efficiency (%) and PAE (%)

40
Simulated Output power 50
Simulated Gain
35
40
30
30
25
Measured Efficiency
Measured PAE 20
20 Simulated Efficiency
Simulated PAE
10
15

10 0
10 15 20 25 30
Input power (dBm)
Fig. 10. Simulated and measured output performance of the designed PA

3.4 Class E matching network implementation and other topologies

Although Class E approach has basically a fixed circuit topology, different solution can be
adopted for the synthesis of output matching network. Depending on the design frequency,
distributed approaches are possible: proper load conditions at fundamental have to be
satisfied, according to (24), and an open circuit condition must be provided at harmonics of
the fundamental frequency, usually second and third harmonics (Negra et al., 2007;
Wilkinson & Everard, 2001; Xu et al., 2006).
In Fig. 11a, no lumped elements are used unless block capacitors, while the 50 matching is
synthesized through a very compact and simple structure reported in Fig. 11b (Mader et al.,
1998). In order to provide harmonic suppression on the load, different quarter-wave open
stubs can be used at different harmonics (Negra et al., 2007), while series transmission lines
and wave impedances are properly chosen to provide the correct fundamental load.

TL2 TL2
VGG VDD λ/8
l/8
λ/8
l/8

TL1 TL1
Lb Lb
ZE ZE R
R
Cb 1/33 λl 1/11λl Cb TL3
l/12
λ/12
3/20λ
3/20 l 1/10λl
(b)

(a)
Fig. 11. Some practical examples of Class E transmission lines amplifiers.

Additionally, different circuit topologies exist that can provide the same results as the
classical formulation: they have been widely investigated in (Grebennikov, 2003) and are
commonly referred as parallel circuit Class E and their main characteristic is the presence of
 Advanced Microwave and Millimeter Wave
372 Technologies: Semiconductor Devices, Circuits and Systems

a finite parallel inductor in the output network, required for the output device biasing
supply, as reported in Fig. 12. As before assumed, the shunt capacitance C includes the
transistor output capacitance Cds.
The first circuit, in Fig. 12a, employs a very simple output matching network, which consist
of a parallel inductor and a series blocking capacitance. Applying ZVS and ZVDS conditions
on this circuit, and considering the transistor to behave as a perfect switch, the solution of
the circuit is given by a second order non homogeneous differential equation, given by (28),
which has to be solved in order to determine the value of all circuit parameters.

d 2 vs   t   L dvs t 
 2 LC   vs t   VDD (28)
d  t 
2
R d  t 

The values of reactive components, L and C, are:

1.025 R
C L  0.41 (29)
R 

and the load resistance R is determined using the desired output power at fundamental
frequency, P1:

VDD 2
R  1.394
P1
(30)

Due to the lack of any filtering action at the output, this circuit becomes not practical in
applications - like telecommunications - which require harmonic suppression (Grebennikov,
2003). Moreover, a higher peak current value is obtained (4.0IDC instead of 2.862 IDC for the
classical topology) that has to be taken into account in the choice of the active device.
The circuit in Fig. 12b adds a series LC filter in the output branch and it is very similar to a
canonic Class E amplifier using a finite DC feed inductance, unless for the absence of the
“tuning” series inductance. Providing a high Q factor for the LC series filter, the current iR
flowing into the output branch can be assumed as sinusoidal: this hypothesis is used as
starting point for a complete time domain analysis which is similar to what reported in
paragraph 4.1. Optimum parallel capacitance C and optimum load resistance R are obtained
after inferring the phase angle between in-phase and quadrature components of
fundamental current:

 R 
  arctan    RC   34.244 (31)
 L 

From which:

0.685 R
C L  0.732 (32)
R 

Output resistance R is derived from desired fundamental output power, P1:

The Switched Mode Power Amplifiers 373

VDD 2
R  1.365
P1
(33)

Slightly different voltage and current peak values (Grebennikov, 2003) are obtained with
respect to the traditional Class E approach:

VMax  3.647  VDD I Max  2.647  I DC

(34)

In Fig. 12c the parallel inductance is replaced by a short-circuited short length transmission
line: this solution is quite popular at microwave frequencies. In order to approximate the
Class E optimum impedance at fundamental frequency, the electrical length and the
characteristic impedance of the transmission line are determined starting from the optimum
fundamental impedance and according to the relation (Grebennikov, 2003):

Z 0  tan     L. (35)

The load impedance ZE seen at device terminals should satisfy the optimum impedance at
fundamental frequency, and remembering relation (31) it is rewritten as:

R
ZE  (36)
1  j tan

(a) (b)

(c)
Fig. 12. Parallel circuit Class E topology (a), parallel circuit Class E with output filter (b) and
transmission line parallel Class E (c).

Finally, using equation (32) to determine the optimum required parallel inductance, the
electrical length of the parallel transmission line can be obtained:

R
tan   0.732 (37).
Z0
 Advanced Microwave and Millimeter Wave
374 Technologies: Semiconductor Devices, Circuits and Systems

4. The inverse Class E amplifier

The Inverse Class E amplifier, or voltage drive Class E amplifier, is commonly considered as
the dual version of the Class E amplifier, in which current and voltage waveforms are
interchanged, as shown in Fig. 13. It is also referred as “series-L/parallel tuned Class E”,
being the traditional topology defined as “parallel-C/series-tuned Class E” (Mury & Fusco,
2005; Mury & Fusco, 2007).
OFF ON

1.0 1.0

0.8 0.8
vds / VMax

0.6 0.6

iD / IMax
0.4 0.4

0.2 0.2

0.0 0.0

0 3.14 2
rad

Fig. 13. Ideal inverse Class E waveforms.

A former version of the Inverse Class E amplifier was reported in (Kazimierczuk, 1981): the
circuit does not have shunt capacitor, while a series tuned filter and a finite DC feed
inductance is considered in the output network, as depicted in Fig. 14. Although this circuit
seems to be similar to those reported in Fig. 12, it implies a different behavior, due to the
different characteristic of the shunting element (an inductor instead of a capacitor). When
the switch is open, and provided a high enough Q factor of the series filter, the only current
flowing in the circuit is the sinusoidal output current iR, that is the inductor current iL. The
latter causes a voltage drop across the inductor, vL, which has a cosinusoidal form. When the
switch is closed, the voltage across the inductor is instantaneously constant and equal to
VDD. This causes a linear increase in the current iL. The current across the switch is calculated
as the difference between iL and iR and assumes the typical asymmetrical shape.

Fig. 14. Inverse Class E amplifier: no-shunt-capacitor/series-tuned topology with finite

inductance.
The Switched Mode Power Amplifiers 375

A complete analysis of the inverse Class E amplifier is reported for the first time in (Mury &
Fusco, 2005; Mury & Fusco, 2007), together with a defined topology which is shown in Fig.
15 and which is substantially different from the previous version given in (Kazimierczuk,
1981). As can be seen by a comparison of Fig. 15 and the circuit depicted in Fig. 2, each
component of the traditional Class E amplifier has been replaced by its dual element in a
dual configuration. A DC blocking capacitance Cb is inserted in order to prevent inductance
L0 from shorting the bias voltage.

Fig. 15. Inverse Class E amplifier.

Hence, the analysis of the inverse Class E amplifier can be carried out starting from the
assumption of a purely sinusoidal output voltage across the output resistance R, which
produces a voltage across the inductor L given by:

vL    VDD  vo    VDD  1  a  sin      (38)

This is the voltage present across the switch during the OFF time, while during the ON time
the switch has no voltage across it and its current is given by integration of (38):


1
 vL   d
 L 0
iSW  (39)

These expressions have the same form of those reported in paragraph 4.1, unless current
and voltage are interchanged: the same kind of analysis as Class E can be performed on the
Inverse Class E circuit. As a consequence, the same numerical results are obtained for the
dual configuration, and are summarized in Table 1, referred to a 50% duty cycle operation.
As can be seen, the maximum allowable voltage for the Inverse Class E operation is much
smaller than for Class E: this is an unquestionable advantage of such a circuit, because the
requirement on device breakdown can be drastically relaxed.
However, it is worth to notice that in Inverse Class E amplifier the output capacitance of the
active device is not taken into account and set to zero in the ideal analysis: in real world
circuit, this is clearly not true. Hence, some actions have to be taken in order to compensate
its presence (e.g. a shunt inductance).
 Advanced Microwave and Millimeter Wave
376 Technologies: Semiconductor Devices, Circuits and Systems

Circuit component Class E Inverse Class E

or electrical value
VMax 3.562  VDD 2.862  VDD
IMax 2.862  I DC 3.562  I DC
I DC 0.2116
C
    VDD 2  L
0.1836 1
R
 C 0.1836    L
0.2116 VDD
L
2  C     I DC
1 Q
C0
 Q  R R
1 1
L0
 2  C0  2  C0
Table 1 - Class E and Inverse Class E comparison.

5. Class F and Class F-1 amplifier

Among the different switched mode amplifier design strategies, several authors include the
Class F and inverse F (or Class F-1) schemes also.

5.1 Class F theoretical analysis

Such design strategy was introduced by Tyler at the end of fifties (Tyler, 1958) and further
investigated several years later (Snider, 1967; Raab, 1996), as a simple and feasible way to
improve power amplifier large-signal performances.
Following the widely accepted definition, Class-F design consists in terminating the device
output with open-circuit terminations at odd harmonic frequencies of the fundamental
component and short-circuiting it at even harmonics. Regarding the input network, it is
typically synthesized in order to guarantee maximum power transfer at the operating
frequency, neglecting or at least circumventing the device input non linear generation by
using short-circuit terminations.
The theoretical output voltage and current waveforms of an ideal Class F PA are depicted in
Fig. 16.
vDS(t)
2VDD

Im ax iD(t)

T/2 T time
Fig. 16. Ideal output voltage (vDS) and current (iD) waveforms of a Class F PA.
The Switched Mode Power Amplifiers 377

The current is assumed as a truncated sinusoid waves (assuming a Class B bias condition),
while the voltage is squared by the proper harmonic loading conditions. The two ideal
waveforms do not overlap: no output current flows for high drain/collector voltages and
maximum current occurs when drain/collector voltage waveform is at its minimum.
Therefore the power dissipated in the active device is nulled (Pdiss=0).
Such an ideal waveforms can be easily described by their Fourier components:

 I Max
  n0

  I Max n1
iD    I
n 0
n  cos  n  
In   2
n
(40)
 1
 2  I Max  1  2 n even
  2
n 1

0 n odd

VDD n0
 4 V
  DD n1
vDS    V n  cos  n 

Vn  0

n even
(41)
n0  n1

 4  VDD  1  2 n odd
  n

where IMax and VDD the maximum output current and bias voltage, respectively.
From the previous equations it can be noted that the current and voltage Fourier
components with the same order n are alternatively zeroed, thus nulling the power
delivered at harmonic frequencies also (Pout,nf=0, n>1).
The values of the ideal terminations are inferred as the ratio between the respective Fourier
components Vn and In, i.e.:

 8 VDD
  n1
  I Max
Vn 
Zn   0 n even (42)
In 

 n odd


Therefore resulting in a purely resistive terminating impedance at fundamental frequency

given by 4/RTL, being RTL the optimum impedance of a Tuned Load scheme (i.e. short
circuiting all the harmonic terminations). Conversely, short circuit condition for even
harmonics and open circuit for odd ones have to be synthesized, as schematically depicted
in Fig. 17.
 Advanced Microwave and Millimeter Wave
378 Technologies: Semiconductor Devices, Circuits and Systems

VGG VDD

@f0 Bias Bias

Zmatch TEE TEE
IN

+ @f0 @nf0 @nf0

@nf0
n odd n even
n>1 Id Vds
OUT
-
Z1 Zodd=� Zeven=0

Fig. 17. Ideal structure of a Class F amplifier.

The results obtained following the Class F strategy were so interesting that, before the
advent of fast switching devices, such approach was widely adopted to design PAs for
amplitude modulated (AM) broadcast radio transmitters (operating at LF 30-300 KHz, MF
0.3-3 MHz and HF 3-30 MHz) or for frequency modulated (FM) broadcast radio transmitters
(at VHF 30-300 MHz and UHF 0.3-3 GHz) (Wood, 1992; Lu, 1992).
Nowadays, the Class F technique is generally adopted for high frequency applications in the
microwave range (i.e. up to tens of Gigahertz). Examples of Class F based on GaAs devices
are available at X (9.6GHz) (Colantonio et al., 2007), Ku (14.5GHz) (Ozalas, 2005) and Ka
(29.5GHz) (Reece et al., 2003) bands. For high frequency applications the active devices
operate in current-mode rather than in switched-mode, and the harmonic loading conditions
are implemented through lumped resonating circuits.

0,6

I1
0,4
I0
In/IMax

0,2
I2
I3
0,0

Class B Class A
-0,2
0 Class C  Class AB 2


Fig. 18. Fourier components I0, I1, I2, I3 normalised to the device maximum current IMax, as
functions of the drain CCA .

Several research efforts were focused to clarify and to implement the harmonic terminating
scheme leading to the Class F optimum behavior and its experimental validation, inferring
practical design guidelines also (Duvanaud et al., 1993; Blache, 1995; Colantonio et al., 1999).
The Switched Mode Power Amplifiers 379

The analytical results can be easily extended to bias conditions different from Class B, still
assuming for the current waveform a truncated sinusoidal wave shaping, with a conduction
angle (CCA)  larger than  (Class AB), while maintaining a square voltage waveform. In
this case the corresponding current harmonic components as function of the CCA depicted
in Fig. 18 result, while the estimated Class F performances are depicted in Fig. 19, compared
with the corresponding theoretical one for a Tuned Load condition.
Drain Efficiency (%)
100
90
80
Class F
70
Tuned Load
60
50

Normalised Output Power (dBm)

1,4
1,2
1,0 Class F
0,8
0,6
0,4 Tuned Load
0,2
0,0
 3/2 2
CCA 
Fig. 19. Ideal performance for a Class F and reference TL amplifiers as functions of the CCA
. Output power normalized to the Class A output at full swing.

5.2 Class F practical limitations

Referring to the ideal solution proposed to implement the Class F loading scheme, depicted
in Fig. 17, it is based on the use of resonating elements ensuring low impedance values
(theoretically short-circuit conditions) for even harmonic frequencies or high values for the
odd harmonics (theoretically open-circuit conditions).
Clearly, for a simple and manageable mathematical formulation, the active device model has
to be strongly simplified, neglecting all parasitic and reactive elements. It implies that when
dealing with an actual device, the loading condition expressed by (42) has to be fulfilled
across the device intrinsic output current source, as already proposed in other similar
simplified approaches (Cripps, 1983). From a practical point of view, the required ideal
terminations pose significant restrictions when implementing the Class technique. In fact,
while it is relatively simple to realize a short-circuit termination, compensating for the
device reactive elements, the realization of an open-circuit condition becomes much more
cumbersome. For example, in high frequency applications the dominant capacitive behavior
shown by the active device (e.g. Cds) tends to short-circuit the device output itself, thus
practically not allowing the open-circuit loading condition for the higher-order odd
harmonics.
At the same time, even if the internal Cds capacitance can be effectively resonated by an
external inductive element, the device output resistance (Rds) cannot be removed, thus
representing an upper limit for the impedance effectively synthesizable across the intrinsic
current source. Therefore the realization of a true open termination is basically unfeasible.
However, it has been demonstrated that lower-order harmonics are more effective in
improving amplifier performance as compared to higher order ones (Raab, 2001). Therefore,
accounting for the reduced number of harmonics can be effectively controlled, new
 Advanced Microwave and Millimeter Wave
380 Technologies: Semiconductor Devices, Circuits and Systems

terminating impedance values have been inferred not only at fundamental but also at
harmonics, resulting in a different voltage harmonic ratio also (Raab, 1997; Colantonio et al.,
2009). In fact, the new optimum voltage ratio becomes |V3/V1|=1/6 rather than 1/3 as in the
ideal case. Simultaneously, the fundamental loading impedance becomes

4 VDD
RF   (43)
3 I Max

resulting in an efficiency improvement of 15% only with respect to the Tuned Load
theoretical case (Colantonio et al., 2009).
A further critical point is represented by the physical mechanisms generating the harmonic
components of both voltage and current waveforms. If the device output only is considered,
it can be described by an independent and forcing current source, whose waveform results
both from the input drive level and the device physical limitations (clipping effects), being
independent on the device terminating impedances. Under this assumption, the output
voltage waveform is dependent on the current one, being generated by loading each
harmonic current component through the respective terminations (Vn=ZnIn). Consequently
a proper phase relationships between the output current harmonic components must be
fulfilled, and in particular I1 and I3 must be opposite in sign. Such a condition, referring to
Fig. 18 practically implies the selection of a suitable bias level close to the Class B condition,
i.e. assuming a non-zero quiescent current level (deep AB bias), while leaving for instance
the same harmonic terminations as derived in the ideal case. The theoretical load curve
behaves as depicted in Fig. 20.
Conversely, the adoption of a Class C bias condition implies a wrong relationships among
the current harmonics phase (see Fig. 18).
0,30 0,30

VGS=0,5 V
0,25 0,25

VGS=0 V
0,20 0,20

VGS=-0,5 V
ID

ID

0,15 0,15

VGS=-1 V
0,10 0,10

VGS=-1,5 V
0,05 0,05

VGS=-2 V
0,00 0,00
0 2 4 6 8 10 12 14 16 0 T/2 T
VDS time

0 2 4 6 8 10 12 14 16
0

T/2

time

Fig. 20. Theoretical load line for a Class F amplifier.

The Switched Mode Power Amplifiers 381

5.3 Class F matching networks implementation

To design the Class F output section, resonating circuits are typically used as traps for the
harmonic frequencies. Such resonators, sometimes referred as idlers, are limited to low-
order harmonics, to reduce both circuit complexity and associated losses. Moreover,
depending on the frequency range, their implementation can be performed either in lumped
or distributed form, while accounting for also the DC bias.
For example, in Fig. 21 is depicted a possible implementation based on the use of a quarter-
wavelength transmission line (/4-TL) and a parallel resonating L0-C0 tank to control the
harmonic impedances. The optimum matching at fundamental frequency f0 is achieved by
the remaining passive components Lm and Cm (Gao, 2006).

VDD

L1 Cm
C1 /4

R=50
L0 C0 Lm
vin

Fig. 21. Example of Class F output network design.

In practical situations, to account the biasing elements and the active device output
capacitance Cds, other proposed solutions are schematically depicted in Fig. 22, where the
design relationships to calculate the element values can be derived evaluating the
impedance loading the device output current source and then imposing the short circuit
condition at 2f0 and the open circuit one at 3f0. (Trask, 1999).

VDD 1 VDD
L1  4
2
6  w0  Cds L1 
9  w02  C ds
5
L2  C2 9
L2 C2 18  w02  Cds L2  L1
15
C2 
12
Cds
L1 L2 15
5 C 2  C ds
16
L1
C1
C1

Fundamental Fundamental
Matching Matching
vin Network vin Network

Cout Cout
(a) (b)
Fig. 22. Practical implementations of Class F amplifier.
 Advanced Microwave and Millimeter Wave
382 Technologies: Semiconductor Devices, Circuits and Systems

In a similar way, a distributed solution can be designed and implemented by using

transmission lines, as for instance reported in Fig. 23 (Grebennikov, 2000; Woo et al., 2006;
Negra et al., 2007).

VDD VDD

Lchoke

/4   /12  =1/2tan-1[Z0 /(2Lout )-1/3]

Lout=1/(9 Cout)
2



-1
/8 Fundamental
=1/3 tan [1/(3Z 0C out)] Fundamental  /6 /8  Matching
Matching vin Network
vin Network

Cout
Cout
(a) (b)
Fig. 23. Distributed solutions implementing the Class F schemes.

Clearly the characteristic impedances of the TLs have to be properly selected when
designing the matching network at fundamental frequency.

5.4 Class F example

An example of hybrid (MIC) Class F PA operating at 5GHz and based on GaAs device (1mm
gate periphery) is reported in Fig. 24, where both the input and output matching networks
were designed on Alumina substrate by using a dixtributed approach.

Fig. 24. Photo of a MIC 5GHz GaAs Class F amplifier.

The corresponding load curve and the performance as compared to a Tuned Load amplifier
based on the same active device and bias point (Class B), are reported in Fig. 25 and Fig. 26,
respectively.
The Switched Mode Power Amplifiers 383

300

250

200 V GS =0.5 (V)

ID (mA)
V GS =0.0 (V)
150
V GS =-0.5 (V)

100 V GS =-1.0 (V)

Quiescent V GS =-1.5 (V)

Bias Point
50 V GS =-2.0 (V)
V GS =-2.5 (V)
V GS =-3.0 (V)
0
0 2 4 6 8 10 12 14 16

V DS (V)
Fig. 25. Load curve of 5GHz MIC Class F amplifier (dashed curve) compared with Tuned
Load case (continuous curve).

30 70

60 TL
Pout (dBm) - Gain (dB)

25
Pout Class F
50 add,TL
20 TL
 - add (%)

Class F add,Class F
40
15
30
10 Gain
20

5
10

0 0
10 12 14 16 18 20 22 10 12 14 16 18 20 22
Pin (dBm) Pin (dBm)
(a) (b)
Fig. 26. Output Power & Gain (a) and efficiency & power added efficiency (b) for the 5GHz
MIC Class F amplifier as compared to Tuned Load amplifier.

Among the other features, it is to note that the Class F amplifier output power is higher as
compared to the Tuned Load approach in the entire range of input drive. A 7-8% measured
improvement (against a maximum theoretical 15% expected) is usually obtained.
It is to note that at low input power levels, a higher power gain with respect to a Tuned
Load is obviously expected due to the larger output load that has been assured at
fundamental frequency, as given by (43). Increasing the input drive level, the use of a Class
F strategy force the output voltage (and current) to approach their maximum swings value,
resulting in a proper bending of the load curve (see Fig. 25), thus improving the output
power at saturation level also.

5.5 The inverse Class F amplifier

The term “inverse” in this kind of amplifier suggests somewhat inverted in the behavior: in
fact, current and voltage drain waveforms are interchanged if compared to a traditional
Class F amplifier (Ingruber et al., 1998; Lepine et al., 2007; Woo et al., 2006).
Inverse Class F power amplifier was introduced as a “rectangular driven Class A harmonic-
controlled amplifier”, in order to combine the advantage of high efficiency of a switched
mode amplifier with the high gain of Class A operation (Ingruber et al., 1998).
 Advanced Microwave and Millimeter Wave
384 Technologies: Semiconductor Devices, Circuits and Systems

It employs a rectangular driving voltage, which forces the active device to operate in the
ohmic region or in the interdiction region, thus justifying - more than for a Class F - the
classification as a switched mode amplifier. Assuming a piecewise linear simplified model
for the active device, the drain current waveform can be directly inferred, resulting in a
rectangular waveform. Thus, open terminations for even harmonics and short circuit
terminations for odd harmonics - except for the fundamental one - give a truncated sinusoid
voltage waveform. Current and voltage waveform do not overlap, thus preventing DC
power consumption on the active device; additionally, thanks to the proper harmonic
terminations, no power is delivered at harmonics of fundamental frequency and 100% drain
efficiency is ideally achievable.

iD(t)
Imax

Vmax VDS(t)

T/2 T time
Fig. 27. Ideal output voltage (vDS) and current (iD) waveforms of an inverse Class F PA.

Referring to the ideal output current and voltage waveforms of Fig. 27, DC and fundamental
frequency components can be obtained using a Fourier analysis:
I
I 0  Max (44)
2
3
1 2  I Max
I Max  cos   d 

I1  
2
(45)
2 

1 VMax
V0  VDD   V2
Max cos   d  (46)
2 
2 

1 VMax
sin   d 
2


V1  V
2
Max (47)

2 2
Then, the expression of harmonic load impedance is given by:

  2 VDD
  n1
 4 I Max

V 
Zn  n   n even (48)
In 

0 n odd


An inverse Class F amplifier requires an infinite number of resonator in order to maintain

the square-shaped output current. Fig. 28 shows an immediate ideal implementation of an
The Switched Mode Power Amplifiers 385

inverse Class F amplifier using multiple even-harmonic resonators to control the voltage
and current waveforms (Grebennikov & Sokal, 2008).

RFC Cb
2f0 4f0 2nf0

vDS R
VDD iDS f0

Fig. 28. Inverse Class F amplifier with multiharmonic resonator circuit.

In real world design, however, a limited number of harmonics has to be taken into account.
Practical output networks implementations are often based on multiharmonic quarterwave-
lenght stubs (Lepine et al., 2007; Woo et al., 2006). Input network design is the most critical
aspect in inverse Class F design. In fact, if a continuous wave excitation is put on the gate,
the required square wave driving voltage occurs only in deep saturation regime, thus
affecting the gain. Ideal conditions would require a square wave driving voltage throughout
the whole dynamic range of the amplifier. This can be obtained providing fundamental
frequency and its second harmonic as a driving signal (Goto et al., 2001; Grebennikov &
Sokal, 2008), so that an out of phase condition exist at their maximum amplitude. A network
example which satisfied this condition is reported in Fig. 29.
Referring to switched mode finite harmonic operation, it is interesting to find a qualitative
relation between the different classes of amplifier, as reported in (Raab, 2001). The transition
from inverse Class F and Class F amplifiers is achieved by moving the second harmonic
impedance (reactance) from zero to ∞, while decreasing the third harmonic impedance
(reactance) from ∞ to zero, while in the intermediate condition, in which both second and
third harmonic reactances have finite values, current and voltage waveforms assumes a
resemblance to Class E amplifier.

Fig. 29. Bi-harmonic inverse Class F amplifier.

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