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The document discusses the complexities of synchronous timing in DVFS blocks due to varying voltages and frequencies, which affect clock tree delays. It suggests using asynchronous interfaces, exemplified by the ARM1176's configuration with an AXI bus, to manage these timing issues, despite added latency. However, it notes that this approach is impractical for AMBA AHB buses, which do not support split transactions, leading to performance degradation in long-latency scenarios.

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Serajeldeen Ghalyoub 201-801-104
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11 views1 page

New Microsoft Word Document

The document discusses the complexities of synchronous timing in DVFS blocks due to varying voltages and frequencies, which affect clock tree delays. It suggests using asynchronous interfaces, exemplified by the ARM1176's configuration with an AXI bus, to manage these timing issues, despite added latency. However, it notes that this approach is impractical for AMBA AHB buses, which do not support split transactions, leading to performance degradation in long-latency scenarios.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Voltage Scaling Interfaces – Effect on Synchronous Timing The timing of a

synchronous interface between a DVFS block and the rest of the sys tem is
made more complex by the fact that the DVFS block changes voltages and
fre quencies. As the voltage in the DVFS block varies, so do the clock tree
delays. There is no way to distribute a single, low-skew clock to both the
DVFS block and the system that will remain low skew for all voltages. Thus,
the standard model for a synchronous inter face breaks down. One solution is
to use an asynchronous interface. One DVFS-enabled configuration of the
ARM1176 takes this approach. It provides an asynchronous interface to an
AXI bus, complete with synchronizers in both directions. These synchronizers
do add to the initial access latency of the transactions across the interface.
In this case, this increased latency is acceptable because the AXI bus is a
split-transaction bus that can handle long-latency transactions without
degrading the overall bus performance. The more basic AMBA AHB bus does
not support split transactions, and as a result long latency transactions
directly degrade bus performance. Therefore, adding an asynchronous
interface to an AMBA subsystem is not practical in most designs. Figure 9-8
shows one approach to deal with this problem.

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