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Scaling the supply voltage of CMOS can reduce gate delays and power consumption within a technology-specific range, particularly effective in older nodes like 0.18u and 0.13u. Voltage scaling is less effective in 90nm nodes and below due to insufficient headroom, but can be beneficial in low-leakage technology nodes. This technique can enhance battery life in portable devices, although it complicates system design and requires additional voltage regulation.

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Serajeldeen Ghalyoub 201-801-104
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Paper 1

Scaling the supply voltage of CMOS can reduce gate delays and power consumption within a technology-specific range, particularly effective in older nodes like 0.18u and 0.13u. Voltage scaling is less effective in 90nm nodes and below due to insufficient headroom, but can be beneficial in low-leakage technology nodes. This technique can enhance battery life in portable devices, although it complicates system design and requires additional voltage regulation.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Scaling the supply voltage of CMOS is possible over a technology-specific

range; gate delays, setup and hold times and even memory access times
scale monotonically with reduced operating voltage over a limited range.
Linear voltage reduction results in a square-law reduction in both dynamic
power consumption and in leakage power. The earlier chapters have focused
on basic multi-voltage techniques for optimizing dynamic power and on
techniques to address leakage on advanced technology nodes. Voltage
Scaling – reducing the supply voltage and clock frequency based on work
load – is a more aggressive technique for dynamic power reduction. It can be
effective on 0.18u and 0.13u technology nodes (typically 1.8 and 1.2V
standard operating volt age respectively) where there is significant voltage
headroom. In generic 90nm nodes (and below) there is not sufficient
headroom to use voltage scaling very effectively. But it can be applicable to
the “Low-Leakage” technology nodes at 90nm, 65nm and below, since these
run at higher voltage than the equivalent generic or high-speed pro cesses.
(The 90nm low voltage processes run at 1.2V nominal voltage compared to
1.0V for the “generic” or high-speed process nodes, for example). Voltage
scaling introduces complications into both the system design and the imple
mentation flow, but can be valuable for portable battery-powered products.
Rarely is all the logic on a SOC required to run at the limit of performance at
all times, and in many systems there may be several different performance
profiles. Dynamically scal ing the supply voltage to a processor or multi-
media subsystem, for example, may significantly improve battery lifetime in
the final product. But every voltage scaled domain introduces another
voltage regulator, usually off chip, and the requirement to interface between
different analog values across voltage boundaries.

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