“Embedded Processors [301495]”

Unit-3: Real World Interfacing with

ARM7 Based Microcontroller
 UNIT – III: Real World Interfacing with ARM7 Based Microcontroller

•UART Programming for transmission and reception of characters

•On-chip ADC using interrupt (VIC)
•On-chip DAC for waveform generation
•EEPROM using I2C,
•Interfacing the peripherals to LPC2148: GSM and GPS using UART
•Interfacing with ARM 7 with DHT 11 sensor and servomotor.

Unit Objectives
1. To get acquainted with programming concept of LPC 2148 processor.
2. To understand interfacing of LPC2148 with various peripheral s.
3. To get insight of on chip peripheral s and its programming for LPC2148.

Unit Outcomes Mapping With COs :

1. To demonstrate interfacing of
CO3: Know about the programming of ARM 7 based
the peripherals with LPC2148. various
microcontroller with on chip peripherals and external
2. To explain on peripherals peripherals.
chip programming for and its Mapping With POs :
LPC2148

Books :
• R1: UM10139 LPC214x User manual, NXP Semiconductor

E&TC Enginnering Department,

AISSMS COE, Pune
UART Programming for transmission and
reception of characters

E&TC Enginnering Department,

AISSMS COE, Pune
 Basics of UART Communication
UART or Universal Asynchronous Receiver Transmitter is a dedicated
hardware associated with serial communication.

The hardware for UART can be a circuit integrated on the

microcontroller or a dedicated IC. This is contrast to SPI or I2C, which
are just communication protocols

UART is one of the most simple and most commonly used Serial
Communication techniques.

Today, UART is being used in many applications like GPS Receivers,

Bluetooth Modules, GSM and GPRS Modems, Wireless Communication
Systems, RFID based applications etc.
 Basics of UART Communication

❖ If you remember older computer systems, devices like Mouse, Printer and
Modem are connected using a heavy connectors at the back. All these devices
communicated using UART.

❖Even though USB has replaced all types of communication standards on

computers and other devices, UART is still being used in the above
mentioned applications.

❖Almost all microcontrollers have dedicated UART hardware built in to their

architecture. The main reason for integrating the UART hardware in to
microcontrollers is that it is a serial communication and requires only two
wires for communication.
 Basics of UART Communication
❖ Basic about Parallel and Serial Communication
Transfer of Digital Data from one device to another can be achieved in two ways:
1. Parallel Data Transfer
2. Serial Data Transfer.

In parallel data transfer, all the bits are transferred from the source to destination at
once. This is possible because parallel data transfer uses multiple lanes or wires
between the transmitter and receiver in order to transfer the data.
 Basics of UART Communication
❖ Basic about Parallel and Serial Communication
Parallel Data Transfer methods are faster and expensive as they needs more
hardware and a lot of wires. Olden day’s printers are the best example for
external parallel communication. Other examples are RAM, PCI, etc.

With the progress in integrated circuit technology, the digital IC’s are becoming
smaller and faster and as a result the transfer rates in Parallel Communication
with multiple lanes have reached a bottle neck.

Serial Communication on the hand, transfers data bit by bit using a single line or
wire. For two way communication between the transmitter and receiver, we
need just two wires for successful serial data transfer.
 Basics of UART Communication
❖ Basic about Parallel and Serial Communication
Since serial communication needs less circuitry and wires, the cost of implementing
is less. As a result, using serial communication in complex circuitry might be more
practical than parallel communication.
But the only concern with serial data transfers is speed. Since the data transfer occurs
over a single line, the speed of transfer in serial communication is less than that of
parallel communication. Now – a – days, the speed of serial data transfer isn’t a
concern as advancements in technology have led to faster transfer speeds.
Introduction to UART Communication
UART or Universal Asynchronous Receiver Transmitter is a serial
communication device that performs parallel – to – serial data conversion at the
transmitter side and serial – to – parallel data conversion at the receiver side.
It is universal because the parameters like transfer speed, data speed, etc. are
configurable.
Since, UART is a piece of hardware that acts as a bridge between the processor
and the serial communication protocol or port as shown in fig below, The serial
communication can be anything like USB, RS232, etc.
Introduction to UART Communication

The letter ‘A’ in UART stands for Asynchronous i.e. there is no clock signal to synchronize or
validate the data transmitted from transmitter and received by the receiver (Asynchronous
Serial Communication).
This is in contrast to Synchronous Serial Communication, which uses a clock signal that is
shared between the transmitter and receiver in order to “Synchronize” the data between them.

If there is no clock (or any other timing signal) between the transmitter and receiver,
then how does the receiver know when to read the data?

In UART, the transmitter and receiver must agree on timing parameters beforehand. Also,
UART uses special bits at the beginning and ending of each data word to synchronize the
transmitter and receiver.
In UART based Serial Communication, the transmitter and receiver communicate in the
following manner.
1. The UART on the sender device i.e. the transmitting UART receives parallel data from
the CPU (microprocessor or microcontroller) and converts it in to serial data. This serial
data is transmitted to the UART on the receiver device i.e. receiving UART.
2. The receiving UART, upon receiving the serial data, converts it back to parallel data and
gives it to the CPU.
Introduction to UART Communication

The pin on the transmitting UART, which transmits the serial data is called TX and
the pin on the receiving UART, which receives the serial data is called RX.

Since the UART involves parallel – to – serial and serial – to – parallel data
conversion, shift registers are an essential part of the UART hardware.
Two shift registers to be specific:
1. Transmitter Shift Register
2. Receiver Shift Register.
 How UART Works?

In UART Serial Communication, the data is transmitted asynchronously i.e. there

is no clock or other timing signal involved between the sender and receiver.

Instead of clock signal, UART uses some special bits called Start and Stop bits.
These bits are added to the actual data packet at the beginning and end
respectively. These additional bits allows the receiving UART to identify the
actual data.
 How UART Works?

The transmitting UART receives data from the controlling device through the data
bus. The controlling device can be anything like a CPU of a microprocessor or a
microcontroller, memory unit like a RAM or ROM, etc.

The data received by the transmitting UART from the data bus is parallel data. To
this data, the UART adds Start, Parity and Stop bits in order to convert it into a data
packet.

The data packet is then converted from parallel to serial with the help of shift
register and is transmitted bit – by – bit from the TX pin.

The receiving UART receives this serial data at the RX pin and detects the actual
data by identifying the start and stop bits. Parity bit is used to check the integrity of
the data.

Up on separating the start, parity and stop bits from the data packet, the data is
converted to parallel data with the help of shift register. This parallel data is sent to
the controller at the receiving end through a data bus.
 Structure of Data Packet or Frame
The data in UART serial communication is organised in to blocks called Packets or Frames.
The structure of a typical UART Data Packet or the standard framing of the data is shown in
the following fig.

a) Start Bit: Start bit is a synchronisation bit that is added before the actual data.
Start bit marks the beginning of the data packet. Usually, an idle data line i.e.
when the data transmission line is not transmitting any data, it is held at a high
voltage level (1).
In order to start the data transfer, the transmitting UART pulls the data line from
high voltage level to low voltage level (from 1 to 0). The receiving UART
detects this change from high to low on the data line and begins reading the actual
data. Usually, there is only one start bit.
 Structure of Data Packet or Frame

b) Stop Bit: The Stop Bit, as the name suggests, marks the end of the data packet.
It is usually two bits long but often only on bit is used. In order to end the
transmission, the UART maintains the data line at high voltage (1).

c) Parity Bit: Parity allows the receiver to check whether the received data is
correct or not. Parity is a low – level error checking system and comes in two
varieties: Even Parity and Odd Parity. Parity bit is optional and it is actually not
that widely used.

d) Data Bits: Data bits are the actual data being transmitted from sender to
receiver. The length of the data frame can be anywhere between 5 and 9 (9 bits if
parity is not used and only 8 bits if parity is used). Usually, the LSB is the first
bit of data to be transmitted.
 Rules of UART
As, there is no clock signal in UART and the transmitter and receiver must agree on
some rules of serial communication for error free transfer of data.
The rules include:
▪ Synchronisation Bits (Start and Stop bits)
▪Parity Bit
▪Data Bits
▪Baud Rate

Baud Rate: The speed at which the data is transmitted is mentioned using Baud
Rate. Both the transmitting UART and Receiving UART must agree on the Baud
Rate for a successful data transmission.
Baud Rate is measured in bits per second. Some of the standard baud rates are 4800
bps, 9600 bps, 19200 bps, 115200 bps etc. Out of these 9600 bps baud rate is the
most commonly used one.
• Let us see an example data frame where two blocks of data i.e. 00101101 and
11010011 must be transmitted. The format of the frame is 9600 8N1 i.e. 9600
bps with 8 bits of data, no parity and 1 stop bit. In this example, we haven’t used
the parity bit.
❑ The asynchronous serial protocol has a number of built-in rules -
mechanisms that help ensure robust and error-free data transfers.
✔ Data bits
✔ Synchronization bits
✔ Parity bits
✔ Baud rate.
❑ The baud rate specifies how fast data is sent over a serial line.
It’s usually expressed in units of bits-per-second (bps).
Framing the data
❑ Each block (usually a byte) of data transmitted is actually sent in
a packet or frame of bits. Frames are created by appending
synchronization and parity bits to our data.
 A serial frame.

9600 8N1 (an example)

❑ 9600 8N1 - 9600 baud, 8 data bits, no parity, and 1 stop bit - is
one of the more commonly used serial protocols.
❑ A device transmitting the ASCII characters ‘O’ and ‘K’ would
have to create two packets of data.
❑ The ASCII value of O(that’s uppercase) is 79, which breaks
down into an 8-bit binary value of 01001111, while K’s binary
value is 01001011.
❑ All that’s left is appending sync bits.
❑ It isn’t specifically stated, but it’s assumed that data is transferred
least-significant bit first.
❑ Notice how each of the two bytes is sent as it reads from
right-to-left.

Since we’re transferring at 9600 bps, the time spent holding each
of those bits high or low is 1/(9600 bps) or 104 µs per bit.
Wiring and Hardware
❑ A serial bus consists of just two wires - one for sending data and
another for receiving. As such, serial devices should have two
serial pins: the receiver, RX, and the transmitter, TX.
Hardware Implementation
❑ RS-232, which can be found on some of the more ancient
computers and peripherals, is like TTL serial flipped on its head.
❑ RS-232 signals usually range between -13V and 13V, though the
spec allows for anything from +/- 3V to +/- 25V.
❑ On these signals a low voltage (-5V, -13V, etc.) indicates either
the idle line, a stop bit, or a data bit of value 1.
❑ A high RS-232 signal means either a start bit, or a 0-value data
bit. That’s kind of the opposite of TTL serial.
❑ The MAX232 is an IC originally designed by a company called
Maxim IC that converts the +/-13V(+/-25V) signals of RS232
down to the 0/5V signals that our Microcontroller can understand.
❑ It also boosts the voltage of our Microcontroller to the needed
+/-13V(+/-25V) of the RS232 protocol so that a computer can
understand our Microcontroller and vice versa.
 RS232 Protocol
https://www.electronicshub.org/

RS232 is one of the most widely used techniques to interface external

equipment with computers. RS232 is a Serial Communication
Standard developed by the Electronic Industry Association
(EIA) and Telecommunications Industry Association (TIA).
RS232 defines the signals connecting between DTE and DCE. Here,
DTE stands for Data Terminal Equipment and an example for DTE is
a computer. DCE stands for Data Communication Equipment or Data
Circuit Terminating Equipment and an example for DCE is a modem.
UART in LPC2148 ARM7 Microcontroller- Serial Communication

Serial Data Transmission in UART

https://binaryupdates.com/uart-in-lpc2148-arm7/
Voltage Levels
RS232 was defined way before TTL logic and hence, it is not
unexpected that RS232 doesn’t use the TTL specific 5V and GND
logic levels.The logic ‘1’ in RS232 is described as being in the
voltage range of -15V to -3V and logic ‘0’ is described as the voltage
range of +3V to +15V i.e. low level voltage is logic ‘1’ and high level
voltage is logic ‘0’. Typically, the logic ‘1’ in RS232 will be -12V and
logic ‘0’ will be +12V.

List of UART in
LPC2148
UART section of LPC 2148:

● The LPC 2148 contains two UARTs which are compatible with
UART IC 16C550 (Industry Standard UART IC).
● UART0 provides only standard transmit and receive data lines
● UART1 also provides a full modem control handshake interface
along with standard transmit and receive data lines.
LPC214x UART0
Features:
● 16 byte Receive and Transmit FIFOs
● Register locations conform to ‘550 industry standard.
● Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
● Built-in fractional baud rate generator with autobauding
capabilities.
● Mechanism that enables software and hardware flow control
implementation.
UART0 block diagram
LPC214x UART1
Features
● UART1 is identical to UART0, with the addition of a modem
interface.
● 16 byte Receive and Transmit FIFOs.
● Register locations conform to ‘550 industry standard.
● Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
● Built-in fractional baud rate generator with autobauding capabilities.
● Mechanism that enables software and hardware flow control
implementation.
● Standard modem interface signals included with flow control
(auto-CTS/RTS) fully supported in hardware (LPC2144/6/8 only).
UART1 block diagram

Pin Type Description

Serial Input: Serial receive
RXD1 Input
data.
Serial Output: Serial transmit
TXD1 Output
data.
CTS1 Input Clear To Send

DCD1 Input Data Carrier Detect

DSR1 Input Data Set Ready

DTR1 Output Data Terminal Ready

RI1 Input Ring Indicator

RTS1 Output Request To Send

 UART0 Registers
Registers Description/Function
Transmit Hold Register: This register contains 8-bit write data
U0THR which can be transmitted through UART0. This is write only
register.

Receive Buffer Register: This register contains 8-bit received data

from UART0. This data is nothing but top most byte of Rx FIFO.
U0RBR
When we use 5, 6 or 7-bit data then remaining bits are padded with
0’s by default. This is read only register.

Line Control Register: The value or settings in this register

configure the UART0 block. As this is an 8-bit register. There are
several parameters configured through this register such as word
U0LCR
length, stop bit, parity enable, parity select, break control, divisor
latch access bit. This register setting plays important role while
initializing UART0 before using it.
 UART0 Registers

U0DLL & U0DLM are standard UART0 baud rate generator

divider registers. Each of this register holds 8-bit values. Together
U0DLL &
these registers form a 16-bit divisor value which will be used for
U0DLM
baud rate generation.

Fractional Divider Register: This is another very important

register, which plays significant role in baud rate generation. In this
8-bit register, first four bits i.e. Bit[3 to 0]-DIVADDVAL: This is
the Prescale Divisor value. If this value is 0 then fractional baud rate
U0FDR
generator have no effect on UART0 baud rate. The remaining 4-bits
i.e. Bit[4 to 7]-MULVAL: This defines Prescale Multiplier value.
Even if fractional baud rate generator is not used the value in this
register must be more than or equal to ‘1’.
UART0 Receiver Buffer Register (U0RBR - 0xE000 C000, when
DLAB = 0, Read Only)
The U0RBR is the top byte of the UART0 Rx FIFO. The Divisor Latch Access
Bit (DLAB) in U0LCR must be zero in order to access the U0RBR. The U0RBR
is always Read Only.

UART0 Transmit Holding Register (U0THR - 0xE000 C000, when

DLAB = 0, Write Only)
The U0THR is the top byte of the UART0 TX FIFO. The Divisor Latch
Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR.
The U0THR is always Write Only.
UART0 Divisor Latch Registers (U0DLL - 0xE000 C000 and U0DLM -
0xE000 C004, when DLAB = 1)
The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator
and holds the value used to divide the clock supplied by the fractional prescaler in
order to produce the baud rate clock, which must be 16x the desired baud rate
(Equation 1).The Divisor Latch Access Bit.(DLAB) in U0LCR must be one in order
to access the UART0 Divisor Latches.
UART0 Fractional Divider Register (U0FDR - 0xE000 C028)
The UART0 Fractional Divider Register (U0FDR) controls the clock pre- scaler
for the baud rate generation and can be read and written at user’s discretion. This
pre-scaler takes the APB clock and generates an output clock per specified
fractional requirements.
UART0 Line Control Register (U0LCR - 0xE000 C00C)
The U0LCR determines the format of the data character that is to be
transmitted or received.
DLAB (Divisor Latch Buffer)
One high-low pulse across DLAB bit indicates baud rate is successfully loaded.
•DLAB=1 baud rate is loading
•DLAB=0 After loading baud rate DLAB must be zero.
Failed to execute the [code] macro. Cause: [String index out of range: 3]. Click
on this message for details.
The message will be received and displayed on terminal emulator or serial
console which configured to appropriate COM Port of PC. In our program
we will use following configuration to establish proper communication:

Baud Rate = 9600 baud (with PCLK=60Mhz)

Data Length = 8 bits
No Parity Bit
and 1 Stop Bit
The master formula for calculating baud rate is given as :

which can be further simplified to :

U0LSR (Line Status Register)

6th bit of LSR is TI flag bit

While(!(U0LSR&0x40));//Monitoring TI bit syntax

0th bit of LSR is RI flag bit

While(!(U0LSR&0x01));//Monitoring RI bit syntax
 UART Initialization

1. Set the PCLK

2. Configure the GPIO Pin for UART Tx and Rx
3. Configure the Rx Pin as input and Tx pin as output
4. Reset the FIFO register and enable it.
5. Set the length of data bit, stop bit and Parity bit.
6. Generate the desired baud rate by computing using master
formula
7. Enable the UART0 Tx and Rx for transmission and Reception of
data or string.
Program to receive and transmit data using UART0

#include<LPC21xx.h>
void main()
{
char a;
VPBDIV=0x00 // 15 MHz freq.
PINSEL0=0x00000005;//P0.0 as TxD0 & P0.1 as RxD0
IODIR0 = 0x01
U0LCR=0x83;//8 -bit character length,DLAB=1
U0DLM=0x00;//
U0DLL=0x61;// Baud rate=9600
U0LCR=0x03;// DLAB=0; to load baud rate value

while(1)
{
while(!(U0LSR&0x01)); //monitoring RI flag
a=U0RBR;

while(!(U0LSR&0x20)); // monitoring TI flag

U0THR=a;
}
}
void Init_UART0(void) //This function setups UART0
{
unsigned int Baud16;
U0LCR = 0x83; // DLAB = 1
Baud16 = (Fpclk / 16) / UART_BPS;
U0DLM = Baud16>>8; //
U0DLL = Baud16 & 0xff; //
U0LCR = 0x03;
}

void UART0_SendByte(unsigned char data)

//A function to send a byte on UART0
{
U0THR = data;
while( (U0LSR&0x20) = =0 );
}
void UART0_SendStr(const unsigned char *str)
//A function to send a string on UART0
{
while(1)
{
if( *str == '\0' ) break;
UART0_SendByte(*str++);
}
}
int main(void)
{
PINSEL0 = 0x00000005; // Enable UART0 Rx and Tx pins
PINSEL1 = 0x00000000;
PINSEL2 = 0x00000000;
Init_UART0( );
UART0_SendStr(SEND_STRING);
while((U0LSR&0x01)==0);
UART0_SendStr(SEND_STRING1);
while(1)
{
}
return(0);
}
 Interfacing the peripherals to LPC2148: GSM
and GPS using UART
Global System for Mobile Communication
∙Features of GSM MODEM
∙GSM Module
∙GSM Mobile Vs GSM Module
∙AT Commands
• Interfacing of GSM Module
∙Interfacing Diagram
∙Pin assignment with LPC 2148
∙Algorithm for GSM module interfacing with LPC2148

3/26/2025 51
 Global System for Mobile Communication
• GSM (Global System for Mobile Communications) is the
technology that underpins most of the world's mobile phone
networks.
• GSM is an open, digital cellular technology used for transmitting
mobile voice and data services.
• The SIM300 module is a Triband GSM/GPRS solution in a compact
plug in module featuring an industry-standard interface
• GSM operates in the 900MHz and 1.8GHz bands GSM supports
data transfer speeds of up to 9.6 kbps, allowing the transmission of
basic data services such as SMS.

3/26/2025 52
 Features of GSM MODEM
•Single supply voltage 3.2v-4.5v
•Typical power consumption in SLEEP Mode: 2.5mA.
•SIM300 tri-band
•MT,MO,CB, text and PDU mode, SMS storage: SIM
card
•Supported SIM Card :1.8V,3V

3/26/2025 53
 GSM Module: Block Diagram

3/26/2025 54
 GSM Module

GSM/GPRS module is used to establish communication between a

computer and a GSM-GPRS system.
Global System for Mobile communication (GSM) is an architecture
used for mobile communication in most of the countries.
Global Packet Radio Service (GPRS) is an extension of GSM that
enables higher data transmission rate

3/26/2025 55
 GSM Mobile Vs GSM Module
• A GSM mobile is a complete system in itself with embedded processors that are
dedicated to provide an interface between the user and the mobile network.
• The AT commands are served between the processors of the mobile termination and the
terminal equipment.
• The mobile handset can also be equipped with a USB interface to connect with a
computer, but it may or may not support AT commands from the computer or an external
processor/controller.
• The GSM/GPRS module, on the other hand, always needs a computer or external
processor/controller to receive AT commands from.
• GSM/GPRS module itself does not provide any interface between the user and the
network, but the computer to which module is connected is the interface between user
and network.
• An advantage that GSM/GPRS modules offer is that they support concatenated (link
(things) together in a chain or series) SMS which may not be supported in some GSM
mobile handsets
• Applications of GSM/GPRS module:
The GSM/GPRS module demonstrates the use of AT commands. They can feature
all the functionalities of a mobile phone through computer like making and receiving
calls, SMS, MMS etc. These are mainly employed for computer based SMS and MMS
services.
3/26/2025 56
 GSM modem: Overview
A GSM modem is a wireless modem that works with a GSM wireless
network. A wireless modem behaves like a dial-up modem. The main
difference between them is that a dial-up modem sends and receives data
through a fixed telephone line while a wireless modem sends and receives
data through radio waves.

A GSM modem can be an external device or a PC Card / PCMCIA Card.

Typically, an external GSM modem is connected to a computer through a
serial cable or a USB cable. A GSM modem in the form of a PC Card /
PCMCIA Card is designed for use with a laptop computer. It should be
inserted into one of the PC Card / PCMCIA Card slots of a laptop computer.

Like a GSM mobile phone, a GSM modem requires a SIM card from a
wireless carrier in order to operate.

Computers use AT commands to control modems. Both GSM modems and

dial-up modems support a common set of standard AT commands. You can
use a GSM modem just like a dial-up modem.
3/26/2025 57
 GSM modem: Overview
In addition to the standard AT commands, GSM modems support
an extended set of AT commands. These extended AT commands
are defined in the GSM standards. With the extended AT
commands, you can do things like:

• Reading, writing and deleting SMS messages.

• Sending SMS messages.
• Monitoring the signal strength.
• Monitoring the charging status and charge level of the battery.
• Reading, writing and searching phone book entries.

The number of SMS messages that can be processed by a GSM

modem per minute is very low -- only about six to ten SMS
messages per minute.

3/26/2025 58
 AT commands :Overview
AT commands are instructions used to control a modem. AT is the abbreviation
of ATtention.

Every command line starts with "AT" or "at". That's why modem commands are
called AT commands.
The AT is an ATTENTION command and is used as a prefix to other parameters
in a string. The AT command combined with other parameters can be set up in the
communications package or typed in manually as a command line instruction.
Many of the commands that are used to control wired dial-up modems, such as
ATD (Dial), ATA (Answer), ATH (Hook control) and ATO (Return to online
data state), are also supported by GSM/GPRS modems and mobile phones.

Besides this common AT command set, GSM/GPRS modems and mobile

phones support an AT command set that is specific to the GSM technology,
which includes SMS-related commands like AT+CMGS (Send SMS message),
AT+CMSS (Send SMS message from storage), AT+CMGL (List SMS
messages) and AT+CMGR (Read SMS messages).
3/26/2025 59
 AT commands :Overview

The starting "AT" is the prefix that informs the modem about the start of
a command line. It is not part of the AT command name.
For example, D is the actual AT command name in ATD and +CMGS is
the actual AT command name in AT+CMGS. However, some books and
web sites use them interchangeably as the name of an AT command.

There are basically 2 types of AT commands in terms of their syntax:

1. Basic commands.
2. extended commands

3/26/2025 60
 AT commands :Overview

1. Basic commands:
Basic commands are AT commands that do not start with “+”. For
example, D(Dial), we can write the command for dialing a call as
ATD. Similarly for A(Answer), H(hook control) and O(Return to
online data state) we can use the commands ATA, ATH and ATO
respectively.
2. Extended commands :
Extended commands are AT commands that start with “+”. All GSM
AT commands are extended commands. For example, +CMGS(Send
SMS message), +CMSS(Send SMS message from storage),
+CMGL(List SMS messages) and +CMGR( Read SMS message) are
some of the extended commands.

3/26/2025 61
 AT commands :Overview

• AT commands are used to control Modems. AT is the abbreviation for Attention.

• These commands come from Hayes commands that were used by the Hayes
smart modems.

• The Hayes commands started with AT to indicate the attention from the
MODEM.
•Hayes commands developed by Dennis Hayes for the Hayes Smartmodem 300
baud modem in 1981.

• The dial up and wireless MODEMs need AT commands to interact with a

computer.

• AT commands with a GSM/GPRS MODEM

3/26/2025 62
 GSM AT Commands and their functions
GSM AT Commands and their functions
AT Command Function of AT Command
ATD Dial
AT+CGMS Send SMS Message

AT+CMSS Send SMS Message from storage

AT+CMGL List SMS Messages

AT+CMGR Read SMS Messages
AT+CSCA? Service Centre Address

AT+CPMS To choose storage from ME or SM

AT+IPR=0 To choose auto from baud rate

AT+SMGF= To choose PDU Mode or Text Mode

3/26/2025 63
 GSM AT Commands and their functions

AT command Description
This command is used to check communication between the
AT
module and the computer.
AT+CMGF=< set the SMS mode(PDU mode or text mode).
mode>
AT+CMGF Message format
AT+CMGL List messages
AT+CMGR Read message
AT+CMGS Send message
AT+CMSS Send message from storage
AT+CMGW Write message to memory
AT+CMGD Delete message
 GSM AT Commands and their functions
-Set functionality to various modes such as GSM, CDMA and
LTE. It is mainly used in modem providing multi-RAT
AT +CFUN=value support.
-Value=some number 0 to 6 or more. 1 means full
functionality
ATD <number> used to call a phone number.
ATA used to answer an incoming call
ATH used to disconnect the established call
AT+CGDCONT=1,"IP AT command to define PDP context,APN is gateway between
address","APN" GPRS network & internet.
AT+COPS=1,2,26201 Manual PLMN selection
AT+COPS? Will provide PLMN information set in the modem
AT+CGMR Display the version of the software loaded on the modem
Used to activate and deactivate GPRS or PS connection
AT+CGATT AT+CGATT=0 deactivates and AT+CGATT=1 activates the
GPRS
 AT commands:Operations
There are total 4 types of AT commands in terms of their operation:
1.Test operation:
A test operation is used to check whether a certain AT command is
supported by the GSM/GPRS modem or mobile phone.

2. Set operation:
A set operation is used to change the settings used by the
GSM/GPRS modem or mobile phone for certain tasks.

3. Read operation:
A read operation is used to retrieve the current settings used by the
GSM/GPRS modem or mobile phone for certain tasks.

4. Execution operation: An execution operation is used to perform an

action or retrieve information/status about the GSM/GPRS modem or
mobile phone.
3/26/2025 66
 Test Operation
A test operation is used to check whether a certain AT command is supported by the
GSM/GPRS modem or mobile phone. All extended AT commands support the test
operation.
The syntax is:
command=?
where command is an AT command. When an AT command is used in the above syntax to
perform a test operation, it is called a test command.

Here is an example. The AT command +CGMI (command name in text: Request

Manufacturer Identification) is used to get the manufacturer name of the GSM/GPRS
modem or mobile phone. To test whether +CGMI is supported, you can make use of the test
command "+CGMI=?". The complete command line that should be entered is:
AT+CGMI=?
If the GSM/GPRS modem or mobile phone supports the AT command +CGMI, the result
code "OK" will be returned, like this:
AT+CGMI=?
OK
If the GSM/GPRS modem or mobile phone does not support the AT command
+CGMI, the result code "ERROR" will be returned, like this:
AT+CGMI=?
3/26/2025 67
ERROR
 Test Operation
If the AT command to be tested has parameter(s), the parameter value(s) supported by
the GSM/GPRS modem or mobile phone may be printed additionally.
Below is an example that illustrates the format of the response. +COMMAND1 is a
fictitious AT command that has four parameters.
AT+COMMAND1=?
+COMMAND1: (0,1),(0-10),(0,1,5-10),("GSM","UCS2")
OK

The supported values of each of the four parameters are enclosed in parentheses.
Commas are used to delimit the parentheses and the values inside parentheses. A
hyphen is used to indicate a range of values. The values inside parentheses can be of
the string type.
In the above example, the response of the test command "+COMMAND1=?"
provides us the following information:
(0,1). The first parameter accepts either 0 or 1.
(0-10). The second parameter accepts any integer between 0 and 10.
(0,1,5-10). The third parameter accepts 0, 1 or any integer between 5 and 10.
("GSM","UCS2"). The fourth parameter accepts either the string "GSM" or "UCS2".
3/26/2025 68
 Test Operation
To a few AT commands, the test operation does not return the parameter values supported.
Instead, it returns the values that are allowed to appear in the information response of the AT
command. An example is the +CBC AT command (command name in text: Battery Charge).
The +CBC command is used to retrieve the connection status and charge level of the battery of
the mobile device. Two values are returned in the information response of the +CBC AT
command. The format is:
+CBC: connection_status,charge_level

For example, if the battery is placed in the mobile device with no charger connected and the
charge level is 80%, the result of the execution of the +CBC AT command will be:
AT+CBC
+CBC: 0,80
OK
If you run the test command "+CBC=?", all the supported values that are allowed to appear in
the connection status field and charge level field will be provided. With Nokia 6021, the result
is:
AT+CBC=?
+CBC: (0,1),(0-100)
OK
"(0,1)" means the connection status field in the information response of the +CBC AT
command can contain either 0 or 1, while "(0-100)" means the charge level field can contain
any 3/26/2025
integer between 0 and 100 69
Set Command:
A set operation changes the settings used by the GSM/GPRS modem or mobile
phone for certain tasks.
The syntax is:
command=value1,value2,...valueN
where command is an AT command and value1 to valueN are the values you want to
set. When an AT command is used in the above syntax to perform a set operation, it
is called a set command.

Here is an example. The AT command +CSCA (command name in text: Service

Centre Address) is used to set the SMSC (SMS center) address for sending SMS
messages. It takes two parameters that specify the SMSC address and type of
address. To set the SMSC address to +85291234567, enter the following command
line in a terminal program such as MS Windows' HyperTerminal:
AT+CSCA="+85291234567",145
If the set command runs successfully, the result code "OK" will be returned:
AT+CSCA="+85291234567",145
OK
3/26/2025 70
Set Command:
Some AT commands have optional parameters. You can choose not to assign values
to them. For example, the second parameter of the +CSCA AT command is optional.
If no value is assigned to the second parameter, the GSM/GPRS modem or mobile
phone will use the default parameter value, which is 145 if the SMSC address starts
with "+" (the plus character). Hence, this command line:
AT+CSCA="+85291234567"
is equivalent to:
AT+CSCA="+85291234567",145

Typically the values you specified with set commands are placed in volatile
memory. If the GSM/GPRS modem or mobile phone is switched off or rebooted, the
values you specified with set commands will be gone. When the GSM/GPRS
modem or mobile phone is powered on again, all settings are back to the defaults.

For some commonly used settings, there are AT commands for saving/restoring the
settings to/from non-volatile memory. For example, the AT commands +CSAS
(command name in text: Save Settings) and +CRES (command name in text:
Restore Settings) can be used to save and restore settings related to SMS messaging
such as the SMS center address.
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Read Command:
A read operation retrieves the current settings used by the GSM/GPRS modem or
mobile phone for certain tasks.
The syntax is:
command?
where command is an AT command. When an AT command is used in the above syntax
to perform a read operation, it is called a read command. The read operation is
supported by all AT commands that are capable of the set operation.

Here is an example that illustrates how to use a read command. The AT command
+CSCA (command name in text: Service Centre Address) is used to set the SMSC
(SMS center) address for sending SMS messages. It takes two parameters that specify
the SMSC address and type of address.
Suppose you set the SMSC address to +85291234567 in the HyperTerminal, like this:
AT+CSCA="+85291234567",145
OK
After that, if you enter the read command "+CSCA?", the GSM/GPRS modem or
mobile phone will return the SMSC address and type of address that you set in the
previous step:
AT+CSCA?
+CSCA: "+85291234567",145
3/26/2025 72
OK
 Execution Command:
An execution operation is used to perform an action (for example, send or read an
SMS message) or retrieve information/status about the GSM/GPRS modem or mobile
phone (for example, retrieve the current battery charge level, battery charging status
or radio signal strength of the mobile network).
The syntax is:
command=value1,value2,...valueN
where command is an AT command and value1 to valueN are the values to assign to
the AT command. If the AT command does not have any parameters, the part
"=value1,value2,...valueN" should be omitted. When an AT command is used in the
above syntax to perform an execution operation, it is called an execution command.

Here is an example illustrating the use of an execution command. The AT command

+CMSS (command name in text: Send Message from Storage) can be used to
perform an execution operation to send an SMS message stored in message storage. It
has three parameters. They specify the index of the memory location that stores the
SMS message, the destination phone number and the type of the phone number
respectively. To send the SMS message at index 1 to the phone number
+85291234567, the following command line can be used:
AT+CMSS=1,"+85291234567",145
3/26/2025 73
 Execution Command:
Some AT commands have optional parameters. You can choose not to assign values
to them. For example, the third parameter of the +CMSS AT command is optional.
If no value is assigned to the third parameter, the GSM/GPRS modem or mobile
phone will use the default parameter value, which is 145 if the destination phone
number starts with "+" (the plus character). Hence, this command line:
AT+CMSS=1,"+85291234567"
is equivalent to:
AT+CMSS=1,"+85291234567",145

Unlike set commands, execution commands do not store the parameter values
assigned to them. So, no read command is available for retrieving the last
parameter values assigned to an execution command. For example, if you send the
command line "AT+CMSS?" to your GSM/GPRS modem or mobile phone, the
ERROR result code will be returned:
AT+CMSS?
ERROR

3/26/2025 74
 Interfacing GSM with LPC2148
The GSM module is communicate the microcontroller with mobile phones through
UART. To communicate over UART or USART, we just need three basic signals which
are namely, RXD (receive), TXD (transmit), GND (common ground).

GSM modem interfacing with microcontroller for SMS control of industrial

equipments. The sending SMS through GSM modem when interfaced with
microcontroller or PC is much simpler as compared with sending SMS through UART.

3/26/2025 75
 Interfacing GSM with LPC2148
Text message may be sent through the modem by interfacing only
three signals of the serial interface of modem with microcontroller
i.e., TxD, RxD and GND. In this scheme RTS and CTS signals of
serial port interface of GSM Modem are connected with each other.

The transmit signal of serial port of microcontroller is connected with

transmit signal (TxD) of the serial interface of GSM Modem while
receive signal of microcontroller serial port is connected with receive
signal (RxD) of serial interface of GSM Modem.

The SMS message in text mode can contain only 140 characters at
the most. It depends upon the amount of information collected from
GPS Engine that you need at the base station for tracking vehicle or
person.

3/26/2025 76
 Interfacing GSM with LPC2148
Display a text in mobile from LPC2148 Development by using GSM module through
UART. In LPC2148 Development contains two serial interfaces that are UART0 &
UART1. Here we are using UART0. The GSM modem is being interfaced with the
microcontroller LPC2148 Development for SMS communication. The SMS can be
sending and receiving for the data sharing and situation information and control.

3/26/2025 77
 Pin assignment with LPC 2148

Pin Assignments

UART DB-9 LPC2148 Processor

Connector Lines

UART0 (P1) ISP TXD-0 P0.0

PGM RXD-0 P0.1

TXD-1 P0.8
UART1 (P2)
RXD-1 P0.9

3/26/2025 78
 Interfacing of GSM Module

3/26/2025 79
 Algorithm for GSM module interfacing with LPC2148
1) Start

2) Initialize UART0 or UART1 serial interface using following instruction

PINSEL0=0X00000005; //Enable P0.0-TxD0,P0.1-RxD0
U0LCR=0X83; //8-BIT Character lenth,NO parity,1 stop bit
U0DLL=97; //Baud rate=9600@PCLK=15Mhz
U0LCR=0X03; //Dlab=0

3) Transmit different AT commands through UART module using instruction

while(!(U0LSR&0X20)); //Monitor TI flag

4) If transmission buffer is Empty, Transmit AT commands U0THR=ch;

5) Provide delay while transmitting each command.

6) To transmit a single character use PUTCH function & to transmit a string use PUTS
function

7) END
3/26/2025 80
Interfacing of LPC2148 with GSM module
 #include<lpc21xx.h> //Includes LPC2148 register
definitions #include "serial.h"
unsigned char GsmSendMsg(unsigned char *msgStr);
void DelayMs(unsigned int count);

int main(void)
{
Uart0Init();
Uart0PutS("ATE0\r\n"); //Turn echo off
DelayMs(500);
Uart0PutS("ATD9503XXXXXX;\r\n"); //replace xxxxxxxxxx with
number to call
DelayMs(20000);
Uart0PutS("ATH0\r\n"); //disconnect call
DelayMs(3000);
GsmSendMsg(“HELLO");
while(1);
}
unsigned char GsmSendMsg(unsigned char *msgStr)
{
Uart0PutS("AT+CMGF=1\r\n");//Send SMS: Select Text mode
DelayMs(100);
Uart0PutS("AT+CMGS=\"9503XXXXXX\"\r\n"); //Send SMS to mobile number
DelayMs(100);
Uart0PutS(msgStr);
DelayMs(100);
Uart0PutCh(0x1A); //CNTL + Z
DelayMs(3000);
return (1);
}

void DelayMs(unsigned int count)

{
volatile unsigned int j,k;
for (j=0;j<count;j++)
for (k=0;k<6000;k++);
}
 Global Positioning System ( GPS)
❖ The Global Positioning System, usually called GPS, is the only fully-functional
satellite navigation system. A constellation of more than two dozen GPS satellites
broadcasts precise timing signals by radio to GPS receivers, allowing them to
accurately determine their location (longitude, latitude, and altitude) in any weather, day
or night, anywhere on Earth.

❖GPS has become a vital global utility, indispensable for modern navigation on land, sea,
and air around the world, as well as an important tool for map-making and land
surveying. GPS also provides an extremely precise time reference, required for
telecommunications and some scientific research, including the study of earthquakes.
Applications
1. Military
2. Navigation
3. Location-based services
4. Location-based games
5. Aircraft passengers
6. Surveying
7. Agriculture
8. Geophysics and geology
9. 3/26/2025
Precise time reference 84
3/26/2025 85
3/26/2025 86
 GPS module interfacing:Overview
You have probably used or benefited from a GPS receiver. They are
found in most smart phones, many new automobiles, and they are
used to track commerce all over the globe. These tiny devices can
instantaneously give your exact position and time, almost anywhere
on the planet, for free! All you need is a GPS receiver, and receivers
are getting less expensive and smaller every day.

Dozens of GPS satellites, all containing extremely accurate atomic

clocks, have been launched since the late 70’s, and launches continue
to this day. The satellites continuously send data down to earth over
dedicated RF frequencies. Our pocket-sized GPS receivers have tiny
processors and antennas that directly receive the data sent by the
satellites and compute your position and time on the fly.

3/26/2025 87
GPS module interfacing:Working

GPS receivers use a constellation of satellites and ground stations to

compute position and time almost anywhere on earth.

At any given time, there are at least 24 active satellites orbiting over
12,000 miles above earth. The positions of the satellites are
constructed in a way that the sky above your location will always
contain at most 12 satellites. The primary purpose of the 12 visible
satellites is to transmit information back to earth over radio
frequency (ranging from 1.1 to 1.5 GHz). With this information and
some math, a ground based receiver or GPS module can calculate its
position and time.
3/26/2025 88
 How does a GPS receiver calculate its position and time?
The data sent down to earth from each satellite contains a few different pieces
of information that allows your GPS receiver to accurately calculate its
position and time. An important piece of equipment on each GPS satellite is an
extremely accurate atomic clock. The time on the atomic clock is sent down to
earth along with the satellite’s orbital position and arrival times at different
points in the sky. In other words, the GPS module receives a time stamp from
each of the visible satellites, along with data on where in the sky each one is
located (among other pieces of data). From this information, the GPS receiver
now knows the distance to each satellite in view. If the GPS receiver’s antenna
can see at least 4 satellites, it can accurately calculate its position and time.
This is also called a lock or a fix.
There is another piece of the global positioning system we haven’t talked
about. Along with satellites and GPS receivers, there are ground based stations
that can communicate with the satellite network and some GPS receivers. This
system is formally called the control segment and increases the accuracy of
your GPS receiver. Common systems that use the control segment to improve
accuracy are WAAS and DGPS. WAAS is common on most GPS receivers
and improves accuracy to about 5 meters. DGPS requires a specific type of
GPS receiver and gets centimetre accuracy. DGPS units are also expensive and
3/26/2025 89
tend to be larger because they require an additional antenna.
 GPS Accuracy
GPS Accuracy depends on a number of variables, most notably
signal to noise ratio (noisy reception), satellite position, weather and
obstructions such as buildings and mountains. These factors can
create errors in your perceived location. Signal noise usually creates
an error from around one to ten meters. Mountains, buildings and
other things that might obstruct the path between the receiver and the
satellite can cause three times as much error as signal noise. A GPS
receiver must be able to get a lock on 4 satellites to be able to solve
for a position. The first lock it gets allows the receiver to obtain the
almanac information and thus what other satellites it should listen
for. Although it is possible to get a position from less than 4
satellites, the margin of error of this position can be rather large.
Your most accurate read of your location comes when you have a
clear view of a clear sky away from any obstructions and under more
than four satellites. To combat these errors, a couple of different
assistants have been created.
3/26/2025 90
 Differential GPS

Another method is Differential GPS or DGPS. DGPS also uses ground or fixed GPS
stations to determine the location, but differs in that it finds the difference between both the
satellite and the ground location reading. These ground stations may be up to 200 nautical
miles from the receiver, and it is important to note that accuracy deteriorates the further you
are from the ground station. DGPS is accomplished by a ground station broadcasting a signal
which dictates the error between the actual pseudo range and the measured pseudo range. This
value is calculated by multiplying the speed of light by the time it takes the signal to travel
from the satellite to the receiver. As an example, one form of DGPS is Wide Area
Augmentation System or WAAS.
.
•A nautical mile is a unit of length used in air, marine,
and space navigation.
A nautical mile is based on the circumference of the
earth, and is equal to one minute of latitude. It is slightly
more than a statute (land measured) mile (1 nautical
mile = 1.1508 statute miles ).
3/26/2025 91
 Differential GPS

Originally developed by the FAA to assist aircraft GPS, WAAS uses a system of
specifically built ground stations. WAAS holds a specific set of accuracy standards that
ground station measurements must meet. Laterally and vertically, WAAS must be accurate
to within 7.6 meters 95% of the time. These ground stations send their measurements to
master stations which send the corrections to WAAS satellites every 5 seconds or quicker.
From the Satellite, a signal is broadcast back to the receivers on earth where the
corrections are used to improve the GPS accuracy. In some locations, WAAS is able to
provide an accuracy of 1 meter lateral and 1.5 meters vertically. While WAAS is only
present in North America, similar systems are in place in many other parts of the world

3/26/2025 92
 The NMEA 0183 Protocol
❖The National Marine Electronics Association (NMEA) is a non-profit
association of manufacturers, distributors, dealers, educational
institutions, and others interested in peripheral marine electronics
occupations. The NMEA 0183 standard defines an electrical interface
and data protocol for communications between marine instrumentation.
❖NMEA 0183 is a voluntary industry standard, first released in March of
1983. It has been updated from time to time; the latest release, currently
(August 2001) Version 3.0, July 2001, is available from the NMEA office
(www.nmea.org)
❖NMEA has also established a working group to develop a new standard
for data communications among shipboard electronic devices. The new
standard, NMEA 2000, is a bi-directional, multi-transmitter,
multi-receiver serial data network. It is multi-master and
self-configuring, and there is no central controller.
3/26/2025 93
 NMEA Output Messages
Table 1.1 – NMEA-0183 Output
Messages

3/26/2025 94
 NMEA Output Messages
1. GGA – Global Positioning System Fixed Data

$GPGGA,161229.487,3723.2475,N,12158.3416,W,1,07,1.0,9.0,M,,,,0000*18
Table 1.2 – GGA Data
Format

3/26/2025 95
 NMEA Output Messages
2. GLL – Geographic Position – Latitude/Longitude
$GPGLL, 3723.2475,N,12158.3416,W,161229.487,A*2C

3/26/2025 96
Message Formats
GPS Configuration
GPS data is displayed in different message formats over a serial interface. There are standard
and non-standard (proprietary) message formats. Nearly all GPS receivers output NMEA data.
The NMEA standard is formatted in lines of data called sentences. Each sentence contains
various bits of data organized in comma delimited format (i.e. data separated by commas).

Here’s example NMEA sentences from a GPS receiver with satellite lock (4+ satellites,
accurate position):
$GPRMC,235316.000,A,4003.9040,N,10512.5792,W,0.09,144.75,141112,,*19
$GPGGA,235317.000,4003.9039,N,10512.5793,W,1,08,1.6,1577.9,M,-20.7,M,,0000*5F
$GPGSA,A,3,22,18,21,06,03,09,24,15,,,,,2.5,1.6,1.9*3E

In above example, the GPGGA sentence contains the follow:

•Time: 235317.000 is 23:53 and 17.000 seconds in Greenwich mean time
•Longitude: 4003.9040,N is latitude in degrees. Decimal minutes, north
•Latitude: 10512.5792,W is longitude in degrees. Decimal minutes, west
•Number of satellites seen: 08
•Altitude: 1577 meters
The data is separated by commas to make it easier to read and parse by computers and
microcontrollers. This data is sent out on the serial port at an interval called the update rate.
Most receivers update this information once per second (1Hz), but more advanced receivers are
capable multiple updates per second. 5 to 20Hz is possible with modern receivers.
3/26/2025 97
 Reading GPS data
Most GPS modules have a serial port, which makes them perfect to connect to a
microcontroller or computer.
1. Connecting to a Microcontroller

Once a GPS module is powered, NMEA data (or another message format) is sent out of a
serial transmit pin (TX) at a specific baud rate and update rate, even if there is no lock. To
have your microcontroller read the NMEA data, all that is needed is to connect the TX pin of
the GPS to the RX (receive) pin on the microcontroller. To configure the GPS module, you
will need to also connect the RX pin of the GPS to the TX pin of the microcontroller.
It is common for the microcontroller to parse the NMEA data. Parsing is simply removing the
chunks of data from the NMEA sentence so the microcontroller can do something useful with
the data.

For example, the microcontroller might need to read only the altitude of your GPS.
$GPGGA,235317.000,4003.9039,N,10512.5793,W,1,08,1.6,1577.9,M,-20.7,M,,0000*5F
Instead of dealing with all of this text, the microcontroller can parse the GPGGA sentence
and end up with only the altitude (in meters).
1577
Once the microcontroller can grab the data needed, the information can be manipulated to
3/26/2025 98
create other interactions on the microcontroller.
 Reading GPS data
2. Connecting to a Computer

A simple way to see the NMEA data directly is to connect the GPS module to a
computer. For the connections, all that is needed is to power the GPS with the FTDI
basic (in this case 5V and GND), then connect the TX pin of the GPS to the RX pin on
the FTDI Basic.
Next, open a serial terminal program at the same baud rate of your GPS module. Even
if the GPS does not have a lock, you should see NMEA sentences steaming by.
$GPRMC,235316.000,A,4003.9040,N,10512.5792,W,0.09,144.75,141112,,*19
$GPGGA,235317.000,4003.9039,N,10512.5793,W,1,08,1.6,1577.9,M,-20.7,M,,0000*
5F
$GPGSA,A,3,22,18,21,06,03,09,24,15,,,,,2.5,1.6,1.9*3E

3/26/2025 99
 Configuring a GPS receiver
• To configure a GPS receiver, knowing the type of chipset your GPS is using is
very important. The GPS chipset contains a powerful processor that is
responsible for the user interface, all of the calculations, as well as analog
circuitry for the antenna. The chipset also allows for data to be sent to the GPS
receiver to configure parameters like, update rate, baud rate, sentence selection,
etc.
• In order to send commands over a serial interface to a GPS receiver, you will
need a command set or reference manual. In our case, we have used SkyTraq
chipsets.
• When communicating with a GPS receiver, most commands need to be
terminated by a checksum. In most cases, you need to XOR each of your
sentences.

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 LPC2148 Interfacing with ADC using VIC
❖Analog Digital Converter
∙Features of ADC
∙ADC Functional Block Diagram
∙ADC Registers
❖Examples
∙Embedded C Program for on-chip ADC using interrupt

3/26/2025 101
 On-chip ADC using interrupt (VIC)

Introduction to ADC
Analog to Digital Converter(ADC) is used to convert analog signal into digital
form. LPC2148 has two inbuilt 10-bit ADC i.e. ADC0 & ADC1.
ADC0 has 6 channels &ADC1 has 8 channels.

Hence, we can connect 6 distinct types of input analog signals to ADC0 and 8
distinct types of input analog signals to ADC1.

ADCs in LPC2148 use Successive Approximation technique to convert analog

signal into digital form.

This Successive Approximation process requires a clock less than or equal to

4.5 MHz. We can adjust this clock using clock divider settings.

Both ADCs in LCP2148 convert analog signals in the range of 0V to VREF

(typically 3V; not to exceed VDDA voltage level).
 Analog Digital Converter

Features of ADC
• 10 bit successive approximation analog to digital converter.
• Input multiplexing among 6 or 8 pins (ADC0 and ADC1).
• Power-down mode.
• Measurement range 0 V to VREF (typically 3 V; not to exceed VDDA voltage level).
• 10 bit conversion time 2.44 µs.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Global Start command for both converters.

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 Analog Digital Converter

3/26/2025
Functional Block 104
Diagram
 Analog Digital Converter
Block Explanation
Block Symbol Description I/O
AD0.1 Channel 1 P0.28
AD0.2 Channel 2 P0.29
AD0.3 Channel 3 P0.30
ADC0
AD0.4 Channel 4 P0.25
AD0.6 Channel 6 P0.4
AD0.7 Channel 7 P0.5
AD1.0 Channel 0 P0.6
AD1.1 Channel 1 P0.8
AD1.2 Channel 2 P0.10
AD1.3 Channel 3 P0.12
ADC1
AD1.4 Channel 4 P0.13
AD1.5 Channel 5 P0.15
AD1.6 Channel 6 P0.21
AD1.7 Channel 7 P0.22
3/26/2025 105
Register description
Register description
A/D Data Registers (ADDR0 to ADDR7, ADC0: AD0DR0 to AD0DR7
-
0xE003 4010 to 0xE003 402C and ADC1: AD1DR0 to AD1DR7- 0xE006
0010 to 0xE006 402C)
The A/D Data Register hold the result when an A/D conversion is
complete, and also include the flags that indicate when a conversion has
been completed and when a conversion overrun has occurred
 ADC Registers
1) Control Register(AD0CR)
•AD0CR is a 32-bit register.
•This register must be written to select the operating mode before A/D conversion can
occur.
•It is used for selecting channel of ADC, clock frequency for ADC, number of clocks
or number of bits in result, start of conversion and few other parameters.

RESERVE EDGE START -- PDN -- CLKS BURST CLKDIV SEL

31-28 27 26-24 23-22 21 20 19-17 16 15-8 7.0

•7-0 SEL: Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and
converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In
software-controlled mode, only one of these bits should be 1. e.g. bit 7 (10000000)
selects AD0.7 channel as analog input. In hardware scan mode, any value containing
1 to 8 one. All zeroes is equivalent to 0x01.
•These bits select ADC0 channel as analog input.
3/26/2025 112
 ADC Registers
1) Control Register

RESERVE EDGE START -- PDN -- CLKS BURST CLKDIV SEL

31-28 27 26-24 23-22 21 20 19-17 16 15-8 7.0

•15-8 CLKDIV: The APB clock (PCLK) is divided by (this value plus one) to
produce the clock for the A/D converter, which should be less than or equal to
4.5 MHz Typically, software should program the smallest value in this field that
yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a
high-impedance analog source) a slower clock may be desirable.
∙The A/D Converters on the LPC2148 is also called as The conversion speed
is selectable by the user
A/D Clock frequency= [Pclk/(CLKDIV+1)] .....................<=4.5 MHz
 ADC Registers
1) Control Register
RESERVE EDGE START -- PDN -- CLKS BURST CLKDIV SEL

31-28 27 26-24 23-22 21 20 19-17 16 15-8 7.0

Bit 16 : BURST

0 = Conversions are software controlled and require 11 clocks

1 = In Burst mode ADC does repeated conversions at the rate selected by
the CLKS field for the analog inputs selected by SEL field. It can be terminated by
clearing this bit, but the conversion that is in progress will be completed.
When Burst = 1, the START bits must be 000, otherwise the conversions will not
start.

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 ADC Registers
1) Control Register
RESERVE EDGE START -- PDN -- CLKS BURST CLKDIV SEL

31-28 27 26-24 23-22 21 20 19-17 16 15-8 7.0

•19-17 CLKS: This field selects the number of clocks used for each conversion in Burst
mode, and the number of bits of accuracy of the result in the RESULT bits of ADDR,
between 11 clocks (10 bits) and 4 clocks (3 bits).

No. of Clock cycles used per bit

CLKS field - 19-18-17
conversion
000 11 clocks cycles / 10 bit conversion
001 10 clocks/ 9 bits
010 9 clocks/ 8 bits
011 8 clocks/ 7 bits
100 7 clocks/ 6 bits
101 6 clocks/ 5 bits
110 5 clocks/ 4 bits
111 4 clocks/ 3 bits
 ADC Registers
1) Control Register

RESERVE EDGE START -- PDN -- CLKS BURST CLKDIV SEL

31-28 27 26-24 23-22 21 20 19-17 16 15-8 7.0

•Bit 20 – RESERVED

•21 PDN
∙PDN=0 The A/D converter is in power-down mode.
∙PDN=1 The A/D converter is operational.

•Bit 23:22 – RESERVED

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 1) Control Register
RESERVE EDGE START -- PDN -- CLKS BURST CLKDIV SEL

31-28 27 26-24 23-22 21 20 19-17 16 15-8 7.0

•Bit 26:24 – START

When BURST bit is 0, these bits control whether and when A/D conversion is started
000 = No start (Should be used when clearing PDN to 0)
001 = Start conversion now
010 = Start conversion when edge selected by bit 27 of this register occurs on CAP0.2/MAT0.2 pin
011= Start conversion when edge selected by bit 27 of this register occurs on CAP0.0/MAT0.0 pin
100 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.1 pin
101 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.3 pin
110 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.0 pin
111 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.1 pin
Bit 27 – EDGE
This bit is significant only when the Start field contains 010-111. In these cases,
0 = Start conversion on a rising edge on the selected CAP/MAT signal
1 = Start conversion on a falling edge on the selected CAP/MAT signal
Bit 31:28 – RESERVED
 ADC Registers
2) Global Data Register: AD0GDR (ADC0 Global Data Register)

DONE OVERRUN Reserved 10 bit A/D RESULT Reserved

31 30 29-16 15-6 5-0

AD0GDR is a 32-bit register.

This register contains the ADC’s DONE bit and the result of the most recent A/D
conversion.
Bit 5:0 – RESERVED
Bits 15:6 – RESULT
When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0
(less than or equal to VSSA) to 1023 (greater than or equal to VREF).

Analog Input 10-bit Digital output Digital Output in HEX

0V 0000 0000 00 B 000H
3.3V 1111 1111 11 B 3FFH

Bit 23:16 – RESERVED

3/26/2025 118
 ADC Registers
2) Global Data Register: AD0GDR (ADC0 Global Data Register)

DONE OVERRUN Reserved 10 bit A/D RESULT Reserved

31 30 29-16 15-6 5-0

Bit 30 – Overrun
This bit is set to 1 in burst mode if the result of one or more conversions is
lost and overwritten before the conversion that produced the result in
the RESULT bits.
This bit is cleared by reading this register.

•DONE (Bit 31)

∙DONE= 1 ;when an A/D conversion is complete.
∙D0NE=0 ;A/D conversion is in progress
For accurate results, you need to wait until this value is 1 before reading the
RESULT bits. (Please note that this value is cleared when you read this register.)
 ADC Registers
3) Status Register : AD0STAT (ADC0 Status Register) (It is read Only)

AD0STAT is a 32-bit register.

It allows checking of status of all the A/D channels simultaneously.

Bit 7:0 – DONE7:DONE0

These bits reflect the DONE status flag from the result registers for A/D channel 7 - channel 0.

Bit 15:8 – OVERRUN7:OVERRUN0

These bits reflect the OVERRUN status flag from the result registers for A/D channel 7 - channel
0.

Bit 16 – ADINT
This bit is 1 when any of the individual A/D channel DONE flags is asserted and enables ADC
interrupt if any of interrupt is enabled in AD0INTEN register.

Bit 31:17 – RESERVED

 ADC Registers
4) Global Start Register : ADGSR (A/D Global Start Register)
ADGSR is a 32-bit register.
Software can write to this register to simultaneously start conversions on both ADC

BURST (Bit 16), START (Bit <26:24>) & EDGE (Bit 27)
These bits have same function as in the individual ADC control registers i.e.
AD0CR & AD1CR. Only difference is that we can use these function for both
ADC commonly from this register.
 ADC Registers
5) Interrupt Enable : AD0INTEN (ADC0 Interrupt Enable)

AD0INTEN is a 32-bit register.

It allows control over which channels generate an interrupt when conversion is completed.

Bit 0 – ADINTEN0
0 = Completion of a A/D conversion on ADC channel 0 will not generate an
interrupt
1 = Completion of a conversion on ADC channel 0 will generate an interrupt
Remaining ADINTEN bits have similar description as given for ADINTEN0.

Bit 8 – ADGINTEN
0 = Only the individual ADC channels enabled by ADINTEN7:0 will generate
interrupts
1 = Only the global DONE flag in A/D Data Register is enabled to generate an
interrupt
 ADC Registers
6) Data Registers : AD0DR0-AD0DR7 (ADC0 Data Registers)

These are 32-bit registers.

They hold the result when A/D conversion is completed.
They also include flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.

Bit 5:0 – RESERVED

Bits 15:6 – RESULT
When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0
(less than or equal to VSSA) to 1023 (greater than or equal to VREF).
Bit 29:16 – RESERVED
Bit 30 – Overrun
This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten
before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
Bit 31 – DONE
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
 Summary: ADC Registers
Register Description
ADxCR A/D COntrol Register: Used for Configuring the ADC

A/D Global Data Register: This register contains the ADC’s DONE
ADxGDR
bit and the result of the most recent A/D conversion

ADxINTEN A/D Interrupt Enable Register

ADxDR0 - A/D Channel Data Register: Contains the recent ADC value for
ADxDR7 respective channel
A/D Status Register: Contains DONE & OVERRUN flag for all the
ADxSTAT
ADC channels
A/D Global Start Register: This address can be written (in the AD0
ADxGSR address range) to start conversions in both A/D converters
simultaneously.
 ADC Registers
6) Interrupt Enable Register
• Enables interrupt on EOC channel
Examples
1.Select ADC-0, Channel-1, Clock frequency 3.75 MHz (let PCLK
is 15 MHz), burst mode repeated conversion and 10-bit resolution.
Power-up ADC and issue start of conversion.

2. Solution: AD0CR = 0x01210302; // configure SEL, CLKDIV,

BURST CLKS & PDN bit fields set START, signal start of
conversion Select ADC–1, Channels 0 to 7, clock frequency 4.5
MHz (assume PCLK is 30 MHz), burst mode repeated
conversion, 8-bit resolution.

3/26/2025 125
 Steps for Configuring ADC
Below are the steps for configuring the LPC1768 ADC.
1. Configure the GPIO pin for ADC function using PINSEL register.
2. Enable the Clock to ADC module.
3. Deselect all the channels and Power on the internal ADC module
by setting ADCR.PDN bit.
4. Select the Particular channel for A/D conversion by setting the
corresponding bits in ADCR.SEL
5. Set the ADCR.START bit for starting the A/D conversion for
selected channel.
6. Wait for the conversion to complete, ADGR.DONE bit will be set
once conversion is over.
7. Read the 10-bit A/D value from ADGR.RESULT.
8. Use it for further processing or just display on LCD.

3/26/2025 126
 Embedded C Program for on-chip ADC using interrupt
#include<lpc21xx.h>
#include<board.h>
void timer0(void)__attribute__((interrupt("IRQ")));
void timer0(void)
{
int adcdata; *T0IR = 0X01;
while(!(*ADDR&0X80000000));///////check status of DONE bit
adcdata = (*ADDR&0X0000FFC0);
adcdata = adcdata >> 6;
q_printf("timer 0 interrupt");
q_printf(" adcdata= %x \n ",adcdata);
*VICVectAddr = 0X00; /////Holds ISR addr of active interrupt.
Writing any value indicates End of Interrupt
}

3/26/2025 127
int main() Embedded C Program for on-chip ADC using interrupt
{
//////
*PINSEL1 = *PINSEL1 & 0XFCFFFFFF;
*PINSEL1 =*PINSEL1 | 0X01000000;////////ADC0.1.....P0.28 pin as ADC
i/p
*ADCR = 0X01210302;
*VICVectCntl0 = 0X24; //////VICVectCntlx=VIQ SLOT 0,Timer0
IRQ(BITS 0 to 4),VIQ (BIT 5)
*VICIntEnable = 0X10; //////High bit enables FIQ or IRQ classified
interrupts(Enable Timer 0 IRQ/FIQ Interrupt)
*T0IR = 0X01;
*T0MCR = 0X03;
*T0MR0 = 0X00E4E1C0;
*T0TCR = 0X01; /////Enable timer
*VICVectAddr0 = (unsigned int)timer0; //////Holds ISR address of timer0
while(1);
return 0;
}
3/26/2025 128
❑ Interrupt : “An interrupt is a signal sent to the CPU which
indicates that a system event has a occurred which needs
immediate attention”.
❑ Interrupt ReQuest (IRQ) can be thought of as a special request
to the CPU to execute a function(small piece of code) when an
interrupt occurs.
❑ ISR : This function or ‘small piece of code’ is technically called
an ‘Interrupt Service Routine‘ or ‘ISR’.
❑ So when an IRQ arrives to the CPU, it stops executing the
current code and start executing the ISR. After the ISR
execution has finished the CPU gets back to where it had
stopped.
Interrupts are handled by Vectored Interrupt Controller(VIC)
LPC214x VIC
Features
● ARM PrimeCell Vectored Interrupt Controller
● 32 interrupt request inputs
● 16 vectored IRQ interrupts
● 16 priority levels dynamically assigned to interrupt requests
● Software interrupt generation
 Interrupt structure of LPC2148
❑ The VIC is a component from the ARM prime cell.
❑ VIC module is a highly optimised interrupt controller.
❑ The VIC is used to handle all the on-chip interrupt sources from
peripherals.
❑ Each of the on-chip interrupt sources is connected to the VIC on a fixed
channel: your application software can connect each of these channels to
the CPU interrupt lines (FIQ, IRQ) in one of three ways.
 Interrupt structure of LPC2148
❑ The VIC allows each interrupt to be handled as an FIQ interrupt, a
vectored IRQ interrupt, or a non vectored IRQ interrupt.
❑ FIQ is the fastest followed by vectored IRQ with non-vectored IRQ
being the slowest.
❖ LPC2148 external interrupt inputs: 4
❖ Processor and on-chip user peripherals generate interrupts
❖ LPC2148 uses ARM PrimeCell (PL190) Vectored Interrupt
Controller for managing interrupts.
❖ When interrupt occurs,
➔ VIC identifies the source of interrupts
➔ Passes requests on interrupt request pins as per the configuration
➔ If more than one interrupt occurs at a time, VIC resolves priority
❖ 32 interrupt request inputs, LPC2148 uses 22 of 32 interrupts
Block diagram of the Vectored Interrupt Controller (VIC)
ARM PrimeCell Vectored Interrupt Controller (PL190)
SFRs
• VICIntSelect (R/W) 0 = IRQ, 1 = FIQ
• VICIntEnable (R/W) Enable Selective Interrupt Source
• VICIntEnClr (R/W) Disable Selective Interrupt Source
• VICIRQStatus (R)to know the status of enabled interrupt
• VICFIQStatus (R)to know the status of enabled FIQ
• VICSoftInt to trigger a software interrupt
• VICSoftIntClear to clear software interrupt
• VICVectCntl0 to VICVectCntl15 Assign interrupt source
• VICVectAddr0 to VICVectAddr15 Assign interrupt address
• VICVectAddr Holds the address of currently active interrupt
• VICDefVectAddr Holds the address of Non-Vectored ISR
Fast Interrupt reQuest (FIQ)
❖ FIQ requests have the highest priority.
❖ Any interrupt source may be assigned as the FIQ interrupt.
❖ The VIC interrupt select register has a unique bit for each
interrupt.
❖ However setting multiple bits in the Interrupt Select Register will
enable multiple FIQ interrupt sources.
❖ On entry the interrupt source can be determined by examining the
VIC FIQ Status register and the appropriate code executed.
❖ Once you have selected an FIQ source the interrupt can be
enabled in the VIC interrupt enable register.
❖ Once an FIQ interrupt is generated, the processor will change to
FIQ mode and vector to 0x0000001C, the FIQ vector.
Leaving An FIQ Interrupt
❖ Before you exit the ISR code you must make sure that any
interrupt status flags in the peripheral have been cleared.
❖ If this is not done you will get continuous interrupts until the flag
is cleared.
Vectored IRQ
❖ Vectored IRQs have the middle priority, but only 16 of the 32
requests can be assigned to this category.
❖ The VIC provides a programmable hardware lookup table which
delivers the address of the C function to run for a given interrupt
source.
❖ Any of the 32 requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15
has the lowest.
❖ Each slot contains a vector address register and a vector control
register.
❖ For a Vectored IRQ the VIC provides a hardware lookup table for
the address of each ISR. The interrupt priority of each peripheral
may also be controlled.
❖ The Vector Control Register contains two fields: a channel field
and an enable bit.
❖ The other register in the VIC slot is the Vector Address Register.
❖ As its name suggests, this register must be initialised with the
address of the appropriate C function to run when the interrupt
associated with the slot occurs.
Leaving An IRQ Interrupt
❖ The interrupt status flags are cleared in the peripheral which
generated the request.
❖ At the end of the interrupt you must do a dummy write to the
Vector Address Register.
❖ This signals the end of the interrupt to the VIC and any pending
IRQ interrupt will be asserted.
Non-Vectored Interrupts
❖ The VIC is capable of handling 16 peripherals as vectored
interrupts and at least one as an FIQ interrupt.
❖ If there are more than 17 interrupt sources on the chip, any extra
interrupts can be serviced as non-vectored interrupts.
❖ The non-vectored interrupt sources are served by a single ISR.
❖ The address of this ISR is stored in an additional vector address
register called the default vector address register.
Leaving A Non-Vectored IRQ Interrupt
❖ As with the vectored IRQ interrupt, you must clear the peripheral
flag and write to the vector address register.
 Vectored Interrupt Controller (VIC)

▪ LPC2148 external interrupt inputs: 4 (available on 9 pins)

▪ Processor and on-chip user peripherals generate interrupts.

▪ The Vectored Interrupt Controller (VIC) takes 32 interrupt

request inputs and programmably assigns them into 3
categories, FIQ, vectored IRQ, and non-vectored IRQ.

▪ Fast Interrupt request (FIQ) requests have the highest priority.

▪ Vectored IRQs have the middle priority, but only 16 of the

32 requests can be assigned to this category. Any of the 32
requests can be assigned to any of the 16 vectored IRQ slots,
among which slot 0 has the highest priority and slot 15 has the
lowest.

▪ Non-vectored IRQs have the lowest priority

● EINT0 Input External Interrupt Input 0 - An active low/high level or
falling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power-down modes. Pins
P0.1 and P0.16 can be selected to perform EINT0 function.

● EINT1 Input External Interrupt Input 1 - See the EINT0 description

above. Pins P0.3 and P0.14 can be selected to perform EINT1 function.

● EINT2 Input ExternalInterrupt Input 2 - See the EINT0

description
above. Pins P0.7 and P0.15 can be selected to perform EINT2 function.

● EINT3 Input External Interrupt Input 3 - See the EINT0 description

above. Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3
function.
LPC2148 has a register VICDefVectAddr to which the user must
assign the address of the default ISR for handling Non
Vectored IRQs.

The difference between Vectored IRQ(VIRQ) and Non-Vectored

IRQ(NVIRQ) is that VIRQ has dedicated IRQ service routine for
each interrupt source which while NVIRQ has the same IRQ
service routine for all Non-Vectored Interrupts.

If more than one request is assigned to FIQ, the VIC ORs the
requests to produce the FIQ signal to the ARM processor.
Bit allocation for various sources of interrupts
in VIC register
VICIRQStatus(RO): IRQ Status Register. This register reads out the state of
those interrupt requests that are enabled and classified as IRQ. It does not
differentiate between vectored and non-vectored IRQs. A bit read as 1
indicates a corresponding interrupt request being enabled, classified as
IRQ, and asserted.

VICFIQStatus(RO): FIQ Status Requests. This register reads out the state of
those interrupt requests that are enabled and classified as FIQ. If more
than one request is classified as FIQ, the FIQ service routine can read this
register to see which request(s) is (are) active.

VICRawIntr(RO): Raw Interrupt Status Register. This register reads out the
state of the 32 interrupt requests / software interrupts, regardless of
enabling or classification.

VICIntEnable(R/W): Interrupt Enable Register. This register controls which

of the 32 interrupt requests and software interrupts are enabled to
contribute to FIQ or IRQ
VICIntSelect(R/W): Interrupt Select Register. This register classifies each of the
32 interrupt requests as contributing to FIQ or IRQ.

● VICIntSelect bit allocation table.

0 :The interrupt request with this bit number is assigned to the IRQ category.
1:The interrupt request with this bit number is assigned to the FIQ category.

VICIntEnClr(WO): Interrupt Enable Clear Register. This register allows software

to clear one or more bits in the Interrupt Enable register

VICSoftInt(R/W): Software Interrupt Register. The contents of this register are

ORed with the 32 interrupt requests from various peripheral functions.

VICSoftIntClear(WO): SoftwareInterrupt Clear Register. Thisregister

allows
software to clear one or more bits in the Software Interrupt register.

VICProtection(R/W): Protection enable register. Thisregister allows

limiting access to the VIC registers by software running in privileged mode.
VICVectAddr(R/W): Vector Address Register. When an IRQ interrupt
occurs, the IRQ service routine can read this register and jump to the
value read.

VICDefVectAddr(R/W): Default Vector Address Register. This register

holds the address of the Interrupt Service routine (ISR) for non-vectored
IRQs.

VICVectAddr0(R/W): Vector address 0 register. Vector Address Registers

0-15 hold the addresses of the Interrupt Service routines (ISRs) for the
16 vectored IRQ slots.

VICVectAddr1 Vector address 1 register.

Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C):

Each of these registers controls one of the 16 vectored IRQ slots. Slot 0
has the highest priority and slot 15 the lowest.
For example, the following two lines assign slot 0 to SPI0 IRQ interrupt
request(s) and slot 1 to TIMER0 IRQ interrupt request(s):
VICVectCntl0 = 0x20 | 10;

VICVectCntl1 = 0x20 | 4;

A/D Interrupt Enable Register (ADINTEN, ADC0: AD0INTEN - 0xE003

400C and ADC1: AD1INTEN - 0xE006 000C)

This register allows control over which A/D channels generate an

interrupt when a conversion is complete.

1 Completion of a conversion on ADC channel 1 will not generate an

interrupt.
2 Completion of a conversion on ADC channel 1 will generate an
interrupt
Important Note

▪ Each Peripheral in lpc2148 has only 1 IRQ associated with it.

▪ But inside each device there may be different sources which can raise an
interrupt.
▪ Like the TIMER0 peripheral has 4 match + 4 capture registers and any
one or more of them can be configured to trigger an interrupt.
▪ Hence such devices have a dedicated interrupt register which contains a
flag bit for each of these source(For Timer block its ‘T0IR’).
▪ So , when the ISR is called first we need to identify the actual source of the
interrupt using the Interrupt Register and then proceed accordingly.
▪ Also just before , when the main ISR code is finished we also need to
acknowledge or signal that the ISR has finished executing for the current
IRQ which triggered it.
▪ This is done by clearing the flag(i.e the particular bit) in the device’s
interrupt register and then by writing a zero to VICVectAddr register
which signifies that interrupt ISR has finished execution successfully.
LPC2148 Interfacing with EEPROM using I2C

❖I2C Module
1. Features of I2C module
2. Applications
3. I2C Bus Configuration
4. Pin Description
5. I2C Registers
❖EEPROM interfacing with LPC2148
1. Algorithm for the Interfacing

3/26/2025 157
 I2C-Bu
The I2C bus was designeds:by Philips in the early ’80s to allow easy
communication between components which reside on the same circuit
board. Philips Semiconductors migrated to NXP in 2006.

The name I2C translates into “Inter IC”. Sometimes the bus is called
IIC or I²C bus.

The original communication speed was defined with a maximum of

100 kbit per second and many applications don’t require faster
transmissions.
For those that do there is a 400 kbit fastmode and – since 1998 – a high
speed 3.4 Mbit option available. Recently, fast mode plus a transfer rate
between this has been specified. Beyond this, there is the ultra fast
mode UFM, but it frankly is no real I2C bus.

3/26/2025 158
 I2C-Bu
s:
I2C is not only used on single boards but also to connect components
which are linked via cable. Simplicity and flexibility are key
characteristics that make this bus attractive to many applications.

Most significant features include:

1. Only two bus lines are required
2. No strict baud rate requirements like for instance with RS232, the
master generates a bus clock
3. Simple master/slave relationships exist between all components
Each device connected to the bus is software-addressable by a unique
address
4. I2C is a true multi-master bus providing arbitration and collision
detection
 I2C-Bu
s:
I2C stands for Inter-Integrated Circuit and also sometimes also referred as
TWI i.e. Two Wire Interface since it uses only 2 wires for data transmission
and synchronization.
The two wires of I2C Bus consists of:
1. Data Line which is SDA i.e. Serial Data
2. Clock Line which is SCL i.e. Serial Clock
 I2C-Bu
s:
I2C bus is a Byte Oriented bus. Only a byte can be transferred at a time.
Communication(Write to & Read from) is always initiated by a Master. The Master first
sends a START condition and then writes the Slave Address(SLA) and the Direction
bit(Read=1/Write=0) on bus and the corresponding Slave responds accordingly.
Format for I2C communication protocol is given as:
 I2C-Bu
❖I2C (Inter-Integrated Circuit,
s: eye-squared-C) and is alternatively known
as I2C or IIC. It is a synchronous, multi-master, multi-slave, packet
switched, single-ended, serial communication bus invented in 1982 by Philips
Semiconductors. It is widely used for attaching lower-speed peripheral ICs to
processors and microcontrollers in short-distance, intra-board communication.

❖Several competitors, such as Siemens, NEC, Texas

Instruments, STMicroelectronics, Motorola, Nordic Semiconductor and Intersil,
have introduced compatible I2C products to the market since the mid-1990s.

3/26/2025 162
 I2C-Bu
s:
The I2C block in LPC2148 and other LPC2100 series ARM7 MCUs can be
configured as either Master, Slave or both Master & Slave. It also features a
programmable clock which aids in using different transfer rates as required. The I2C
block in LPC214x supports speeds up to 400kHz.

I2C has 4 operating modes:

1.Master Transmitter mode
2.Master Receiver mode
3.Slave Transmitter mode
4.Slave Receiver mode

I2C works in two modes namely,

•Master Mode
Master is responsible for generating clock and initiating communication
•Slave Mode
Slave receives the clock and responds when addressed by the Master
 I2C-Bu
s:

Two wires of the I2C interface are SDA (serial data) and SCL (serial clock).
•SDA is Serial Data wire used for data transfer in between master and slave
•SCL is Serial Clock wire used for clock synchronization. Clock is provided
by the master

There are two types of data transfer possible on I2C interface depending on
Read/Write operation i.e.
Data transfer from Master Transmitter to Slave Receiver and
Data transfer from Slave Transmitter to Master Receiver
 LPC2148 Interfacing with EEPROM using I2C
I2C Module
Features of I2C module
1. Standard I2C compliant bus interfaces that may be configured as Master, Slave,
or Master/Slave.
2. Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
3. Programmable clock to allow adjustment of I2C transfer rates.
4. Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus.
5. Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
6. Bidirectional data transfer between masters and slaves.
7. The I2C bus may be used for test and diagnostic purposes.
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 LPC2148 Interfacing with EEPROM using I2C
Applications
Interfaces to external I2C standard parts
1. Serial RAMs
2. LCDs
3. Tone generators
I2C Bus Configuration

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 LPC2148 Interfacing with EEPROM using I2C

Pin Description

Pin Type Description LPC2148 Pins

SDA0/1 Input/output I2C Serial Data P0.3 and P0.14

SCL0/1 Input/output I2C Serial Clock P0.2 and P0.11

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 LPC2148 Interfacing with EEPROM using I2C

Pin Description
LPC2148 I2C Pins

SCL0: - Serial Clock pin of I2C0.

SDA0: - Serial Data pin of I2C0.
SCL1: - Serial Clock pin of I2C1.
SDA1: - Serial Data pin of I2C1
 LPC2148 Interfacing with EEPROM using I2C
Depending on the state of the direction bit (R/W), two types of data transfers are
possible on the I2C bus:
• Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the master is the slave address. Next follows a number
of data bytes. The slave returns an acknowledge bit after each received byte.

• Data transfer from a slave transmitter to a master receiver.

The first byte (the slave address) is transmitted by the master. The slave then returns
an acknowledge bit. Next follows the data bytes transmitted by the slave to the
master.
The master returns an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is returned. The
master device generates all of the serial clock pulses and the START and STOP
conditions. A transfer is ended with a STOP condition or with a repeated START
condition.
Since a repeated START condition is also the beginning of the next serial transfer,
the I2C bus will not be released.
 LPC2148 Interfacing with EEPROM using I2C
I2C Registers
Summary of I2C Registers

Sr. Generic Reset I2Cn Register name &

Description Access
No Name value Address

I2C Control Set Register. When a one is written to a I2C0CONSET - 0xE001

bit of this register. the corresponding bit in the I2C C000
1 I2CONSET R/W 0x00
control register is set. Writing a zero has no effect on I2C1CONSET - 0xE005
the corresponding bit in the I2C control register. C000
I2C Status Register. During I2C operation, this I2C0STAT - 0xE001 C0004
2 I2STAT register provides detailed status codes that allow RO 0xF8
software to determine the next action needed. I2C1STAT - 0xE005 C004

I2C Data Register. During master or slave transmit

mode. data to be transmitted is written to this register. I2C0DAT - 0xE001 C008
3 I2DAT R/W 0x00
During master or slave receive mode, data that has I2C1DAT - 0xE005 C008
been received may be read from this register.
I2C Slave Address Register. Contains the 7 bit slave
address for operation of the I2C interface in slave I2C0ADR - 0xE001 C00C
4 I2ADR mode and is not used in master mode. The least R/W 0x00
significant bit determines whether a slave responds to I2C1ADR - 0xE005 C00C
3/26/2025 the general call address. 170
 LPC2148 Interfacing with EEPROM using I2C
I2CxCONSET Register
8-bit Register
Bits 7 6 5 4 3 2 1 0
Symbol - I2CEN STA STO SI AA - -

8 bits Explained
Bit Symbol Description
0-1 -- Reserved
Assert Acknowledge
2 AA
AA=1; request an acknowledge
I2C Serial Interrupt
3 SI
SI=1; indicate state change
STOP
4 STO
STO=1; sends stop condition
START
5 STA
STA=1; sends START condition
6 I2CEN I2CEN=1; I2C interface enable
7 - Reserved
3/26/2025 171
 I2Cx Registers

1) I2C0CONSET (8 bit) :
I2C control set register: The bits in this register control the operation of the I2C interface. Writing a 1 to a bit of this
register causes the corresponding bit in the I2C control register(inside I2C block) to be set. Writing a 0 has no effect. This is
a Read-Write register.

1.Bits[0 & 1] : Reserved

2.Bit 2 – AA – Assert Acknowledge Flag : When this bit is set to 1, an acknowledge (Logic low on SDA) will be returned
when a data byte has been received in the master receiver mode. Similarly when AA is set to 0, a not acknowledge (Logic
low on SDA) will be returned when a data byte has been received in the master receiver mode.

3.Bit 3 – SI – I2C Interrupt Flag : This bit is set whenever the I2C state changes(Except for state code 0xF8). When SI is
set the Low Period of the serial clock is stretched which is also termed as clock stretching. When SCL is HIGH, its not
affected by the state of SI flag. SI must be reset using I2CONCLR register every time.

4.Bit 4 – STO – STOP Flag : When this bit is set to 1 the I2C interface will send a STOP condition.

5.Bit 5 – STA – START Flag : When this bit is set to 1 the I2C interface is forced to enter Master mode and send a START
Condition or send a Repeated START if its already in Master mode.

6.Bit 6 – I2EN – I2C interface Enable : This bit is used to Enabled or Disable the I2C interface. When set to 1 the I2C
interface is enabled and when set to 0 the I2C interface is disabled.

7.Bit 7 – Reserved.
I2Cx Registers

2) I2C0CONCLR (8 bit) – I2C control clear register. This register is used to clear bits in I2C0CONSET
register. Writing 0 no effect. The bit locations are same as that of I2C0CONSET register given above. Its a
Write only register.

3) I2C0STAT (8 bit) – This gives the current state of I2C interface in form of state codes. This is a read
only register.

4) I2C0DAT (8 bit) – This register contains the data that is to be transmitted or the latest received data.
Data in this register is always shifted from right to left i.e. the first bit to be transmitted is the MSB (bit 7),
and after a byte has been received, the first bit of received data is located at the MSB of I2C0DAT.

5) I20SCLH (16 bit) – This register is used to store the High time period of the SCL pulse.

6) I20SCLL (16 bit) – This register is used to store the Low time period of the SCL pulse.

7) I2C0ADR (8 bit) – I2C Slave Address register : Not applicable for master mode. Used to store the
address in slave mode.
I2Cx Registers
I2Cx Registers
 LPC2148 Interfacing with EEPROM using I2C
Algorithm for the Interfacing
1. Start
2. Initialize I2C bus interface
PINSEL0=0X10400050; //Configure P0.11-SCL1 & P0.14-SD1
I2CSCLH=150;
I2CSCLL=150; //SET I2C frequency=[Pclk/(I2CSCLL+I2CSCH)]
3. Transmit the slave address(Page address, Page offset, No. of bytes)
4. Enable I2C bus interface
I2CCONSET=0X40;////I2CEN=1\
5. Master (LPC2148) will transmit START signal
I2CCONSET=0X20;//STA=1

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 LPC2148 Interfacing with EEPROM using I2C
Algorithm for the Interfacing

6. Transmit slave address (7-bit address, R/W=0; write operation)

7. Wait for acknowledgement
8. Transmit Page address and page offset at which data is to be written
9. Wait for acknowledgment
10. Transmit data using I2CDAT register
11. Wait for acknowledge
12. After successful transmission of data , master will transmit STOP condition
I2CCONSET=0X10;//STO=1
14. Disable I2C interface
I2CCONCLR=0X40; //I2CENC=1
15. END

3/26/2025 177
 I2C operating modes

Master Transmitter mode:

In this mode data is transmitted from master to slave. Before the master
transmitter mode can be entered, the I2CONSET register must be
initialized as shown in Table. I2EN must be set to 1 to enable the I2C
function.
● The I2C interface will enter master transmitter mode when software
sets the STA bit.
● The I2C logic will send the START condition as soon as the bus is
free.
● After the START condition is transmitted, the SI bit is set, and the
status code in the I2STAT register is 0x08.
● This status code is used to vector to a state service routine which
will load the slave address and Write bit to the I2DAT register, and
then clear the SI bit.
● SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register.
● The STA bit should be cleared after writing the slave address.
Master Receiver mode

● In the master receiver mode, data is received from a slave transmitter.

The transfer is initiated in the same way as in the master transmitter
mode.

● When the START condition has been transmitted, the interrupt service
routine must load the slave address and the data direction bit to the I2C
Data Register (I2DAT), and then clear the SI bit.

● In this case, the data direction bit (R/W) should be 1 to indicate a

read.
● When the slave address and data direction bit have been
transmitted and an acknowledge bit has been received, the SI bit is set,
and the Status Register will show the status code.

● For master mode, the possible status codes are 0x40, 0x48, or 0x38.

● For slave mode, the possible status codes are 0x68, 0x78, or 0xB0.
 The LSB of I2ADR is the general call bit. When this bit is set, the
general call address (0x00) is recognized.
Software must set values for the registers I2SCLH and I2SCLL to
select the appropriate data rate and duty cycle. I2SCLH defines the
number of PCLK cycles for the SCL high time, I2SCLL defines the
number of PCLK cycles for the SCL low time. The frequency is
determined by the following formula (fPCLK being the frequency of
PCLK)
 Two-wire Serial
EEPROM
512K (65,536 x 8)

The AT24C512 provides 524,288

bits of serial electrically erasable
and programmable
read only memory (EEPROM)
organized as 65,536 words of 8
bits each. The device’s
cascadable feature allows up to
four devices to share a common
two-wire bus. The
device is optimized for use in
many industrial and commercial
applications where low power
and low-voltage operation are
essential.
 LPC2148 Interfacing with EEPROM using I2C
EEPROM interfacing with LPC2148

3/26/2025 187
On-chip DAC for waveform generation
 DAC
▪10 bit digital to analog converter
▪ Power-down mode

Pin description
 DAC Register (DACR)

VAOUT = (VALUE * VREF )/1024

http://www.ocfreaks.com/lpc2148-dac-programming-tutorial/
 LPC2148-Interfacing-with-on-chip-DAC

•Features of DAC
•Digital to Analog Control Register (DACR)
∙Interfacing Diagram
∙Embedded C Program

3/26/2025 191
 Features of DAC

•LPC2148 has one 10-bit DAC

•Settling time software selectable
•DAC peripheral has only one register, DACR
•It contains 10-bit value for conversion in bit[15:6] position

3/26/2025 192
 LPC2148-Interfacing-with-on-chip-DAC

3/26/2025 193
 Introduction to DAC

Digital to Analog Converter (DAC) are mostly used to generate analog signals (e.g.
sine wave, triangular wave etc.) from digital values.

•LPC2148 has 10-bit DAC with resistor string architecture. It also works in Power
down mode.

•LPC2148 has Analog output pin (AOUT) on chip, where we can get digital value in
the form of Analog output voltage.

•The Analog voltage on AOUT pin is calculated as ((VALUE/1024) * VREF).

Hence, we can change voltage by changing VALUE(10-bit digital value) field
in DACR (DAC Register).

•e.g. if we set VALUE = 512,

then, we can get analog voltage on AOUT pin as ((512/1024) * VREF) = VREF/2.
 LPC2148 DAC Block
ARM7 LPC2148 MCU incorporates a 10 bit DAC and provides
buffered analog output. As per the datasheet, it is implemented
as a string DAC which is the most simplest form of DAC
consisting of resistors in series where N = no. of bits which
simply forms a Kelvin-Varley Divider.
LPC214x DAC has only 1 output pin, referred to as AOUT. The
Analog voltage at the output of this pin is given as:
Aout= VALUE/1024 * VREF.

Where VALUE is the 10-bit digital value which is to be

converted into its Analog counterpart and VREF is the input
reference voltage.

3/26/2025 196
 DAC Pin Description

DAC Pin Description

Pin Type Description
Analog Output. After the selected settling time after the
AOUT
Output DACR is written with a new value, the voltage on this
(P0.25)
pin (with respect to VSSA) is VALUE/1024 * VREF.
Voltage Reference. This pin provides a voltage reference
VREF Reference
level for the D/A converter.
Analog Power and Ground. These should be nominally
VDDA, VSSA Power the same voltages as V3 and VSSD, but should be isolated
to minimize noise and error.

3/26/2025 197
 Digital to Analog Control Register (DACR)
31-17 16 15-6 5-0
Reserved BIAS 10-bit Digital Value Reserved

DAC Register (DACR - address OxE006 C000) Bit Description

Reset
Bit Symbol Value Description
value
Reserved, user software should not write ones to reserved
5:0 - NA
NA bits. The value read from a reserved bit is not defined.

After the selected settling time after this field is written

15:6 VALUE with a 0 new VALUE, the voltage on the AOUT pin (with 0
respect to VssA ) is VALUE/1024 * VREF.
The settling time of the DAC is 1 µs max, and the
0 0
maximum 0 current is 700 µA.
16 BIAS
The settling time of the DAC is 2.5 µs and the maximum
1
current is 350 µA.
Reserved, user software should not write ones to reserved
31:17 - NA
NA bits. The value read from a reserved bit is not defined.
3/26/2025 198
 Resolution, Accuracy and Settling time with respect to DAC.

Resolution :
•The resolution of a converter is the smallest change in voltage which may be produced at the
output (or input) of the converter. For example, an 8-bit D/A converter has 2^8-1=255 equal
intervals. Hence the smallest change in output voltage is(1/255) of the full scale output range.
•Resolution should be high as possible. It depends on the number of bits in the digital input applied
to DAC. Higher the number of bits, higher is the resolution.
•It can also be defined as the ratio of change in analog output voltage resulting from a change of 1
LSB at the digital input.
For n-bit DAC,

Accuracy :
•Absolute accuracy is the maximum deviation between the actual converter output and the
ideal converter output.
•Relative accuracy is the maximum deviation after gain and offset errors have been removed.

Settling time :
•Settling time represents the time it takes for the output to settle within a specified band ±(1/2)
LSB of its final value, after the change in digital input.
•It should be as small as possible.
 ARM7 LPC2148 DAC example
As it can been seen, programming the DAC block is very straight forward. We
just need to select DAC function for P0.25 pin and feed a 10-bit value which
needs to be converted into its Analog form. Lets see a basic LPC2148 DAC
example. For most development boards VREF will be connected to VCC using
some form of noise isolation. In this DAC example, we will be changing the
output from 0V to VREF and then falling back to 0V in steps of 10ms. This DAC
program will basically output a sawtooth waveform. We will be using BIAS = 0
i.e. settling time of 1us. You can connect an Oscilloscope or a Multimeter
between P0.25 and GND to check the changing analog output. Since the output is
buffered you can drive an LED from AOUT but it won’t glow until it reaches its
forward bias voltage of around 1.7 Volts. So, keep this in mind when checking for
analog output using an LED.

3/26/2025 200
 Programming Steps

•First, configure P0.25/AOUT pin as DAC output using PINSEL Register.

•Then set settling time using BIAS bit in DACR Register.

•Now write 10-bit value (which we want to convert into analog form) in VALUE field of

DACR Register.
 DAC register Configuration
Configure DAC register for generating with 3.3V VREF & Select 700
microseconds settling time.
1.0V,
2.1.65V,
3.3.3V
Formula:
AOUT= VREF * (10 bit Digital Value/Resolution)
Solution:
1.DACR = 0x00010000; //AOUT = 0V
2.DACR = 0x00018000; //AOUT = 1.65V
3.DACR = 0x0001FFC0; //AOUT = 3.3 V
Draw DAC interfacing diagram with LPC2148. Also write program
for triangular waveform generation

3/26/2025 202
 DAC Interfacing Diagram

3/26/2025 203
Configuring internal DAC of LPC2148 for Generation of Triangular waveform
Embedded C Program
#include"LPC214x.h"
#define DACPinMask 1 << 19
#define DAC_DataMask 0x0000FFC0
#define DataShift 1<<6
void DACInit(void)
{
int i;
i = PINSEL1;
i = (i & 0xFFF3FFFF ); //Set P0.25 as AOUT Pin for analog output
PINSEL1 = (i | DACPinMask);
DACR = 1 << 16 ; //set the settling time to 2.5us and max current to 300uA
}
void delay(unsigned int time)
{
unsigned int i,j;
for(i = 0; i < time ;i++ )
{
for(j = 0; j < 10000 ; j++);
}
}
3/26/2025 204
 Configuring internal DAC of LPC2148 for Generation of Triangular waveform
Embedded C Program
int main(void)
{
int i;
DACInit(); // initialsie the DAC interface
while(1)
{
for(i = 0 ; i < 1024 ;i++ ) // positive ramp of triangular waveform
{
DACR = ( DAC_DataMask & (i << DataShift));
delay(2);
}
for(i = 1023 ; i > 0 ;i-- ) //negative ramp of triangular waveform
{
DACR = ( DAC_DataMask & (i << DataShift));
delay(2);
}
}
return 0;
}

3/26/2025 205
DHT 11 Humidity & Temperature Sensor
DHT11 Temperature & Humidity Sensor features a temperature
& humidity with a calibrated digital signal output

DHT 11 Sensor
Technical Specifications
Interfacing with microcontroller
 DHT11 Sensor

DHT11 is a single wire digital humidity and temperature sensor, which provides
humidity and temperature values serially.

It can measure relative humidity in percentage (20 to 90% RH) and temperature in
degree Celsius in the range of 0 to 50°C.

It has 4 pins of which 2 pins are used for supply, 1 is not used and the last one is used
for data.

The data pin is the only pin used for communication. Pulses of different TON and
TOFF are decoded as logic 1 or logic 0 or start pulse or end of the frame.
 Overall Communication Process

•When MCU sends a start signal, DHT11 changes from the low-
power-consumption mode to the running-mode, waiting for MCU
completing the start signal.

•Once it is completed, DHT11 sends a response signal of 40-bit data

that include the relative humidity and temperature information to
MCU.

•Users can choose to collect (read) some data.

•Without the start signal from MCU, DHT11 will not give the response
signal to MCU.

•Once data is collected, DHT11 will change to the

lowpower- consumption mode until it receives a start signal from
MCU
Code:
https://www.instructables.com/Measuring-Humidity-Using-
Sensor-DHT11/
 Interfacing Diagram

Future Technology Devices International

Example
Let’s see the example for Reading temperature and humidity from DHT11 sensor.
Here, the Data Pin of DHT11 is connected to P0.4 of LPC2148. UART0 is used for displaying
data on a serial monitor on a PC/laptop.

Programming Steps
•Initialize UART0
•Make the pin connected to the sensor data pin as an output pin and transmit a Start pulse.
•Make the pin connected to the sensor data pin as an input pin and receive the Response pulse
from the sensor.
•Once the response pulse is received, receive 40-bit data from the sensor.
•Display the received data on a serial terminal using UART0. In the case of checksum error, an
error indication is also displayed.
 Interfacing of LPC2148 with servomotor

•A Servo Motor is a type of DC Motor (or AC Motor) that is used for precision linear or
angular positioning. A simple DC Servo Motor consists of a DC Motor, position sensor and a
feedback network that all combine and produce a very high accurate movement.

•Servo Motors aren’t used for continuous rotation like normal DC Motors. They are often
used in closed loop position control applications. One of the best application of the servo
motor is the robotic hand movement or tilt or pan movement of a CCTV camera.

•Even though stepper motors are also used for accurate position control, the main advantage
of servo motors over stepper motors is the power consumption. After achieving a desired
position, the servo motor stops consuming power.

•But in case of a stepper motor, after moving to a desired position, the stepper motor draws
power to lock itself to that position. Hence, servo motors have the advantage in low power
devices.
What is a Servo Motor?
A servo motor is a type of motor that can rotate with great precision.
Normally this type of motor consists of a control circuit that provides feedback on the
current position of the motor shaft, this feedback allows the servo motors to rotate
with great precision. If you want to rotate an object at some specific angles or
distance, then you use a servo motor
A Servo Motor is a combination of DC motor, position control system and gears. Servo motor’s rotation
is controlled by applying a PWM signal to it, width of the PWM signal decides the rotation angle and
direction of the motor. SG90 Servo Motor is one of the popular and cheapest one. SG90 is a 180
degree servo. So with this servo we can position the axis from 0-180 degrees:
•Operating Voltage: +5V
•Gear Type: Plastic
•Rotation Angle: 0 to 180 deg
•Weight: 9gm
•Torque: 2.5kg/cm

https://circuitdigest.com/article/servo-motor-working-and-basics
 • Servo motor works on PWM (Pulse width modulation) principle, means
its angle of rotation is controlled by the duration of applied pulse to its
Control PIN.

For every 20 milliseconds Servo motor checks the pulse. So, adjust the pulse width of the
signal to rotate the motor’s shaft.
•1 ms (1 millisecond) pulse width for rotation of servo to 0 degree
•1.5ms pulse width for rotation to 90 degree (neutral position)
•2 ms pulse width for rotation of servo to 180 degree.
PWM working of LPC2148
Understanding the Program

There are two main aspects of the program for Servo Motor interfacing with LPC2148: Generation of Clock
signal using PLL Module and Generation of PWM signal using PWM generator. First, we see the generation
of clock using PLL. The system clock CCLK and peripheral clock PCLK are set to user preferred values
using the on – chip PLL of the LPC2148. The limit of the clock signal frequency for LPC2148 MCU is 60
MHz So, using the following lines of code in the program, we can generate a 60 MHz CCLK and a 60 MHz
PCLK. A detailed information and tutorial about PLL in LPC2148 can be found here. First, we need to
enable the PLL0 module and set the multiplier and divider values. For that, the following commands can be
used.

PLL0CON = 0x01;
PLL0CFG = 0x24;
Next step is to lock these multiplier and divider values using a feed sequence.
PLL0FEED = 0xAA;
PLL0FEED = 0x55;
Now wait for the PLL to lock to the values and connect the PLL module.
while (! (PLL0STAT & 0x00000400));
PLL0CON = 0x03;
Once again, lock the values with feed sequence and also enable the PCLK to same frequency as CCLK.
PLL0FEED = 0xAA;
PLL0FEED = 0x55;
VPBDIV = 0x01;
With these instructions, the CCLK and PCLK are set at 60 MHz using the PLL0 module.
Next step is to initialize the PWM Module and generate PWM signal
PWMPCR = 0x0; //Selecting Single Edge PWM (it is selected by default)
PWMPR = PWMPRESCALE-1; // PWMPRESCALE=60 for 1 micro-second resolution
PWMMR0 = 10000; // Duration of the period is set to 10 ms
PWMMR5 = 2500; // Pulse duration is set to 2.5 ms
PWMMCR = (1<<1); // PWMTC is reset on PWMMR0 match
PWMLER = (1<<5) | (1<<0); // update MR0 and MR5
PWMPCR |= (1<<13); // PWM output is enabled
PWMTCR = (1<<1) ; //Reset PWM TC & PR
PWMTCR = (1<<0) | (1<<3); // Finally, enable counters and PWM Mode
With the above mentioned commands, the PWM5 is set and generates PWM signal. Final step
is to control the Pulse duration with the help of buttons.
If button connected to P0.15 is pushed, the duty cycle should be 50%. So, the following code
will do that.
if( !((IO0PIN) & (1<<15)) ) // Check P0.15
{
PWMMR5 = 5000; //T-ON=50%
PWMLER = (1<<5); //Update Latch Enable bit for PWMMR5
#include
<lpc214x.h>

#define PWMPRESCALE 60

int main(void)
{
PLL0CON=0x01;
PLL0CFG=0x24;
PLL0FEED=0xaa;
PLL0FEED=0x55;
while(!(PLL0STAT & 0x00000400));
PLL0CON=0x03;
PLL0FEED=0xaa;
PLL0FEED=0x55;
VPBDIV=0x01;
PINSEL1=0x00000400;
PWMPCR = 0x0;
PWMPR = PWMPRESCALE-1;
PWMMR0 = 10000;
PWMMR5 = 2500;
PWMMCR = (1<<1);
PWMLER = (1<<5) | (1<<0);
PWMPCR |= (1<<13);
PWMTCR = (1<<1) ;
PWMTCR = (1<<0) | (1<<3);

IODIR0=IODIR0 & ((1<<16)|(1<<15));

IODIR1=IODIR1 & ((1<<16)|(1<<17));
 while(1)
{
if( !((IO0PIN) & (1<<16)) ) // Check P0.1
{
PWMMR5 = 2500;
PWMLER = (1<<5);
}
else if( !((IO0PIN) & (1<<15)) )
{
PWMMR5 = 5000;
PWMLER = (1<<5);
}
else if( !((IO1PIN) & (1<<16)) )
{
PWMMR5 = 7500;
PWMLER = (1<<5);
}
else if( !((IO1PIN) & (1<<17)) )
{
PWMMR5 = 10000;
PWMLER = (1<<5);
}
}
//return 0;
}
THANK YOU