MODULE-4

Exception and Interrupt Handling:

Exception handling, ARM processor exceptions and modes, vector
table, exception priorities, link register offsets, interrupts, assigning interrupts,
interrupt latency, IRQ and FIQ exceptions, basic interrupt stack design and
implementation.
Firmware:
Firmware and bootloader, ARM firmware suite, Red Hat redboot,
Example: sandstone, sandstone directory layout, sandstone code structure.

Textbook 1: Chapter 9.1 and 9.2, Chapter 10

What is exception?
An exception is any condition that needs to halt the normal sequential
execution of instructions.
Examples are
 when the ARM core is reset
 when an instruction fetch or memory access fails
 when an undefined instruction is encountered
 when a software interrupt instruction is executed or
 when an external interrupt has been raised.
List different ARM processor exceptions and associated modes.
Table 9.1 lists the ARM processor exceptions. Each exception causes the
core to enter a specific mode. In addition, any of the ARM processor
modes can be entered manually by changing the CPSR.
When an exception causes a mode change, the core automatically
 saves the cpsr to the spsr of the exception mode.
 saves the pc to the lr of the exception mode.
 sets the cpsr to the exception mode.
 sets the pc to the address of the exception handler.

Figure 9.1 shows a simplified view of exceptions and associated modes

What is Vector table? Explain briefly.
Vector table—a table of addresses that the ARM core branches to when an
exception is raised. These addresses commonly contain branch instructions
of one of the following forms:
B <address> :
This branch instruction provides a branch relative from the pc.
LDR pc, [pc, #offset] :This load register instruction loads the handler
address from memory to the pc.
MOV pc, #immediate:
This move instruction copies an immediate value into the pc.
Explain exception priority mechanism in ARM7 Microcontroller.
Exceptions can occur simultaneously, so the processor has to adopt a priority
mechanism.
Table 9.3 shows the various exceptions that occur on the ARM processor and their
associated priority level.
For instance, the Reset exception is the highest priority and occurs when power is
applied to the processor. Thus, when a reset occurs, it takes precedence over all other
exceptions.
Similarly, when a Data Abort occurs, it takes precedence over all other exceptions apart
from a Reset exception.
The lowest priority level is shared by two exceptions, the Software Interrupt and
Undefined Instruction exceptions.
Certain exceptions also disable interrupts by setting the I or F bits in the cpsr, as shown
in Table 9.3.
Each exception is dealt with according to the priority level set out in Table 9.3.
Explain the function of LINK REGISER(R14).
When an exception occurs, the link register is set to a specific address
based on the current pc. For instance, when an IRQ exception is raised, the
link register lr(r14) points to the last executed instruction plus 8.
Care has to be taken to make sure the exception handler does not corrupt
lr because lr is used to return from an exception handler.
The IRQ exception is taken only after the current instruction is executed,
so the return address has to point to the next instruction, or lr − 4. Table
9.4 provides a list of useful addresses for the different exceptions.
The next two examples show different methods of returning from an IRQ
or FIQ exception handler.
Example-1
This example shows that a typical method of returning from an IRQ and FIQ handler is
to use a SUBS instruction:
handler
<handler code>
...
SUBS pc, r14, #4 ; pc=r14-4
Because there is an S at the end of the SUB instruction and the pc is the destination
register, the cpsr is automatically restored from the spsr register
Example-2
This example shows another method that subtracts the offset from the link register r14
at the beginning of the handler.
handler
SUB r14, r14, #4 ; r14-=4
...
<handler code>
...
MOVS pc, r14 ; return
After servicing is complete, return to normal execution occurs by moving the link
register r14 into the pc and restoring cpsr from the spsr.
Explain different steps require to handle exception in ARM Microcontroller.
Here are the steps that the ARM processor does to handle an exception:
• Preserve the address of the next instruction.
• Copy CPSR to the appropriate SPSR, which is one of the banked registers for each
mode of operation.
• Force the CPSR mode bits to a value depending on the raised exception.
• Force the PC to fetch the next instruction from the exception vector table.
• Now the handler is running in the mode associated with the raised exception.
• When handler is done, the CPSR is restored from the saved SPSR.
• PC is updated with the value of (LR – offset) and the offset value depends on the type
of the exception.
And when deciding to leave the exception handler, the following steps occurs:
• Move the Link Register LR (minus an offset) to the PC.
• Copy SPSR back to CPSR, this will automatically changes the mode back to the
previous one.
• Clear the interrupt disable flags (if they were set).
What is interrupt? Explain briefly.
The interrupt is a signal generated by hardware or software when a process or an event
needs immediate attention. It alerts the processor to a high-priority process requiring
interruption of the current working process.
There are two types of interrupts available on ARM processor.
The first type is the interrupt caused by external events from hardware peripherals and
the second type is the SWI instruction.
The ARM core has only one FIQ pin, that is why an external interrupt controller is
always used so that the system can have more than one interrupt source which are
prioritized with this interrupt controller and then the FIQ interrupt is raised and the
handler identifies which of the external interrupts was raised and handle it.
How interrupts are assigned in ARM Microcontroller ? Explain briefly.

It is up to the system designer who can decide which hardware peripheral can produce
which interrupt request. By using an interrupt controller we can connect multiple
external interrupts to one of the ARM interrupt requests and distinguish between
them.
There is a standard design for assigning interrupts adopted by system designers:
• SWIs are normally used to call privileged operating system routines.
• IRQs are normally assigned to general purpose interrupts like periodic timers.
• FIQ is reserved for one single interrupt source that requires fast response time, like
DMA or any time critical task that requires fast response.
What is interrupt latency? Explain briefly.
Interrupt latency is the interval of time between from an external interrupt signal being
raised to the first fetch of an instruction of the ISR of the raised interrupt signal.

System architects must balance between two things, first is to handle multiple interrupts
simultaneously, second is to minimize the interrupt latency.

Minimization of the interrupt latency is achieved by software handlers by two main

methods, the first one is to allow nested interrupt handling so the system can respond to
new interrupts during handling an older interrupt. This is achieved by enabling
interrupts immediately after the interrupt source has been serviced but before finishing
the interrupt handling.
The second one is the possibility to give priorities to different interrupt sources; this is
achieved by programming the interrupt controller to ignore interrupts of the same or
lower priority than the interrupt being handled if there is one.
Explain different steps involved in Serving IRQ and FIQ interrupts in ARM
Microcontroller.
IRQ and FIQ interrupts only occur when a specific interrupt mask is cleared in the cpsr. The
ARM processor will continue executing the current instruction in the execution stage of the
pipeline before handling the interrupt.
An IRQ or FIQ interrupt causes the processor hardware to go through a standard procedure
(provided the interrupts are not masked):
1. The processor changes to a specific interrupt request mode, which reflects the interrupt being
raised.
2. The previous mode’s cpsr is saved into the spsr of the new interrupt request mode.
3. The pc is saved in the lr of the new interrupt request mode.
4. Interrupt/s are disabled—either the IRQ or both IRQ and FIQ interrupts are disabled in the
cpsr. This immediately stops another interrupt request of the same type being raised.
5. The processor branches to a specific entry in the vector table.
Illustrate Working of IRQ (Interrupt Request )and FIQ (Fast Interrupt Request) interrupts with an
example.
Figure 9.4 shows what happens when an IRQ interrupt is raised when the processor is in user mode.
The processor starts in state 1. In this example both the IRQ and FIQ exception bits in the cpsr are enabled.
When an IRQ occurs the processor moves into state 2. This transition automatically sets the IRQ bit to one,
disabling any further IRQ exceptions. The FIQ exception, however, remains enabled because FIQ has a
higher priority and therefore does not get disabled when a low-priority IRQ exception is raised. The cpsr
processor mode changes to IRQ mode.
 The user mode cpsr is automatically copied into spsr_irq.
 Register r14_irq is assigned the value of the pc when the interrupt was raised.
 The pc is then set to the IRQ entry +0x18 in the vector table.
 In state 3 the software handler takes over and calls the appropriate interrupt service routine to service the
source of the interrupt.
 Upon completion, the processor mode reverts back to the original user mode code in state 1
Figure 9.5 shows an example of an FIQ exception. The processor goes through a
similar procedure as with the IRQ exception, but instead of just masking further IRQ
exceptions from occurring, the processor also masks out further FIQ exceptions. This
means that both interrupts are disabled when entering the software handler in state 3
Changing to FIQ mode means there is no requirement to save registers r8 to r12 since
these registers are banked in FIQ mode. These registers can be used to hold
temporary data, such as buffer pointers or counters. This makes FIQ ideal for
servicing a single source, high-priority, low-latency interrupt.
Write an ALP to enable and disable IRQ and FIQ interrupts.
Design and Implement Stack in ARM Microcontroller.
Exception handling uses stacks extensively because each exception has a specific mode
of operation, so switching between modes occurs and saving the previous mode data is
required before switching so that the core can switch back to its old state successfully.
Each mode has a dedicated register containing a stack pointer.
The design of these stacks depends on some factors like operating system equirements
for stack design and target hardware physical limits on size and position in memory.
Most of ARM based systems has the stack designed such that the top of it is located at
high memory address.
A good stack design tries to avoid stack overflow because this causes instability in
embedded systems.

In the following figure we have two memory layouts which show how the stack is
placed in memory:
The first is the traditional stack layout. The second layout has the advantage that when
overflow occurs, the vector table remains untouched so the system has the chance to
correct itself.
Firmware
What is firmware?
The firmware is a low-level software that provides an interface between the
hardware and the application/operating system level software. It resides in the
ROM and executes when power is applied to the embedded hardware system.
Firmware can remain active after system initialization and supports basic system
operations.
What is bootloader?
The bootloader is a small application that installs the operating system or
application onto a hardware target. The bootloader only exists up to the point that
the operating system or application is executing, and it is commonly incorporated
into the firmware.
Explain different stages involved in Firmware execution .
1. Set up the target platform: Prepare the environment to boot an operating system since an
operating system expects a particular type of environment before it can operate.
This step involves making sure that the platform is correctly initialized (for example, making
sure that the control registers of a particular microcontroller are placed at a known address or
changing the memory map to an expected layout).
Platform identification: The firmware has to identify and discover the exact core and
platform it is operating on. The core is normally recognized by reading register 0 in coprocessor
15, which holds both the processor type and the manufacturer name.
Diagnostics: Diagnostics software provides a useful way for quickly identifying basic
hardware malfunctions. Because of the nature of this type of software, it tends to be specific to
a particular piece of hardware.
Debug Interface: Debug capability is provided in the form of a module or monitor that
provides software assistance for debugging code running on a hardware target. This
assistance includes the following:
■ Setting up breakpoints in RAM. A breakpoint allows a program to be interrupted and
the state of the processor core to be examined.
■ Listing and modifying memory (using peek and poke operations).
■ Showing current processor register contents.
■ Disassembling memory into ARM and Thumb instruction mnemonics.
Command line interpreter(CLI):
It allows you to change the operating system to be booted by altering the default
configurations through typing commands at a command prompt. For embedded systems,
the CLI is commonly controlled through a host terminal application. Communication
between the host and the target is normally over a serial or network connection.
2. Abstract the hardware: The Hardware Abstraction Layer (HAL) is a software layer that
hides the underlying hardware by providing a set of defined programming interfaces.
The HAL software that communicates with specific hardware peripherals is called a
device driver. A device driver provides a standard application programming interface (API)
to read and write to a specific peripheral.
3. Load a bootable image: The ability of firmware to carry out this activity depends upon the
type of media used to store the image. Note that not all operating system images or
application images need to be copied into RAM. The operating system image or application
image can simply execute directly from ROM.
ARM processors are normally found in small devices that include flash ROM. A common
feature is a simple flash ROM filing system (FFS), which allows multiple executable images
to be stored.
4. Relinquish control: This is where the firmware hands over control of the
platform to an operating system or application. Note that not all firmware
hands over control; instead the firmware can remain the controlling software
on the platform. Firmware designed to pass control to an operating system
may become inactive once the operating system has control. Alternatively, the
Machine Independent Layer (MIL) or Hardware Abstraction Layer (HAL) part
of the firmware can remain active. This layer exposes, through the SWI
mechanism, a standard application interface for specific hardware devices.
Write short note on ARM Firmware Suite (AFS).
ARM has developed a firmware package called the ARM Firmware Suite (AFS). AFS is
designed purely for ARM-based embedded systems. It provides support for a number of
boards and processors including the Intel XScale and StrongARM processors. The package
includes two major pieces of technology, a Hardware Abstraction Layer called μHAL
(pronounced micro-HAL) and a debug monitor called Angel.
μHAL provides a low-level device driver framework that allows it to operate over dif-
ferent communication devices (for example, USB, Ethernet, or serial). It also provides a
standard API.
μHAL supports these main features:
■ System initialization—setting up the target platform and processor core. Depending
upon the complexity of the target platform, this can either be a simple or complicated
task.
■ Polled serial driver—used to provide a basic method of communication with a host.
■ LED support—allows control over the LEDs for simple user feedback. This provides an
application the ability to display operational status.
■ Timer support—allows a periodic interrupt to be set up. This is essential for preemptive
context switching operating systems that require this mechanism.
■ Interrupt controllers—support for different interrupt controllers.
The boot monitor in μHAL contains a CLI.
The second technology, Angel, allows communication between a host debugger and a
target platform. It allows you to inspect and modify memory, download and execute
images, set breakpoints, and display processor register contents. All this control is through
the host debugger. The Angel debug monitor must have access to the SWI and IRQ or FIQ
vectors. Angel uses SWI instructions to provides a set of APIs that allow a program to
open, read, and write to a host filing system. IRQ/FIQ interrupts are used for
communication purposes with the host debugger.
Write short note on RedBoot firmware .
RedBoot is a firmware tool developed by Red Hat. It is provided under an open source
license with no royalties or up front fees. RedBoot is designed to execute on different CPUs
(for instance, ARM, MIPS, SH, and so on). It provides both debug capability through GNU
Debugger (GDB), as well as a bootloader. The RedBoot software core is based on a HAL.
RedBoot supports these main features:
 Communication—configuration is over serial or Ethernet. For serial, X-Modem protocol
is used to communicate with the GNU Debugger (GDB). For Ethernet, TCP is used to
communicate with GDB. RedBoot supports a range of network standards, such as bootp,
telnet, and tftp.
 Flash ROM memory management—provides a set of filing system routines that can
download, update, and erase images in flash ROM. In addition, the images can either
be compressed or uncompressed.
 Full operating system support—supports the loading and booting of Embedded Linux,
Red Hat eCos, and many other popular operating systems. For Embedded Linux,
RedBoot supports the ability to define parameters that are passed directly to the kernel
upon booting.
Explain Sandstone firmware package.
Sandstone firmware package carries out only the following tasks:
 set up target platform environment
 load a bootable image into memory and
 relinquish control to an operating system.
It is, however, still a real working example.
 The implementation is specific to the ARM Evaluator-7T platform, which includes an
ARM7TDMI processor.
Table 10.2 lists the basic characteristics of Sandstone.
Sandstone Directory Layout
The sandstone source file sand.s is located under the sand/build/src directory.
The object file produced by the assembler is placed under the build/obj
directory.
The object file is then linked, and the final Sandstone image is placed under the
sand/build/image directory.
This image includes both the Sandstone code and the pay-load.
The payload image, the image that is loaded and booted by Sandstone, is found
under the sand/payload directory.
For information about the Sandstone build procedure, take a look at the
readme.txt file under the sand directory.
This file contains a description of how to build the example binary image for the
ARM Evaluator-7T.
Sandstone Code Structure
Sandstone consists of a single assembly file. The file structure is broken down into a
number of steps, where each step corresponds to a stage in the execution flow of Sandstone.
Step 1: Take the Reset Exception
Execution begins with a Reset exception. Only the reset vector entry is required in the
default vector table. It is the very first instruction executed.
Step 2: Start Initializing the Hardware
The primary phase in initializing hardware is setting up system registers. These registers
have to be set up before accessing the hardware.
Step 3: Remap Memory
One of the major activities of hardware initialization is to set up the memory environment.
Sandstone is designed to initialize SRAM and remap memory. This process occurs fairly
early on in the initialization of the system.
Step 4: Initialize Communication Hardware
Communication initialization involves configuring a serial port and outputting a standard
banner. The banner is used to show that the firmware is fully functional and memory has
been successfully remapped. The serial port is set to 9600 baud, no parity, one stop bit, and no
flow control host terminal has to be configured with these
settings.
Step 5: Bootloader—Copy Payload and Relinquish Control
The final stage involves copying a payload and relinquishing control of the pc
over to the copied payload.