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2022 2 CED Week09 FIFO v2

The document outlines a lab project on First-In-First-Out (FIFO) systems at Kwangwoon University, detailing the functional description, project properties, and state operations of a synchronous FIFO implemented with 8 32-bit registers. It includes information on status flags, handshake signals, and the necessary Verilog files for the project. Additionally, it presents a block diagram and state operations for managing data flow within the FIFO structure.

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minhyung lee
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8 views12 pages

2022 2 CED Week09 FIFO v2

The document outlines a lab project on First-In-First-Out (FIFO) systems at Kwangwoon University, detailing the functional description, project properties, and state operations of a synchronous FIFO implemented with 8 32-bit registers. It includes information on status flags, handshake signals, and the necessary Verilog files for the project. Additionally, it presents a block diagram and state operations for managing data flow within the FIFO structure.

Uploaded by

minhyung lee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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컴퓨터공학 기초 실험2

Lab #8
FIFO

Kwangwoon University
Basic Computer Engineering Lab2
First-In-First-Out (FIFO)
➢ FIFO has control logic that manages read & write pointer which
generates status flags and provides handshake signals for interface with
user logic

➢ Queue
✓ First-in, First-out
✓ Nodes are removed only from the head (dequeue)
✓ Nodes are inserted only at the tail (enqueue)

Basic Computer Engineering Lab2, p. 2


Synchronous FIFO

PRACTICE Ⅰ

Basic Computer Engineering Lab2, p. 3


Functional Description

➢ 8개의 32bit register로 이루어짐

➢ 각 FIFO는 status flag와 handshake signal을 출력


✓ Status flag: full, empty
✓ Handshake signal: wr_ack, wr_err, rd_ack, rd_err

➢ Counter vector는 FIFO안에 있는 현재 data 수 제공

➢ 다음 슬라이드는 조교가 구현한 예시이므로 동일할 필요 없음

Basic Computer Engineering Lab2, p. 4


Project Properties

➢ New Project Wizard


✓ Project name : fifo
✓ Family & Device : Cyclone V 5CSXFC6D6F31C6 (밑에서 6번째)

➢ Verilog file
✓ Add files: register32_r_en.v, write_operation.v, read_operation.v,
Register_file.v
✓ New files: fifo.v, fifo_ns.v, fifo_cal.v, fifo_out.v (예시)

Basic Computer Engineering Lab2, p. 5


Block Diagram

32

➢ Next state logic: 외부로 wr_en과 rd_en을 받고 내부에서 현재 state와 data_count를 받아 다


음 state를 출력
➢ Calculate address logic: state, data_count, head, tail을 받아 다음 state에 대한 head, tail값
(register file의 주소값)과 현재 data의 개수를 계산
➢ Output logic: 현재 state와 data_count를 받아 full, empty 및 handshake signal을 출력
➢ Register file: 사용자로부터 받은 입력을 저장하거나 알맞은 register의 값을 출력
Basic Computer Engineering Lab2, p. 6
FIFO FSM

INIT WR_EN & ~FULL


head = 0; RD_EN & ~EMPTY
reset_n nop
tail = 0;
WR_EN & FULL / WR_ERR
empty = 1; RD_EN & EMPTY / RD_ERR

READ WRITE
DATA_COUNT--; DATA_COUNT++;
DOUT = Mem[head]; Mem[tail] = DIN;
head++; tail++;
if DATA_COUNT == 0, if DATA_COUNT == 8,
EMPTY = 1 FULL = 1

RD_ERROR WR_ERROR
No change; No change;
EMPTY = 1 FULL = 1

NO_OP
if DATA_COUNT == 0, EMPTY = 1
if DATA_COUNT == 8, FULL = 1

Basic Computer Engineering Lab2, p. 7


State Operations

➢ 프로젝트 내에서 필요로 하는 State는 다음과 같음

State Operations

INIT head = tail = DATA_COUNT = 0;


NO_OP No change
mem[tail] = DIN; tail++; DATA_COUNT++;
WRITE
If DATA_COUNT == 8, FULL = 1;
WR_ERROR No change; FULL = 1;
DOUT = mem[head]; head++; DATA_COUNT--;
READ
If DATA_COUNT == 0, EMPTY = 1;
RD_ERROR No change; EMPTY = 1

Basic Computer Engineering Lab2, p. 8


Output Design – Full & Empty

➢ Data count를 기준으로 full, empty를 판단

Data_count Full Empty


0 0 1
8 1 0
1~7 0 0

Basic Computer Engineering Lab2, p. 9


Testbench(1/2)

Basic Computer Engineering Lab2, p. 11


Testbench(2/2)

Basic Computer Engineering Lab2, p. 12


Q&A

THANK YOU

Basic Computer Engineering Lab2, p. 13

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