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Assignment 02

The document outlines an assignment for VLSI Design and Testing, detailing various topics including wafer processing, CMOS inverter fabrication, and SOI technology. It also covers CMOS gate switching characteristics, design rules, and comparisons of different CMOS logic structures. Additionally, it requires schematic designs and illustrations for specific logic circuits and components.

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13 views1 page

Assignment 02

The document outlines an assignment for VLSI Design and Testing, detailing various topics including wafer processing, CMOS inverter fabrication, and SOI technology. It also covers CMOS gate switching characteristics, design rules, and comparisons of different CMOS logic structures. Additionally, it requires schematic designs and illustrations for specific logic circuits and components.

Uploaded by

kusumanskusumans
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Design and Testing-BEC602

ASSIGNMENT-02 Questions

1. Explain with neat diagram Wafer Processing and Selective Diffusion


2. Explain with neat diagrams CMOS inverter fabrication using n-well process with
different masks used for it.
3. Explain with neat diagrams Silicon on Insulator (SOI) CMOS Technology.
4. With neat diagrams, explain the lambda design rules for wires, contact cuts and
Transistors.
5. Explain switching characteristics of CMOS gate with determination following
switching time

i) Rise time ii) Fall time iii) Delay time


6. Describe the following with relevant equations

i) Charge sharing ii) Yield


7. Illustrate the merits & demerits of following CMOS logic structures with a two input
NOR gate realization as an example.
i) Dynamic CMOS logic ii) Domino CMOS logic
8. Illustrate the working, merits and demerits of the following logic structures with two
i/p NAND gate realization as an example: i) Clocked CMOS logic.
9. Design the schematic and layout diagram for Y= (AB+CD+E) using CMOS logic.
10. Illustrate the static behaviour of basic bistable element with necessary circuit
schematic and voltage transfer curve.
11. Illustrate the working of AOI based implementation of the clocked NOR based SR
latch circuit with necessary circuit, truth table and waveforms.
12. Illustrate the working of CMOS SR latch based on NOR gates with necessary circuit
and truth table.
13. Illustrate the working of Linear feedback shift register and 3 bit Built in Logic Block
Observation with necessary circuit diagram

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