CSE2009 – COA – End Term Question Bank – May2025

Part -A

1. Differentiate Memory Address Register and Memory Data Register.

2. Define clock rate.

3. Differentiate between Index Addressing Mode and Relative Addressing Mode.

4. Which is the storage that can be accessed faster by processor?

5. Perform -12 + 8 using 2’s complement system.

6. What is Memory mapped I/O?

7. If 32-bits are used to address a memory location, what is the maximum size of that
memory?

8. Generate the control sequence for the instruction Move R1,R2 in processor with single
bus organization and multiple bus organization.

9. List the four stages of pipelining used in instruction execution in a computer

architecture?

10. What is WMFC? Why is this signal important?

11. Mention the group of lines in the system bus.

12. Define Computer and it’s peripherals with a neat diagram.

13. Process of inserting an element in stack is called ____________

14. What are the major components of a CPU?

15. Mention true or false for the statement given below:

a) Array multiplier circuit is used for the multiplication of unsigned number and not
signed number.
b) Booth’s algorithm is used for the multiplication of signed as well as unsigned number.

16. What is the disadvantage of an n-bit ripple-carry adder for which carry-look ahead
circuit is required?

17. There are two Modes of DMA. What are those? Briefly explain each.
18. Differentiate between multiple bus organization and single bus organization?

19. Why pipelining is required in computer system.

20. What is hazard in pipelining? Mention two hazards.

21. List the functional units of computer system

22. Distinguish between CISC and RISC Processor

23. Summarize the type of ROM used in computer system

24. Outline the processor execution time equation of a computer system

25. Distinguish between PUSH and POP instruction with examples

26. Distinguish between MAR and MDR in Computer Architecture

27. Utilize the Booth’s Algorithm Recoding Table, to recode the sequence of (10110111)2

28. Illustrate the flowchart of Programmed I/O Communication Technique

29. Outline the control sequence for the instruction ADD R1, R2, R3 in Single Bus
architecture.

30. List the tasks involved in pipelining concepts of computer system

Part - B

1. Illustrate the different techniques that can be used to increase the

performance of a system. Justify your answer with suitable diagrams.

2. Let a processor operate by a frequency 20MHtz and it executes a

typical program in which 50% are register referenced instruction, 30% are
memory reference instructions and 20% are branch instructions. Register
referenced instruction, memory reference instructions and branch
instructions take 4, 8 and 6 clock cycles respectively. Find out the total time
taken by the processor to execute the program.
 3. In a 16-bit machine, a Stack is stored from memory address 2500 to 1500. Initially, the
stack is empty, and the stack pointer (SP) points to the address 2498. Determine the
address of stack pointer, after the following operations –
• Push the value ‘A’ onto the stack
• Push the value ‘B’ onto the stack
• Pop a value from the stack
• Push the value ‘C’ onto the stack
• Push the value ‘D’ onto the stack
• Pop a value from the stack

4. Frame the instructions to evaluate the expression E=(A+B)/(C+D) in Three address, Two
address and one address instruction.

5. Explain the following addressing modes – i) Absolute Mode ii) Index Mode iii) Base with
Index Mode iv)Auto-increment Mode v) Relative Mode.

6. Perform the division of 14÷3 using the Integer Restoring division method

7. What is the main limitation of a Ripple Carry Adder. Illustrate using

expressions of G and P how the Carry Lookahead Adder overcomes the
limitation.

8. Describe Booth's algorithm for signed-operand multiplication and solve −12×

-10.

9. Design a DMA interface and explain its working with a suitable diagram

10. Register R1 and R2 of computer holds the value 3200 and 4600 respectively.
Find the effective address of the source operand in each of the following
instructions? (Assume 64-bit word length and each are individual
instructions)
i. Load 20(R1), R2
ii. Subtract (R1) +, R5
iii. Add – (R2), R5
iv. Store 30(R1,R2), (R5)
Move R1, R5

11. Explain interrupt-driven I/O communication and the role of ISR to solve the
interrupts.
12. Suppose the main memory consists of 512 blocks of 8 words each and cache
consists of 64 blocks. How many bits are required for the main memory
address? How many bits are there in each of Tag, block/set and word fields for
Direct, Associative, and Set- Associative mapping techniques? (Note: There are
4 cache blocks in each set).

13. Illustrate single-bus organization with a neat diagram. Generate and explain
the control sequence for execution of complete instruction [Add R4,R5] in
single- bus organization.

14. Illustrate the concept of pipelining and explain the different types of hazards
in pipelining.

15. Illustrate multiple-bus organization with a neat diagram. Generate and

explain the control sequence for execution of complete instruction [Add
R4,R5] in multiple- bus organization.

16. How is the performance increased by using pipelining concept? What are the
possible hazards in pipelining. Explain.

17. Define ROM. Explain various types of ROMs. Discuss

the difference between Read-only Memory and
Random Access Memory.

18. Describe a BUS and its types. Explain BUS structure

in detail with a neat sketch.

19 Draw the basic functional units of a computer and

explain each block briefly.

19. Describe the different ways to represent negative

numbers? Subtract 7-2 using 2’s compliment
method.

20. What are addressing modes? Explain any 5 various

addressing modes with examples

21. What are the different types of computers and

 where are they used.

22. Design 4-bit carry-look ahead adder circuit. The

truth table for full adder, Boolean expression for
sum, carry, generate and propagate functions are to
be shown.

23. Write the difference between I/O mapped and

memory mapped I/O.

24. What is the use of branch instruction? Why it is

used? Perform the multiplication of -6 and 5 using
Booth’s algorithm.

25. Perform division of 11 (1011) by 3 (0011) using

restore division method. Also, draw the hardware
circuit. Use sign extension method to show the
multiplication of two numbers in which
multiplicand is -13 and multiplier is +11.

26. Define the following signals:

a) DMA request b) DMA acknowledge c) HOLD d)
HLDA
e) INTR

27. Explain the memory hierarchy in computer

architecture with neat sketch.

28. Explain the loading data from memory to register

for the instruction MOV R2, (R1) by showing all the
control sequence and single processor bus system.

29. Explain the concept of 4-stage pipelining.

Draw the multiple bus organization and explain it.

30. Explain the arithmetic operation for the instruction

ADD R1, R2, R3 by showing all the control sequence
and single processor bus system.

31. Explain all the hazards of pipelining.

32. Explain the storing data from register to memory for

the instruction MOV (R2), R1 by showing all the
control sequence and single processor bus system.
33. Draw the block diagram of Interrupt driven I/O and
explain it. Also, draw the block diagram of DMA
method of I/O transfer mode and explain it.

34. Explain the register transfer operation for the

instruction MOV R4, R1 by showing all the control
sequence and single processor bus system.

35. Explain the storing word into memory operation for

the instruction MOV (R1), R2 by showing all the
control sequence and single processor bus system.

36. Using sequential circuit perform the multiplication

for which multiplier (M) is 1101 and multiplicand
(Q) is 1011. Also draw the hardware circuit.

37. Draw the block diagram of programmed I/O and

explain it.

38. What is the difference between single bus system

and multiple bus system. Which one is more
efficient.

39. Distinguish between the big endian assignment and

little endian assignment with suitable example

40. Explain the types of instructions based on addresses

with suitable examples

41. Identify the overflow values for the 5-bit signed

number addition of the following
i. (-12) + (-10)
ii. (-9) – (-13)
iii. (-11) + (-8)
iv. (-9) – (-8)
v. (+14)+(-7)

42. Explain the communication between the Processor

and Memory with block diagram

43. Demonstrate the purpose of bus structure in

Computer System with necessary blocks
 44. Summarize the architecture of Single Bus
architecture and Multiple Bus architecture with
block diagram

45. Outline the flowchart of Memory Hierarchy in

computers

46. Identify the Effective address of the following

instruction
i. ADD (R3)+, R4
ii. STORE 100(R3,R2),(R4)
iii. MOV #4004, R2
iv. LOAD 14(R2),R7
v. SUB –(R1),R2
vi. STORE 50(R4),R1

47. Consider a cache consisting of 256 blocks of 16

words each, for a total of 4096 words and assume
main memory is addressable by 16 bit address and
it consists of 4K blocks. Develop the mapping
formats for the different mapping techniques.

48. Explain about Cache memory and its usage in

Computer organization

49. Demonstrate the memory read/write operation of

the 16 X 8 Internal Memory chip

50. Illustrate the various addressing modes of computer

instructions with examples

51. Rephrase the following values to Single Precision

Floating Point
i) -0.011561
ii) +0.000789

52. Make use of Sign Extension algorithm to perform the

multiplication of (+31) and (-28)

53. Develop the 4 bit adder circuit to reduce the latency

in the propagation of the Carry signal with necessary
diagrams.

54. Rephrase the following values to Single Precision

 Floating Point
i) -0.001786
ii) +0.23546

55. Make use of Booth’s algorithm to perform the

multiplication of (+22) and (-19)

56. Utilize the Restoration Method to perform the

division of 15 by 9

57. Distinguish between Memory mapped IO and I/O

mapped I/O

58. Demonstrate the importance of Direct Memory

Access controller with architecture

59. identify the control sequence for the instruction of

ADD (R2), R1 for the Single Bus Architecture with
diagram

60. Explain about the Interrupt based I/O

Communication

61. Identify the control sequence for the instruction of

ADD R3,R4,R5 for the Multiple Bus Architecture with
diagram

62. Outline the types of hazards in pipelining with

necessary diagram