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VLSI Design 1marks Question

The document contains a series of multiple-choice questions related to VLSI design concepts, including chip utilization, leakage power, and placement strategies. It covers topics such as physical design, floorplanning, routing, and VLSI simulation and synthesis. The questions aim to assess knowledge on various aspects of VLSI design methodologies and techniques.

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Arpan Bhattacharya
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23 views12 pages

VLSI Design 1marks Question

The document contains a series of multiple-choice questions related to VLSI design concepts, including chip utilization, leakage power, and placement strategies. It covers topics such as physical design, floorplanning, routing, and VLSI simulation and synthesis. The questions aim to assess knowledge on various aspects of VLSI design methodologies and techniques.

Uploaded by

Arpan Bhattacharya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Introduction

 1) Chip utilization depends on ___.


a. Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

 2) In Soft blockages ____ cells are placed.


a. Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells

a.
b. 11) Leakage power is inversely proportional to ___.
a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

13) Search and Repair is used for ___.


 a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None


15) More IR drop is due to ___.
 a. Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers
16) The minimum height and width a cell can occupy in the
design is called as ___.
a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

 19) "Total metal area and(or) perimeter of conducting layer /


gate to gate area" is called ___.
a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

 20) The Solution for Antenna effect is ___.


a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing

 22) If the data is faster than the clock in Reg to Reg path ___
violation may come.
a. Setup
b. Hold
c. Both
d. None

 31) Pitch of the wire is ___.


a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing

 33) In technology file if 7 metals are there then which metals


you will use for power?
a. Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

 34) If metal6 and metal7 are used for the power in 7 metal
layer process design then which metals you will use for clock ?
a. Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

1. If it is required to design a circuit with the maximum


possible performance, which of the following design
styles would you prefer? (2)
(a) FPGA.
(b) Gate array.
(c) Full custom.
(d) Standard cell.

2. Which of the following statements is/are not true for standard


cell-based design? (1)
(a) Cells of arbitrary sizes can be included in a design
(b) The area of each of the cells must be the same
(c) The height of each of the cells must be same
(d) Feed-through cells may be required to complete the
interconnections
Placement

 29) Which of the following is preferred while placing macros


___?
a. Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O


38) What is the effect of high drive strength buffer when added in
long net ?
a. Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

 41) Utilization of the chip after placement optimization will


be ___.
a. Constant
b. Decrease
c. Increase
d. None of the above

3.
Which of the following statements is/are true in
physical design? (1)
(a) Floorplanning precedes partitioning.
(b) Partitioning precedes placement.
(c) Floorplanning and routing can proceed in
parallel.
(d) Placement precedes routing.

4. In which step of physical design are the shapes and the


pin locations of flexible blocks get defined? (3)
(a) Floorplanning.
(b) Placement.
(c) Routing.
(d) None of these.

5. Which of the following is true for the Timberwolf


placement algorithm? (3)
(a) We start with an initial partition of the blocks
and improve it so that the cost reduces in every
iteration.
(b) The cost can sometimes increase across
iterations.
(c) The probability of accepting worse moves
decrease as the number of iterations increases.
(d) It generates optimum placement solutions for
rectangular blocks.

6. If N denotes the number of circuit nodes, the worst-case


time complexity of the Kernighan-Lin algorithm is
given by, (3)
(a) O(N)
(b) O(N log2N)
(c) O(N2)
(d) O(N3)

Floorplanning & Routing


 4) Delay between shortest path and longest path in the clock
is called ____.
a. Useful skew
b. Local skew
c. Global skew
d. Slack
 5) Cross talk can be avoided by ___.
a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets

 6) Prerouting means routing of _____.


a. Clock nets
b. Signal nets
c. IO nets
d. PG nets

 7) Which of the following metal layer has Maximum


resistance?
a. Metal1
b. Metal2
c. Metal3
d. Metal4

 8) What is the goal of Clock Tree Synthesis?


a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

 9) Usually Hold is fixed ___.


a. Before Placement
b. After Placement
c. Before CTS
d. After CTS
 12) Filler cells are added ___.
a. Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing

 17) CRPR stands for ___.


a. Cell Convergence Pessimism Removal
b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal

 25) Timing sanity check means (with respect to PD)___.


a. Checking timing of routed design without net delays
b. Checking Timing of placed design with net delays
c. Checking Timing of unplaced design without net
delays
d. Checking Timing of routed design with net delays

 30) Routing congestion can be avoided by ___.


 a. placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None

 39) Delay of a cell depends on which factors ?


a. Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

 40) After the final routing the violations in the design ___.
a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.

 43) What are pre routes in your design?


a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.

VLSI Simulation

7. Which of the following represents the behavioral description of a


function? (1)
(a) A netlist of gate and their interconnections
(b) The truth table description of a combinational function
(c)The sum-of-product representation of the function
(d) All of these
8. Which of the following function cannot be realized by a single 4-
input LUT in a typical FPGA? (6)
(a) F=A.B + B.C’
(b) F=A.B’+B.C’+C.D’
(c) F=A.B+C.D+A.E
(d) F=1

68) Stuck open (off) fault occur/s due to _________


a. An incomplete contact (open) of source to drain node
b. Large separation of drain or source diffusion from the gate
c. Both a and b
d. None of the above
ANSWER: Both a and b (module 4)

5) Among the VHDL features, which language


statements are executed at the same time in parallel
flow?

a. Concurrent
b. Sequential
c. Net-list
d. Test-bench
ANSWER: Concurrent (module 4)

(module 4)
For which of the following modules, we can swap the input pins without changing the functionality?
a. A module realizing the function F = A.B + B.C + C.A
b. A 2-to-1 multiplexer
c. A 5-input NOR gate.
d. A 2-input exclusive-OR gate.
No, the answer is incorrect.
Score: 0
Accepted Answers:
a. A module realizing the function F = A.B + B.C + C.A
c. A 5-input NOR gate.
d. A 2-input exclusive-OR gate.
6. What is the probability of a two-input AND function be 1? (mod 4)

VLSI Synthesis

1. Which among the following is a process of


transforming design entry information of the circuit into
a set of logic equations? (mod 5)
a. Simulation
b. Optimization
c. Synthesis
d. Verification
ANSWER: Synthesis

13) Which among the following is an output generated


by synthesis process? (mod 5)

a. Attributes & Library


b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list
ANSWER: Gate-level net list

48) Which among the following is/are regarded as the


function/s of translation step in synthesis process? (mod
5)

a. Conversion of RTL description to boolean unoptimized


description
b. Conversion of an unoptimized to optimized boolean
description
c. Conversion of unoptimized boolean description to PLA format
d. All of the above
ANSWER: Conversion of RTL description to Boolean
unoptimized description
49) In synthesis flow, which stage/s is/are responsible
for converting an unoptimized Boolean description to
PLA format? (mod 5)

a. Translation
b. Optimization
c. Flattening
d. All of the above
ANSWER: Flattening

50) In synthesis flow, the flattening process generates


a flat signal representation of _____levels. (mod 5)

A. AND
B. OR
C. NOT
D. EX-OR

a. A & B
b. C & D
c. A & C
d. B & D
ANSWER: A & B

7. What is high level synthesis? (from C/C++ to RTL) (mod 5)

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