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Clever Crew

This document presents an efficient VLSI design for the Advanced Encryption Standard (AES) optimized for resource-constrained embedded systems like IoT devices. The architecture features an 8-bit pipelined structure with key optimizations such as clock gating and shared modules, achieving a balance of speed, power, and area efficiency. Implemented on a Xilinx FPGA, the design is suitable for secure, real-time encryption applications.

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6 views1 page

Clever Crew

This document presents an efficient VLSI design for the Advanced Encryption Standard (AES) optimized for resource-constrained embedded systems like IoT devices. The architecture features an 8-bit pipelined structure with key optimizations such as clock gating and shared modules, achieving a balance of speed, power, and area efficiency. Implemented on a Xilinx FPGA, the design is suitable for secure, real-time encryption applications.

Uploaded by

mohamedalima2004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AN EFFICIENT VLSI DESIGN FOR PIPELINED ADVANCED ENCRYPTION

STANDARD IN CRYPTOGRAPHY
Jayanita Devi R, Padmapriya A

Supervisor: Ms. JAYAMANI K, Assistant Professor


Department of Electronics and Communication Engineering

ABSTRACT:
In today’s data-driven world, ensuring the confidentiality and
integrity of information is crucial, especially in resource-constrained Design Input: The Nano-AES architecture is implemented in Verilog HDL with an
embedded systems like IoT devices. This project presents a efficient 8-bit data path, optimized for IoT devices.
VLSI implementation of the Advanced Encryption Standard (AES),
focusing on a compact, low-power, and high-speed design suitable ● Encryption Flow: The design processes plaintext through key AES stages—
for secure hardware environments. This architecture supports 128- Sub-Bytes, Shift-Rows (embedded in the State-Register), Mix Columns, and Add
bit AES encryption, integrating optimized Sub-Bytes, Mix-Columns, Round Key—using a pipelined approach
and embedded Shift-Rows for area efficiency. A single Sub-Bytes
module is shared between key expansion and encryption, reducing ● Power Optimization: Clock gating is applied to key components like the State-
logic overhead. Clock gating is applied across key blocks to Register and Key-Register to reduce power consumption during idle states.
minimize dynamic power usage, while constant-time operations
enhance resistance to side-channel attacks. Implemented on the ● Simulation and Synthesis: The design is verified using ModelSim and
Xilinx XC3S200TQ-144 FPGA using Verilog HDL, the design is synthesized on an FPGA using Xilinx ISE tools.
verified through ModelSim simulations and synthesized using Xilinx
ISE. The result is a compact AES core that achieves a balanced
● Performance: The optimized architecture significantly reduces area and delay
trade-off between speed, area, and power—ideal for real-time
encryption in resource-limited environments. This work compared to conventional AES designs, making it ideal for secure, low-power
demonstrates a scalable and secure AES solution ideal for real-time applications.
encryption in resource-limited environments.
In an increasing digital world, data security has become a critical
concern. Cryptography plays a central role in ensuring
confidentiality, integrity, and authentication of information in RESULT:
communication systems. The Advanced Encryption Standard (AES)
is one of the most widely used symmetric key encryption
algorithms, standardized by NIST due to its strong security and
performance. Implementing AES in hardware offers significant
advantages in terms of speed, parallelism, and resistance to
software-based attacks. However, achieving high performance while
minimizing power consumption and area is a major design
challenge, especially for embedded and IoT systems where
resources are limited. This project focuses on designing an efficient
VLSI architecture for the AES algorithm using an 8-bit pipelined
structure. The design aims to reduce silicon area, optimize power
usage, and maintain high throughput. Key architectural
optimizations, including clock gating, embedded Shift-Rows, and
shared Sub-Bytes modules, are introduced to enhance overall
efficiency and security. The result is a compact, power-aware AES
METHODOLOGY:

CONCLUSION:
This project presents a compact and efficient VLSI implementation
of the
AES algorithm using an 8-bit pipelined architecture. Key
optimizations such
as embedded Shift-Rows, shared Sub-Bytes, and clock gating help
reduce
power and area while maintaining high performance. The design,
implemented
on a Xilinx FPGA, is well-suited for secure, real-time encryption in
embedded
and IoT systems. Overall, the architecture offers a practical balance
of speed,
security, and resource efficiency for lightweight cryptographic
applications.

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