25 Advanced SystemVerilog

Interview Questions

With Detailed Explanations and Examples

By Kittu Patel – VeriCore

May 16, 2025

SystemVerilog Interview Collection VeriCore Academy

Preface
SystemVerilog stands as the cornerstone of modern functional verification. With its
vast set of features ranging from object-oriented programming to constrained random
verification and assertions, mastering SV is crucial for cracking top-level VLSI interviews.
This document contains 25 carefully curated high-level interview questions along with
deep and insightful answers. Every question is designed to test not just syntax, but real-
world understanding of how SystemVerilog is applied in testbenches, UVM, and ASIC
design environments.
Each section is structured to deepen your conceptual understanding and sharpen your
problem-solving skills.

Who this is for:

• Experienced verification engineers preparing for product company interviews.

• VLSI aspirants wanting to master advanced SystemVerilog topics.

• Professionals looking to upskill and deepen their verification knowledge.

Let’s master SystemVerilog – one question at a time.

— Kittu Patel

Page 1
SystemVerilog Interview Collection VeriCore Academy

1 Advanced Data Types and Structures (Q1–Q25)

Q1. What is the difference between ‘struct‘, ‘union‘, and ‘class‘
in SystemVerilog? Provide examples.
Answer: SystemVerilog supports three primary composite data types: ‘struct‘, ‘union‘,
and ‘class‘. Here’s a detailed comparison:

• struct groups variables under a single name; all variables exist simultaneously.

• union allows only one variable to occupy memory at any time (overlapping mem-
ory).

• class is a dynamic object with OOP features such as inheritance and polymorphism.

Example:

typedef struct {
bit [3:0] id;
bit [7:0] data;
} packet_t;

typedef union {
bit [31:0] raw;
struct {
bit [7:0] header;
bit [23:0] payload;
} fields;
} u_data;

class transaction;
rand bit [7:0] addr;
rand bit [31:0] data;
endclass

Key Points:

• ‘struct‘ and ‘union‘ are used for static memory-efficient design.

• ‘class‘ allows OOP principles and dynamic behavior, making it ideal for testbench
modeling.

Page 2
SystemVerilog Interview Collection VeriCore Academy

Q2. Explain ‘typedef struct packed‘ and its practical use in de-
sign/verification.
Answer: The ‘typedef struct packed‘ keyword defines a packed structure, where all
members are packed next to each other with no padding, allowing it to be treated like a
single vector.
Syntax:

typedef struct packed {

logic [3:0] opcode;
logic [11:0] addr;
logic [15:0] data;
} instruction_t;

Why Use It?

• Packed structs can be assigned to bit vectors directly.

• Useful for representing bus protocols and aligning with memory layouts.

Example Use:

instruction_t instr;
logic [31:0] raw_instr;

raw_instr = 32’hABCD1234;
instr = instruction_t’(raw_instr);

Page 3
SystemVerilog Interview Collection VeriCore Academy

Q3. Differentiate between ‘static‘, ‘automatic‘, and ‘dynamic‘

arrays. Which is best suited in testbenches?
Answer:

• Static arrays: Size known at compile-time.

• Automatic arrays: Stack-allocated arrays created fresh each time a task is called.

• Dynamic arrays: Size can be changed during runtime using ‘new[]‘.

Example:

bit [7:0] static_array[4]; // Static

automatic bit [7:0] auto_array[4]; // Automatic
bit [7:0] dyn_array[]; // Dynamic

initial begin
dyn_array = new[8]; // Allocates size at runtime
end

• Best for Testbenches: Dynamic arrays — provide flexibility and memory effi-
ciency.

Page 4
SystemVerilog Interview Collection VeriCore Academy

Q4. What is a ‘queue‘ in SystemVerilog and how is it different

from a dynamic array?
Answer: A ‘queue‘ is a variable-size, ordered collection similar to a dynamic array but
supports push/pop operations.
Key Differences:

• Queues grow and shrink with push front(), push back(), pop front(), pop back().

• Dynamic arrays only resize via ‘new[].

Syntax:

bit [7:0] q[$]; // Declaring a queue

initial begin
q.push_back(10); // Add to end
q.push_front(5); // Add to start
q.pop_back(); // Remove last element
end

Use Case: Queues are ideal for modeling FIFOs or temporary transaction buffers.

Page 5
SystemVerilog Interview Collection VeriCore Academy

Q5. What are associative arrays in SV? Where are they best
used?
Answer: Associative arrays allow indexing using any scalar data type, not just integers.
They’re best when the index is sparse or unknown at compile time.
Syntax:

bit [7:0] aa[string]; // Associative array with string key

initial begin
aa["read"] = 1;
aa["write"] = 0;
end

Features:

• Dynamic memory

• Iterator support: foreach, first(), last(), next(), prev()

Used in: Scoreboards, coverage models, response tracking.

Page 6
SystemVerilog Interview Collection VeriCore Academy

Q6. How are associative arrays iterated in SystemVerilog? Give

an example.
Answer: SystemVerilog supports four iterator methods for associative arrays:

• first(var)

• last(var)

• next(var)

• prev(var)

Example:

bit [7:0] aa[string];

string key;

initial begin
aa["a"] = 1;
aa["b"] = 2;
aa["c"] = 3;

key = aa.first();
while (key != "") begin
$display("Key: %s, Value: %0d", key, aa[key]);
key = aa.next(key);
end
end

Page 7
 SystemVerilog Interview Collection VeriCore Academy

Q7. Explain the use of ‘$size‘, ‘$left‘, ‘$right‘, ‘$high‘, ‘$low‘

system tasks with respect to arrays.
Answer: These system tasks provide bounds and size-related information of arrays.

• size(array) − N umberof elements.left(array) - Left-most index.

• right(array) − Right − mostindex.low(array) - Lower bound.

• high(array) − U pperbound.
Example:

bit [7:0] arr[5:1];

initial begin
$display("Size: %0d", $size(arr)); // Output: 5
$display("Left: %0d", $left(arr)); // Output: 5
$display("Right: %0d", $right(arr)); // Output: 1
$display("Low: %0d", $low(arr)); // Output: 1
$display("High: %0d", $high(arr)); // Output: 5
end

Page 8
SystemVerilog Interview Collection VeriCore Academy

Q8. How are queues initialized and resized during simulation?

Can they shrink dynamically?
Answer: Yes. Queues are self-sizing and can be dynamically modified using ‘pushf ront‘, ‘pushb ack‘, ‘pop
Example:

bit [7:0] q[$];

initial begin
q = {1, 2, 3};
q.push_back(4);
q.pop_front();
q.pop_back();
end

Note: Use queues in scoreboards and transaction-level modeling for dynamic buffer-
ing.

Page 9
SystemVerilog Interview Collection VeriCore Academy

Q9. Write a function to reverse a dynamic array in SystemVer-

ilog.
Answer:

function void reverse_array(ref int dyn[]);

int i, temp;
for (i = 0; i < dyn.size()/2; i++) begin
temp = dyn[i];
dyn[i] = dyn[dyn.size()-1 - i];
dyn[dyn.size()-1 - i] = temp;
end
endfunction

Usage:

int a[] = {1,2,3,4,5};

reverse_array(a);

Page 10
SystemVerilog Interview Collection VeriCore Academy

Q10. What are ‘bit-stream‘ casting and its advantages? Provide

an example.
Answer: Bit-stream casting is used to reformat bits into another type without changing
the underlying bit pattern.
Syntax:

type’(bit_vector)

Example:

typedef struct packed {

bit [7:0] addr;
bit [7:0] data;
} packet_t;

bit [15:0] raw = 16’hABCD;

packet_t pkt = packet_t’(raw);

Advantage:

• Easy and efficient reinterpretation of data.

• Used for modeling memory-mapped protocols.

Page 11
SystemVerilog Interview Collection VeriCore Academy

Q11. How does a class handle memory in SystemVerilog? Ex-

plain shallow vs deep copy.
Answer: In SystemVerilog, ‘class‘ objects are dynamic and accessed via handles. Two
types of copy behavior exist:

• Shallow Copy: Copies handle only. Both variables point to the same memory.

• Deep Copy: Clones object and creates a new instance with same data.

Example (Shallow Copy):

class A;
int x;
endclass

A obj1 = new();
obj1.x = 10;

A obj2 = obj1; // Shallow copy

obj2.x = 20; // obj1.x is also 20

Page 12
SystemVerilog Interview Collection VeriCore Academy

Q12. How is new[] used in dynamic arrays and classes? Show

with both.
Answer: new[] dynamically allocates memory for arrays or array of class objects.
Dynamic Array:

int dyn_array[];
dyn_array = new[10]; // Allocates 10 elements

Class Array:

class Item;
int value;
endclass

Item items[];
initial begin
items = new[5];
foreach(items[i])
items[i] = new(); // Allocate each object
end

Page 13
SystemVerilog Interview Collection VeriCore Academy

Q13. Explain the use of foreach loop in iterating over arrays.

Give all valid variants.
Answer: foreach is a SystemVerilog looping construct optimized for arrays (including
multidimensional).
1D Example:

int arr[5];

foreach (arr[i])
$display("Index: %0d, Value: %0d", i, arr[i]);

2D Example:

bit [7:0] arr[3][4];

foreach (arr[i,j])
$display("arr[%0d][%0d]=%0d", i, j, arr[i][j]);

Page 14
SystemVerilog Interview Collection VeriCore Academy

Q14. Can we pass associative arrays to functions? How are they

passed and accessed?
Answer: Yes, associative arrays can be passed to functions/tasks by reference.
Syntax:

function void printAA(ref int aa[string]);

string key;
key = aa.first();
while (key != "") begin
$display("%s = %0d", key, aa[key]);
key = aa.next(key);
end
endfunction

Call:

int aa[string];
aa["apple"] = 1;
aa["banana"] = 2;
printAA(aa);

Page 15
SystemVerilog Interview Collection VeriCore Academy

Q15. Differentiate between class and interface in SV with use

cases.
Answer:

• Class is used in testbenches for transaction modeling, sequences, and OOP.

• Interface encapsulates signal-level connectivity, grouping logic signals.

Class:

class Packet;
rand bit [7:0] addr;
endclass

Interface:

interface bus_if;
logic clk, rst;
logic [7:0] data;
endinterface

Usage: Class is behavioral, interface is structural.

Page 16
SystemVerilog Interview Collection VeriCore Academy

Q16. Explain the difference between rand and randc in Sys-

temVerilog. When is each used?
Answer:

• rand: Generates random values with repetition allowed.

• randc: Generates random values in a cyclic fashion (without repetition until all
values are used).

Example:

class A;
rand bit [1:0] x; // can repeat
randc bit [1:0] y; // cycles through all values 0 to 3
endclass

Use Case: Use ‘randc‘ when you want exhaustive permutation, such as generating
all priority levels, IDs, etc.

Page 17
SystemVerilog Interview Collection VeriCore Academy

Q17. What is constraint overriding and how is it achieved in

SystemVerilog?
Answer: Constraint overriding allows a child class to override constraints defined in a
parent class.
Example:

class Base;
rand bit [7:0] data;
constraint c1 { data < 100; }
endclass

class Child extends Base;

constraint c1 { data > 150; } // Overrides parent
endclass

Note: Constraint names must match exactly. Overridden constraints are evaluated
instead of the parent’s.

Page 18
 SystemVerilog Interview Collection VeriCore Academy

Q18. Can randomization fail in SystemVerilog? How do you

detect and debug it?
Answer: Yes. Randomization can fail if constraints conflict or there are no legal values
possible.
Detection:

if (!obj.randomize())
$error("Randomization Failed");

Debugging Tips:

• Reduce constraints step-by-step.

• Print constraints and variables.

• Use constraint solver diagnostic tools (e.g., display, coverage).

Page 19
SystemVerilog Interview Collection VeriCore Academy

Q19. What is a randcase and how is it different from case in

SystemVerilog?
Answer: case selects based on expression values. randcase selects based on probabilis-
tic weights.
Example:

randcase
1: a = 1;
3: a = 2; // Higher weight, more likely
endcase

Use Case: Modeling probabilistic behaviors such as random traffic generation, error
injection, etc.

Page 20
SystemVerilog Interview Collection VeriCore Academy

Q20. How does inheritance work in SystemVerilog classes? In-

clude a code example.
Answer: SystemVerilog supports single inheritance using ‘extends‘. The derived class
inherits all properties of the base class.
Example:

class Animal;
function void speak();
$display("Generic Animal");
endfunction
endclass

class Dog extends Animal;

function void speak();
$display("Bark");
endfunction
endclass

Usage:

Animal a = new Dog();

a.speak(); // Outputs: Bark

Note: Dynamic dispatch applies, enabling polymorphism.

Page 21
SystemVerilog Interview Collection VeriCore Academy

Q21. What is the difference between ‘static‘ and ‘automatic‘

variables in SystemVerilog?
Answer:

• Static: Retains value across function/task calls.

• Automatic: Allocated on stack, initialized every call.

Example:

function void static_counter();

static int x = 0;
x++;
$display("Static x = %0d", x);
endfunction

function void auto_counter();

automatic int y = 0;
y++;
$display("Auto y = %0d", y);
endfunction

Page 22
SystemVerilog Interview Collection VeriCore Academy

Q22. Explain virtual classes in SystemVerilog with an example.

Answer: A virtual class is an abstract class meant to be inherited and never instantiated
directly.
Use Case: Common base for polymorphic behavior.
Example:

virtual class Packet;

pure virtual function void send();
endclass

class EthernetPacket extends Packet;

function void send(); $display("Ethernet sent"); endfunction
endclass

Instantiation:

Packet p = new EthernetPacket();

p.send(); // Output: Ethernet sent

Page 23
SystemVerilog Interview Collection VeriCore Academy

Q23. Can class handles be assigned to null? How is null handle

dereferencing handled?
Answer: Yes, class handles default to ‘null‘. Dereferencing a null handle causes a runtime
fatal error.
Example:

class C;
int x;
endclass

C obj = null;
$display(obj.x); // Fatal: null handle dereference

Prevention:

if (obj != null)
$display(obj.x);

Page 24
SystemVerilog Interview Collection VeriCore Academy

Q24. What is a copy constructor in SystemVerilog and how is it

implemented?
Answer: A copy constructor duplicates one object’s values into another object during
instantiation.
Syntax:

class Packet;
int data;
function new(Packet p);
this.data = p.data;
endfunction
endclass

Usage:

Packet p1 = new();
p1.data = 100;
Packet p2 = new(p1); // Copy constructor

Tip: Manually copy nested members for deep copy.

Page 25
SystemVerilog Interview Collection VeriCore Academy

Q25. How are constraints prioritized in SystemVerilog? What

happens if multiple constraints affect a variable?
Answer: SystemVerilog doesn’t prioritize constraints explicitly. All active constraints
are processed by the solver to find a legal solution. If constraints conflict, randomization
fails.
Example:

rand int x;
constraint c1 { x > 5; }
constraint c2 { x < 3; } // Conflicts with c1 → randomization fails

Note: Avoid overlapping or contradictory constraints.

Page 26