1. What is ARM stands for?

o ARM stands for “Advanced RISC Machines”, Developed by Acorn Computers Limited,
early 80’s.
o It is the first commercial RISC processor.
o Renamed Advanced RISC Machines (ARM) Limited in the early 90’s

2. What is ARM7?
▪ ARM7 is a 32-bit RISC microprocessor core designed by ARM Ltd., commonly used in
microcontrollers.

3. Is ARM a single core?

ARM is not a processor itself but a company that designs processor architectures and
cores. So, the number of cores depends on which ARM-based processor you're referring
to. Here's a quick breakdown:

Types of ARM Cores

1. Single-Core (Classic ARM Cores)

o Examples: ARM7, ARM9, ARM11

o Used in older or low-power microcontrollers

o Typically single-core

2. Multi-Core (Application Processors)

o Examples: Cortex-A Series (A7, A53, A72, etc.)

o Found in smartphones, tablets, etc.

o Often dual-core, quad-core, octa-core, or more

3. Real-Time Cores (Cortex-M Series)

o Examples: Cortex-M0, M3, M4, M7

o Used in microcontrollers (like STM32, NXP)

o Usually single-core, but some support dual-core (e.g., STM32H7)

4. High-Performance Custom Cores

o Used by companies like Apple (M-series, A-series) or Qualcomm (Kryo)

o These may have 6, 8, 10, or more cores

 4. Difference between Cortex A, cortex M and cortex R with minimum 3 differences
with application?

“Cortex-A is ideal for complex OS applications like smartphones, Cortex-M is optimized for low
power and real-time control in microcontrollers, and Cortex-R focuses on real-time reliability
for critical systems like automotive safety.”

Comparison: Cortex-A vs Cortex-M vs Cortex-R

Feature Cortex-A Cortex-M Cortex-R

Application
Target Use Microcontrollers Real-time systems
processors

Moderate to low High performance with real-

Performance High-performance
performance time features

Full OS (Linux,
OS Support RTOS or bare-metal RTOS or bare-metal
Android)

Anti-lock braking systems

(ABS)
Smartphones, tablets, IoT devices, sensor
Application Airbag systems in
smart TVs nodes, wearables
automotive, robotics,
avionics

5. What does ARM7TDMI stand for?

T: Thumb, D: Debug, M: Multiplier, I: Embedded ICE (In-Circuit Emulator).

T – Thumb Instruction Set

o ARM7TDMI supports both 32-bit ARM instructions and 16-bit Thumb instructions.
o Thumb instructions are more compact, saving memory and improving code density—
useful in embedded systems with limited flash memory.
o The processor can switch between ARM and Thumb modes as needed.

D – Debug Support
o Adds hardware debug features.
o Allows developers to set breakpoints, watch memory, and control execution using JTAG
or ICE interfaces.
o Very useful for diagnosing issues in embedded systems.
 M – Fast Multiplier
o Includes a hardware multiplier for fast multiplication operations.
o Improves performance in applications that need arithmetic operations like signal
processing or control systems.

I – Embedded ICE (In-Circuit Emulator)

o Provides on-chip debugging capabilities without needing external emulators.
o Makes it easier to test and debug real-time code running on hardware.

6. Draw the Data flow model in ARM Core?

o An ARM core can be viewed as functional units connected by buses

o The information on bus may be an instruction or a data item or an address

7. What are the ARM7 architectural features?
1. Von Neumann Architecture + RISC ISA
o ARM7 uses Von Neumann architecture, meaning instructions and data share the
same memory and bus.
o It follows the RISC (Reduced Instruction Set Computing) principle, which
focuses on simple and efficient instructions for faster execution.
2. 32-bit Core Architecture

ARM7 is a 32-bit processor:

o 32-bit ALU (Arithmetic Logic Unit) for arithmetic/logic operations

o 32-bit Instruction Set for ARM mode
o 32-bit Address and Data Bus, allowing access to 4 GB of memory
3. Registers
o It has 37 total 32-bit registers, but only 16 are visible in any given mode (like user,
IRQ, FIQ, etc.)
o This helps with fast context switching, especially in interrupts.
4. High Code Density with Dual Instruction Sets
o Supports ARM (32-bit) and Thumb (16-bit) instruction sets
o Thumb gives better code density, especially in memory-constrained applications
5. Data Type Support
o Can handle 8-bit (byte), 16-bit (halfword), and 32-bit (word) data
o Makes it flexible for dealing with different types of data sizes
6. Memory Alignment
o Word (32-bit) data must be aligned at 4-byte boundaries
o Halfword (16-bit) data must be aligned at even byte boundaries
o Proper alignment ensures faster memory access and prevents data corruption
7. Load-Store Architecture
o ARM7 uses a load-store model, meaning only load (LDR) and store (STR)
instructions access memory
o All other operations are done on registers, improving speed and efficiency
▪ LOAD: Register ← Memory
▪ STORE: Register → Memory

8. What is pipelining in ARM7 processors, and what are the different stages involved?

Pipelining is a technique used in ARM7 processors to increase instruction throughput by

overlapping the execution of multiple instructions. Instead of processing one
instruction at a time (sequential execution), pipelining divides the execution into stages,
allowing several instructions to be processed simultaneously at different stages.
The ARM7 processor uses a 3-stage pipeline, which consists of:
1. Fetch (F):
The processor retrieves the instruction from memory.
2. Decode (D):
The fetched instruction is decoded to understand what actions are needed and which
registers or memory it will use.
3. Execute (E):
The instruction is executed, i.e., the operation is performed (arithmetic, memory
access, etc.).
These stages overlap such that while one instruction is being executed, the next is being
decoded, and another is being fetched. This increases efficiency and instruction
throughput without increasing the clock speed.

9. What are the different processor modes in ARM7, and how do they control access
to the CPSR register?
In the ARM7 architecture, the processor mode determines which registers are active
and the access permissions to the CPSR (Current Program Status Register), particularly
the control and flag fields.
Access Levels:
• Privileged Modes:
Allow full read-write access to the CPSR (control + flags).
• Non-Privileged Mode (User Mode):
Allows read-only access to the control field, but full access to condition flags.

User Mode (usr) – Non-Privileged

• Default mode for running user applications.

• Restricted access to control fields in CPSR.

Fast Interrupt Request Mode (fiq) – Privileged

• Triggered by high-priority interrupts via the nFIQ pin.

• Minimal latency due to reduced context saving.
• Interrupt nesting is disabled for fast response.

Interrupt Request Mode (irq) – Privileged

• Triggered by normal (low-priority) interrupts via the nIRQ pin.

• Higher latency than FIQ.
• Interrupt nesting is allowed.

Supervisor Mode (svc) – Privileged

• ARM 7 enters this mode on reset/power up.

• It is used to execute the BIOS/Bootloader Program.
• Is generally the mode that an operating system kernel operates in.
• This mode can also be invoked by the programmer by SWI (Software Interrupt)
Instruction.

Abort Mode (abt) – Privileged

• Entered when memory access fails (e.g., invalid address or permission).

Undefined Mode (und) – Privileged

• Triggered when an undefined instruction is executed.

• Often used for coprocessor access handling.

System Mode (sys) – Privileged

• Identical to User Mode but with full CPSR access.

• Used when user-level code needs privileged execution.

10. Why is ARM not considered a "pure" RISC (Reduced Instruction Set Computer)
architecture? What features differentiate it from traditional RISC designs?
While ARM (Advanced RISC Machine) is based on the RISC architecture principles, it
is not a pure RISC processor. Traditional RISC architectures are characterized by
simple, fixed-length instructions, single-cycle execution, and uniform instruction
formats. However, ARM deviates from these in several ways to optimize for
performance, code density, and embedded efficiency.

Key Features That Make ARM Not Pure RISC:

1. Variable Cycle Execution:
o Unlike classic RISC, where each instruction ideally executes in one cycle, ARM
has some instructions that require multiple cycles depending on their
complexity (e.g., load/store multiple, memory access).
2. Inline Barrel Shifter:
o ARM integrates a barrel shifter into many data processing instructions, allowing
complex operations like shifts and rotates within a single instruction. This
increases instruction complexity—uncommon in pure RISC.
3. Thumb 16-bit Instruction Set:
o ARM introduces the Thumb mode, which compresses frequently used 32-bit
instructions into 16-bit format for better code density. This dual-instruction set
system (ARM + Thumb) departs from the uniform instruction format of RISC.
4. Conditional Execution:
o ARM supports conditional execution for most instructions using condition
codes (e.g., EQ, NE, GT). This reduces branching but adds complexity, which
pure RISC avoids.
5. Enhanced DSP Instructions:
 o ARM includes Digital Signal Processing (DSP)-oriented instructions to
accelerate multimedia and signal operations—another deviation from the
minimalist RISC design philosophy.
6. Jazelle Support:
o ARM processors include Jazelle DBX, which allows direct execution of Java
bytecodes (up to 70%). This integration of high-level instruction support is
atypical in pure RISC processors.