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VHDL Tutorial

A hardware model in VHDL is described in two parts, the entity declaration part and the associated architecture body part. The entity declaration gives a name to the model being developed and also declares its external interface signals. The architecture body defines the internal details of the model -- including any internal signals and one or more concurrent statements.

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VHDL Tutorial

Uploaded by

Kishore Sri

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VHDL Tutorial

Presenter : Raj Singh

IC Design Group CEERI, Pilani 333 031 Rajasthan, India

Tel : Fax : E-Mail :

01596-242359 01596-242294 [email protected]

VHDL Tutorial : Introduction

Introduction Overview Constructs Usage Examples

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VHDL Tutorial : Introduction

History of VHDL

1981 : Department of Defense, USA launches the Very High Speed Integrated Circuits (VHSIC) project. 1983 : Request for Proposal (RFP) issued by US Air Force to develop a language for hardware design description. The winner was a team composed of Intermetrics, IBM and TI. 1985 : VHDL version 7.2 made available. 1986 : Initial suite of support software released. IEEE starts effort of standardizing VHDL.
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VHDL Tutorial : Introduction

History of VHDL

1987 : IEEE-1076 Standard released, VHDL-87. 1993 : Revised IEEE-1076 Standard released, VHDL-93. 2001 : Revised IEEE-1076 Standard released, VHDL-2001. 2002 : Work on VHDL-200x started.

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VHDL Tutorial : Overview

Introduction Overview Constructs Usage Examples

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VHDL Tutorial : Overview

Model of a Hardware in VHDL A hardware model in VHDL is described in two parts, the entity declaration part and the associated architecture body part.
ENTITY

BODY 1

BODY 2

BODY N

VHDL Tutorial : Constructs

Types, Operators and Objects in VHDL Every modeling language models its subject using certain value sets, operations on those value sets and dening storage locations to hold the values. VHDL is a strongly-typed language. In VHDL, distinct value sets are dened through different type declarations. The language also has predened types. The set of predened types (and subtypes) are contained in the VHDL package STANDARD. They are : Boolean, bit, character, severity_level, integer, natural, positive, real, time,
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VHDL Tutorial : Constructs

delay_length, string, bit_vector, file_open_kind, file_open_status. A listing of the package STANDARD is given in Annexure-I. Different operations on values of specic types are dened with the help of function declaration and denitions. The language also provides a set of pre-dened operators for the specic pre-dened types.

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VHDL Tutorial : Constructs

VHDL creates four distinct classes of objects for storing values it manipulates. This is done through object declarations. The four object classes are : 1. Signal. 2. Variable. 3. Constant. 4. File.

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VHDL Tutorial : Constructs

Types, Operators and Objects in VHDL

VHDL provides unlimited number of data types for characterizing the values held by signal, variable and constant. Data types are categorized into four major categories : 1. Scalar types. 2. Composite types. 3. Access types. 4. File types.

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Subtypes of Types A subtype is a type with constraints. The constraint species the subset of values for the type. The type is called the base type of the subtype. An object is said to belong to a subtype if it is of the base type and if it satises the constraint. Subtype declarations are used to declare subtypes. An object can be declared to belong to either a type or a subtype. The set of operations belonging to a subtype is the same as that associated with its base type. Subtypes are useful for range checking and for imposing additional constraints on types. Example :
subtype MY_INTEGER is integer range 1 to 64; subtype MEM_ADDRESS is BIT_vector(31 downto 0); type DIGIT is (0,1,2,3,4, 5,6,7,8,9); subtype MID_DIGIT is DIGIT range 3 to 6;
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VHDL Tutorial : Constructs

Types, Operators and Objects in VHDL

Access Types : Values belonging to an access type are pointers to a dynamically allocated object of some other type. We will not be discussing them any further. File Types : Objects of le types represent les in the host environment. They provide a mechanism by which a VHDL design communicates with the host environment. The le type declarations and declaration of le objects will be covered later.

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VHDL Tutorial : Constructs

Types, Operators and Objects in VHDL

Operators : The operators in VHDL are classied into seven categories : 1. Logical Operators. 2. Relational Operators. 3. Shift Operators. 4. Adding Operators. 5. Sign Operators. 6. Multiplying Operators. 7. Miscellaneous Operators.
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VHDL Tutorial : Constructs

Operators in VHDL Logical Operators : and, or, nand, nor, xor, xnor, not Example : variable SUM, A, B : BIT; SUM := A xor B;

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VHDL Tutorial : Constructs

Relational Operators : =, /=, <, <=, >, >= Example :

type FOUR_LOGIC_LEVEL is (U,0,1,Z); FOUR_LOGIC_LEVEL(U) < FOUR_LOGIC_LEVEL(Z) if (A < 10) then Z <= 1; if (TEMP >= CHECK) then KOUT := 0;

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VHDL Tutorial : Constructs

Shift Operators : Logical sll, srl Arithmetic sla, sra Rotate rol, ror. Example : "1001010" sll 2 gives "0101000" "1001010" rol 2 gives "0101010"
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VHDL Tutorial : Constructs

Adding Operators : +, -, & (concatenation) Example : variable SUM1, SUM2, SUM1 := A + B; SUM2 := A - B; constant S1 : string constant S2 : string constant S3 : string A, B : integer;

:= "abc"; := "def"; := S1 & S2; -- "abcdef"

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Objects of class signal are declared in : architecture-item-declaration zone : signals declared here are accessible throughout the architecture body, but not outside it. entity-item-declaration zone : signals declared here are accessible throughout all the architecture bodies associated with the entity. block-item-declaration zone of a concurrent block statement : signals declared here are accessible throughout the block (including any nested subblocks). in package declarations.
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VHDL Tutorial : Constructs

Creating Signal Waveforms

Phase 1 T T+8 T+13 T+50 ns

Phase1 <= 0, 1 after 8 ns, 0 after 13 ns, 1 after 50 ns; Signal Drivers
RESET curr@now 3@T+5ns 21@T+10ns 14@T+17ns

RESET <= 3 after 5 ns, 21 after 10 ns, 14 after 17 ns;

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VHDL Tutorial : Constructs

Effect of Transport Delay on Signal Drivers

RX_DATA curr@now 11@T+10ns 20@T+22ns

RX_DATA

curr@now 11@T+10ns 35@T+18ns

signal RX_DATA : NATURAL; ... process begin ... RX_DATA <= transport 11 after 10 ns;
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VHDL Tutorial : Constructs

... RX_DATA <= transport 20 after 22 ns; ... RX_DATA <= transport 35 after 18 ns; ... end process; The following summarizes the rules for adding a new transaction to a driver when transport delay is used : 1. If the delay time of the new transaction is greater than those of all the transactions already present on the driver, then the new transaction is added at the end of the driver.
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VHDL Tutorial : Constructs

2. If the delay time of the new transaction is earlier than or equal to one or more transactions on the driver, then these transactions are deleted from the driver and the new transaction is added at the end of the driver.

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VHDL Tutorial : Constructs

Effect of Inertial Delay on Signal Drivers

TX_DATA

curr@now 22@20ns

TX_DATA

curr@now 33@15ns

Sequential Statements in VHDL Following is the list of sequential statements used in a process : variable assignment statement. signal assignment statement. wait statement. if statement.
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VHDL Tutorial : Constructs

Sequential Statements in VHDL

case statement. loop statement. next statement. exit statement. null statement.
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VHDL Tutorial : Constructs

VHDL Tutorial : Constructs

process(A,B) begin . . . end process;

process begin . . . wait on A,B; end process;

process begin A <= 1; B <= A; wait for 100 ns; end process;
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vs.

process begin A <= 1; wait for 0 ns; B <= A; wait for 100 ns; end process;
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VHDL Tutorial : Constructs

Example : wait wait wait wait wait on A, B, C; until A = B; for 10 ns; on CLOCK for 20 ns; -- max. 20 ns wait on CARRY until (SUM > 100) for 50 ms;

Example : Use of wait statement process variable Temp1, Temp2 : BIT; begin Temp1 := A and B;
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VHDL Tutorial : Constructs

wait for 5 ns; Temp2 := C and D; wait for 3 ns; Z <= Temp1 or Temp2; wait on A, B, C, D; -- a process can have -- many wait statements end process;

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VHDL Tutorial : Constructs

Sequential Statements in VHDL Assertion Statement Assertion statements are useful in modeling constraints of an entity. Syntax : assert condition [report message] [severity severity-level]; Example : assert Enable /= X report "Unknown Value on Enable" severity error;
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VHDL Tutorial : Constructs

Sequential Statements in VHDL Procedure Call Statement Syntax : procedure-name [(association-list)]; association-list may be specied using positional association or named association.
Example : type OP_CODE is (ADD, SUB, MUL, DIV, LT, LE, EQ); . . . procedure ALU_Unit(
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VHDL Tutorial : Constructs

A, B : in integer; OP : in OP_CODE; Z : out integer; ZCOMP : out Boolean) is begin case OP is when ADD when SUB when MUL when DIV when LT when LE when EQ end case; end ALU_Unit; -- using positional association. ALU_Unit(D1, D2, ADD, SUM, COMP); -- using named association. ALU_Unit(Z => SUM, B => D2, A => D1, OP => ADD, ZCOMP => COMP);
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=> => => => => => =>

Z := A + Z := A Z := A * Z := A / ZCOMP := ZCOMP := ZCOMP :=

B; B; B; B; (A < B); (A <= B); (A = B);

VHDL Tutorial : Constructs

Sequential Statements in VHDL Return Statement This statement is used to terminate the execution of a subprogram. Syntax : return [expression]; For a procedure when this statement is executed, control returns to the point at which the procedure was called. For a function, the return statement returns a value. This value substitutes for the function call in the calling expression.
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VHDL Tutorial : Constructs

Example : function AND_Function(X, Y : in BIT) return BIT is begin if X = 1 and Y = 1 then return 1; else return 0; end if; end AND_Function; . . . Z <= A or AND_Function(C, D); . . .
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VHDL Tutorial : Usage

Introduction Overview Constructs Usage Examples

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VHDL Tutorial : Usage

Data-Flow Modeling This style of modeling views the digital system as a network of processing stages through which the input data ows and gets processed as it ows through them. The main VHDL construct for data-ow modeling is the concurrent signal assignment statement. Besides, the concurrent signal assignment statement, the conditional signal assignment statement and the selected signal assignment statement are used for this style of modeling. The collection of these concurrent statements models the network of processing stages, with each statement serving as an abstraction of a processing stage i.e. processing is data-driven.
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VHDL Tutorial : Usage

I1 I2 I3 I4

S1 S3 S2 ZOUT

architecture Data_flow of NAND4 is signal S1, S2, S3 : BIT; begin S1 <= I1 and I2; S2 <= I3 and I4; S3 <= S1 and S2; ZOUT <= not S3; end Data_flow;

The order of statements in the above architecture body is unimportant as they are concurrent statements.
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VHDL Tutorial : Usage

Example : Modeling a Multiplexer stage (using conditional signal assignment). ZOUT <= IN0 after 5 ns when S1 = 0 and S0 = 0 else IN1 after 5 ns when S1 = 0 and S0 = 1 else IN2 after 5 ns when S1 = 1 and S0 = 0 else IN3 after 10 ns; Example : Modeling a Multiplexer stage (using selected signal assignment). signal MUX_Control : BIT_vector(1 downto 0); with MUX_Control select ZOUT <= IN0 after 5 ns when "00", IN1 after 5 ns when "01", IN2 after 5 ns when "10", IN3 after 10 ns when "11";

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Structural Model Example

I1 I2 I3 I4 U1

S1 U3 S3 U4 ZOUT

A 4-input NAND gate constructed from three 2-input AND gates and one INVERTER.
entity NAND4 is port(I1, I2, I3, I4 : in BIT; ZOUT : out BIT); end NAND4; architecture AND2_INVERT of NAND4 is
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VHDL Tutorial : Usage

-- declarative zone for architecture items signal S1, S2, S3 : BIT; component AND2 port(A, B : in BIT; C : out BIT); end component; component INVERT port(X : in BIT; Y : out BIT); end component; begin -- concurrent statement zone. For a purely -- structural architecture only component -- instantiation statements are used. U1 U2 U3 U4 : : : : AND2 port map(I1, I2, S1); AND2 port map(I3, I4, S2); AND2 port map(S1, S2, S3); INVERT port map(S3, ZOUT);
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VHDL Tutorial : Usage

end AND2_INVERT;

The above example is a valid VHDL structural model that can be successfully compiled but not simulated. This is because component instances in the architecture have no associated behaviour; they merely describe the structure e.g. a board with wired sockets, but no ICs plugged in. In order to be able to simulate the model, we need to associate a desired entity and one of its architecture bodies with each component instance. In VHDL parlance it is called conguring a component instance. The conguration of an architecture body is complete when all the components instances in it have been congured. Conguration (of component instances and architectures) in VHDL is achieved through the following :
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VHDL Tutorial : Usage

conguration specication. conguration declaration. Conguration specications are included within the architecture body itself in the architecture-item-declaration region. Conguration declaration is a separate design unit that is used to hierarchically congure the selected architecture of an entity.
Example : Conguring an architecture body through the use of conguration specication. architecture AND2_INVERT of NAND4 is -- declarative zone for architecture items signal S1, S2, S3 : BIT;
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VHDL Tutorial : Usage

component AND2 port(A, B : in BIT; C : out BIT); end component; component INVERT port(X : in BIT; Y : out BIT); end component; -- configuring the instances. for U1, U2, U3 : AND2 use entity TWO_INPUT_AND(Beh1); for U4 : INVERT use entity INVERTER(Data_flow); begin -- concurrent statement zone. For a purely -- structural architecture only component -- instantiation statements are used. U1 : AND2 port map(I1, I2, S1);
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VHDL Tutorial : Usage

U2 : AND2 port map(I3, I4, S2); U3 : AND2 port map(S1, S2, S3); U4 : INVERT port map(S3, ZOUT); end AND2_INVERT; Example : conguring and entity and its architecture body through the use of conguration declaration. configuration My_config of NAND4 is for AND2_INVERT for all : AND2 use entity TWO_INPUT_AND(Beh1); end for; -- AND2 for U4 : INVERT use entity INVERTER(Data_flow); end for; -- INVERT end for; -- AND2_INVERT end My_config;
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VHDL Tutorial : Usage

Attributes in VHDL An attribute is a named characteristic of items belonging to the following classes : types, subtypes. procedures, functions. signals, variables, constants.

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For example, if one declares signal CLOCK : BIT; then the following expression can be used in VHDL code to detect the rising edge of CLOCK : CLOCKevent and CLOCK = 1 If the value of this expression is TRUE, then a rising edge of the CLOCK has occurred at the current simulation time. Thus, one can model a positive-edge triggered D ip-op functionality as follows : if (CLOCKevent and CLOCK = 1) then
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VHDL Tutorial : Usage

Q <= D; end if; CLOCKlastevent is the time value at which the last change in the CLOCK signal occurred. This can be used to check the setup (or hold) time.

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VHDL Tutorial : Usage

Use of Packages and Libraries Within a design unit in the VHDL design le (the design le comprises of a collection of design units), visibility of items contained in a package that has been analyzed into a design library can be achieved (or effected) by placing the library and use clauses before the design unit.
library work; -- work is the default library. The -- library clause above can be dropped. use work.My_FUNC.all; . . . entity declaration . . . library CMOS; use CMOS.NOR2; . . . entity declaration or architecture body . . .
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VHDL Tutorial : Usage

Block Statement Block statement is a concurrent statement. By itself it has no execution semantics, rather it provides additional semantics for statements that are enclosed within it. It is primarily used for the following purposes : 1. To disable signal drivers by using guards. 2. To create an item declaration zone with a limited scope. 3. To demarcate a portion of the design or a level in design hierarchy.
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VHDL Tutorial : Usage

Block statements can be nested. Any number of concurrent statements (including none) can appear within a block.

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NOR2 : block -- A block for the bound -- entitys architecture generic(PT_HL, PT_LH : TIME); -- generics of the block correspond to -- the generics in the entity declaration

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generic map(PT_HL => FALL_TIME, PT_LH => RISE_TIME); -- Mapping of generics from -- entity to component port(A, B : in BIT; Z : out BIT); -- ports of the block correspond to the -- ports in the entity declaration port map(A => S0, B => S1, Z => Q); -- Mapping of ports from -- entity to component begin -- statements in architecture body -- appear here end block NOR2; end block N1;
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VHDL Tutorial : Usage

Generate Statement Concurrent statements can be conditionally selected or replicated during the elaboration phase using the generate statement. There are two forms of the generate statement : 1. For-generation scheme : for replicating concurrent statements using a forloop like scheme. 2. If-generation scheme : for conditionally elaborating concurrent statements. The generate statement is interpreted during elaboration. It has no simulation semantics. It resembles a macro expansion and provides a compact description of regular structures like memories, registers and counters.
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VHDL Tutorial : Usage

Syntax (for-generation scheme) : generate-label : for generate-identifier in discrete-range generate [block-declarations begin] concurrent-statements end generate [generate-label]; Example : Using for-generation scheme.
A COUT
4

FULL_ADD4
4

CIN

SUM

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A(3) B(3)
CAR(4) FA(3)

A(2) B(2)
FA(2)

A(1) B(1)
CAR(2) FA(1)

A(0) B(0)
CAR(1) FA(0) CAR(0)

CAR(3)

COUT

CIN

SUM(3)

SUM(2)

SUM(1)

SUM(0)

entity FULL_ADD4 is port(A, B : in BIT_vector(3 downto 0); CIN : in BIT; SUM : out BIT_vector(3 downto 0); COUT : out BIT); end FULL_ADD4; architecture FOR_GENERATE of FULL_ADD4 is component FULL_ADDER port(PA, PB, PC : in BIT; PSUM, PCOUT: out BIT); end component; signal CAR : BIT_vector(4 downto 0);
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VHDL Tutorial : Usage

begin CAR(0) <= CIN; GK : for K in 3 downto 0 generate FA : FULL_ADDER port map(A(K), B(K), CAR(K), SUM(K), CAR(K+1)); end generate GK; COUT <= CAR(4); end FOR_GENERATE;

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-- Thus, type LINE is an access type -- (pointer) which points to a STRING. variable N1_VAR : BIT_vector(0 to 3); variable N2_VAR : integer; begin if ((CLOCKevent and CLOCK = 1) and (not ENDFILE(VECTORS)) then READLINE(VECTORS, BUF); -- READ() is an overloaded procedure READ(BUF, N1_VAR); READ(BUF, N2_VAR); -- apply values read to input signals -- of entity under test N1 <= N1_VAR;
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VHDL Tutorial : Usage

N2 <= N2_VAR; elsif (ENDFILE(VECTORS)) then report "Finished All the Vectors"; end if; end process;

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Test Bench To test the VHDL model of any digital hardware we need to apply test stimuli waveforms to its inputs, capture the response waveforms at the models outputs and compare the captured response waveforms with the expected output waveforms. A VHDL model written for the above purpose essentially simulates the running of a test on a hardware test setup with the Device Under Test (DUT) plugged in the DUT socket and is typically called a test bench.

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Test Bench Blocks

STIMULUS GENERATOR

DEVICE UNDER TEST

RESPONSE CAPTURE AND COMPARISON

One can use VHDL not only for modeling the device (DUT) but also for modeling the Stimulus Generator, Response Capture and Response Analysis Block i.e. the entire test bench.

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Example : A typical test bench template. entity TEST_BENCH is end TEST_BENCH; architecture ILLUSTRATIVE of TEST_BENCH is -- declare DUT in a component declaration. -- declare local signals that will connect to the DUTs I/Os. begin ---------Include a process that will generate the stimulus waveforms on signals that will connect to the DUTs inputs. Instantiate the DUT such that these signals connects to the DUTs inputs. Include a process that will monitor and compare the captured response waveforms from the DUTs outputs by having all the local signals that connect to the DUTs outputs on its sensitivity list.

end ILLUSTRATIVE;
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VHDL Tutorial : Examples

AND OR Z

Example : Behavioural modeling of AOI circuit. entity AOI is port(I1, I2, I3 : in BIT; Z : out BIT); end AOI;

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architecture BEHAVIOUR1 of AOI is begin process(I1, I2, I3) variable V1, V2, V3 : BIT; begin V1 := I1 and I2; V2 := V1 or I3; V3 := not V2; Z <= V3 after 3 ns; end process; end BEHAVIOUR1;

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In the top-down design method after initially capturing the behavioural description, such as the one in the example above (comprising of a single process statement), partitioning of the behaviour into multiple interacting processes is done. In the next step, entities can be dened that have their behaviours described by the individual processes. These entities can then be connected (via corresponding component declarations, their instantiations and congurations) to produce a structural description. This constitutes one step downwards in the top-down design procedure. More than one downward steps are typically required before the components become realizable/ synthesisable through a bottom-up step.

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entity AOI is port(I1, I2, I3 : in BIT; Z : out BIT); end AOI; architecture BEHAVIOUR2 of AOI is signal S1 : BIT; begin P1 : process(I1, I2) begin S1 <= I1 and I2 after 1 ns; end process P1; P2 : process(S1, I3) begin Z <= S1 nor I3 after 2 ns; end process P2; end BEHAVIOUR2;
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Behaviour to Structure
entity AOI is port(I1, I2, I3 : in BIT; Z : out BIT); end AOI; architecture STRUCT1 of AOI is signal S1 : BIT; component P1 port(I1, I2 : in BIT; Z : out BIT); end component; ----note that we require only one kind of component here as both AND and NOR gates are of 2-input and 1-output variety.

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-- configuration specifications. -- assuming entity-architecture pair is -- defined for AND2 and NOR2 gates. for U1 : P1 use entity AND2(AND2) port map(I1, I2, Z); -- (AND2) specifies the architecture -- chosen for the entity AND2. for U2 : P1 use entity NOR2(NOR2) port map(I1, I2, Z); -- (NOR2) specifies the architecture -- chosen for the entity NOR2. begin U1 : P1 port map(I1, I2, S1); U2 : P1 port map(S1, I3, Z); end STRUCT1;
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Structural Modeling Modeling of the chip/system as an interconnection of available cells, parts, and/or components.
Requirement Description of external interface of the chip Description of list of component/part types (with pin identiers) Description of actual placements (instantiations) of components and wiring Description of the behaviour of instanced parts/components
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VHDL Construct entity declaration component declaration

component instantiation statements (with port map) Implied or Explicit

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Implied : An entity of the same name as the component together with its

associated most recently analyzed architecture supplies the behaviour for the instanced part.

Explicit : The conguration specication or the conguration declaration

serve to bind a particular instance or a chosen set of instances to specic entity-architecture pairs that would supply the behaviour for the instance.

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end component; end cell_list;

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Example 6 : Use of IEEE std logic 1164.

library IEEE; use IEEE.std_logic_1164.all; entity AND2 is generic(AND2_delay : TIME); port(I1, I2 : in std_logic; Z : out std_logic); end AND2; . . . AND2s architecture body . . . library IEEE; use IEEE.std_logic_1164.all; entity NOR2 is generic(NOR2_delay : TIME); port(I1, I2 : in std_logic; Z : out std_logic); end NOR2; . . . NOR2s architecture body . . .
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VHDL Tutorial : Examples

VHDL Tutorial : Examples

VITAL Modeling Standard IEEE standard 1076.4 (Standard VITAL ASIC Modeling Specication) provides a standard for the usage of the VHDL language and modeling style for modeling ASIC libraries. It permits back-annotation of post-route SDF delay data onto a structural VHDL model via the use of generics in an automated way (through the development of tools for this purpose based on the standard).

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Data-Flow Modeling Modeling of hardware as a ow of data through stages (or a network) of operators which modify the data as it ows through them. It is a convenient way of specifying processing on data (which implies a network of logic gates). Logic synthesis tools can take a data-ow description and convert it into a structural description (comprising of an interconnection of available gates in a target library).

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MINUTES_CARRY := 0; HOURS_CARRY := 0; if (SECONDS /= 59) then SECONDS_next <= SECONDS + 1; else SECONDS_next <= 0; MINUTES_CARRY := 1; end if; if (MINUTES_CARRY = 1) then if (MINUTES /= 59) then MINUTES_next <= MINUTES + 1; else MINUTES_next <= 0; HOURS_CARRY := 1; end if; end if; if (HOURS_CARRY = 1) then
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if (HOURS /= 12) then HOURS_next <= HOURS + 1; else HOURS_next <= 1; end if; end if; end if; end process COMBI; end RTL_3;

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Special Encoder

I4 I3 I2 I1 MSB LSB

entity SPECIAL_ENCODER is generic(DELAY : TIME := 5 ns); port(I1, I2, I3, I4 : in BIT; MSB, LSB : out BIT); end SPECIAL_ENCODER; architecture BEHAVIOURAL of SPECIAL_ENCODER is begin process(I1, I2, I3, I4) variable BIT1, BIT0 : BIT;
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VHDL Tutorial : Examples

begin if ((I1 or I2 or I3 or I4) = 0) then assert FALSE report "ALL INPUTS 0"; else if I4 = 1 then BIT1 := 1; BIT0 := 1; elsif I3 = 1 then BIT1 := 1; BIT0 := 0; elsif I2 = 1 then BIT1 := 0; BIT0:=1; else BIT1 := 0; BIT0 := 0; end if; MSB <= BIT1 after DELAY; LSB <= BIT0 after DELAY; end if; end process; end BEHAVIOURAL; package TEST_BENCH_DECL is type TWO_CHANNEL_TRACE_ELEMENT is record CH1 : BIT; CH0 : BIT;
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VHDL Tutorial : Examples

Count = 1

Count = 0

Count = 1

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VHDL Tutorial : Examples

Example : Modulo-3 Counter (if statement based model). package COUNT_LOGIC is type STATE is (COUNT_0, COUNT_1, COUNT_2); end COUNT_LOGIC; use work.COUNT_LOGIC.all; entity COUNTER_3 is port(CLK : in BIT; ENABLE : in BIT; RESET_BAR : in BIT; COUNT_ZERO : out BIT := 1; COUNT_ONE : out BIT := 0; COUNT_TWO : out BIT := 0); end COUNTER_3; architecture IF_BASED of COUNTER_3 is signal PRESENT_STATE : STATE := COUNT_0; begin
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VHDL Tutorial : Examples

COUNTING : process(CLK, RESET_BAR) begin if RESET_BAR = 0 then PRESENT_STATE <= COUNT_0; COUNT_ZERO <= 1; COUNT_ONE <= 0; COUNT_TWO <= 0; elsif (CLK = 1 and CLKevent and ENABLE = 1) then if (PRESENT_STATE = COUNT_0) then PRESENT_STATE <= COUNT_1; COUNT_ONE <= 1; COUNT_ZERO <= 0; elsif (PRESENT_STATE = COUNT_1) then PRESENT_STATE <= COUNT_2; COUNT_TWO <= 1; COUNT_ONE <= 0;
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VHDL Tutorial : Examples

elsif (PRESENT_STATE = COUNT_2) then PRESENT_STATE <= COUNT_0; COUNT_ZERO <= 1; COUNT_TWO <= 0; end if; end if; end process COUNTING; end IF_BASED;

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VHDL Tutorial : Examples

Example : Modulo-3 Counter (case statement based model).

package COUNT_LOGIC is type STATE is (COUNT_0, COUNT_1, COUNT_2); end COUNT_LOGIC; use work.COUNT_LOGIC.all; entity COUNTER_3 is port(CLK : in BIT; ENABLE : in BIT; RESET_BAR : in BIT; COUNT_ZERO : out BIT := 1; COUNT_ONE : out BIT := 0; COUNT_TWO : out BIT := 0); end COUNTER_3; architecture CASE_BASED of COUNTER_3 is signal PRESENT_STATE : STATE := COUNT_0; begin
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Example : Modulo-3 Counter (selected signal assignment based model).

package COUNT_LOGIC is type STATE is (COUNT_0, COUNT_1, COUNT_2); type CONDITION is (CONDITION_0, CONDITION_1, CONDITION_2, CONDITION_NOTRAN); end COUNT_LOGIC; use work.COUNT_LOGIC.all; entity COUNTER_3 is end COUNTER_3; architecture SEL_SIG of COUNTER_3 is signal signal signal signal signal begin
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PRESENT_STATE : STATE := COUNT_0; SEL_CONDITION : CONDITION; OUTPUT : BIT_vector(2 downto 0); CLK, ENABLE, RESET_BAR : BIT; COUNT_ZERO, COUNT_ONE, COUNT_TWO : BIT;

VHDL Tutorial : Examples

SEL_CONDITION <= CONDITION_0 when (RESET_BAR = 0) or (RESET_BAR = 1 and PRESENT_STATE = COUNT_2 and ENABLE = 1 and CLK = 1 and CLKevent) else CONDITION_1 when (RESET_BAR = 1) and (PRESENT_STATE = COUNT_0 and ENABLE = 1 and CLK = 1 and CLKevent) else CONDITION_2 when (RESET_BAR = 1) and (PRESENT_STATE = COUNT_1 and ENABLE = 1 and CLK = 1 and CLKevent) else CONDITION_NOTRAN; with SEL_CONDITION select PRESENT_STATE <= COUNT_0 when CONDITION_0,
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VHDL Tutorial : Examples

COUNT_1 when CONDITION_1, COUNT_2 when CONDITION_2, PRESENT_STATE when CONDITION_NOTRAN; with SEL_CONDITION select OUTPUT <= "001" when CONDITION_0, "010" when CONDITION_1, "100" when CONDITION_2, OUTPUT when CONDITION_NOTRAN; COUNT_ZERO <= OUTPUT(0); COUNT_ONE <= OUTPUT(1); COUNT_TWO <= OUTPUT(2); CLK <= not(CLK) after 25 ns; RESET_BAR <= 0, 1 after 50 ns; ENABLE <= 0, 1 after 100 ns, 0 after 300 ns; end SEL_SIG;

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VHDL Tutorial : Examples

Example : Modulo-3 Counter (if and case statement based model).

package COUNT_LOGIC is type STATE is (COUNT_0, COUNT_1, COUNT_2); end COUNT_LOGIC; use work.COUNT_LOGIC.all; entity COUNTER_3 is port(CLK : in BIT; ENABLE : in BIT; RESET_BAR : in BIT; COUNT_ZERO : out BIT := 1; COUNT_ONE : out BIT := 0; COUNT_TWO : out BIT := 0); end COUNTER_3; architecture CASE_IF of COUNTER_3 is signal PRESENT_STATE : STATE := COUNT_0; begin
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VHDL Tutorial : Examples

COUNTING : process(CLK, RESET_BAR) begin if RESET_BAR = 0 then PRESENT_STATE <= COUNT_0; COUNT_ZERO <= 1; COUNT_ONE <= 0; COUNT_TWO <= 0; elsif (CLK = 1 and CLKevent and ENABLE = 1) then case PRESENT_STATE is when COUNT_0 => PRESENT_STATE <= COUNT_1; COUNT_ONE <= 1; COUNT_ZERO <= 0; when COUNT_1 => PRESENT_STATE <= COUNT_2; COUNT_TWO <= 1;
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VHDL Tutorial : Annexures

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VHDL Tutorial : Annexures

RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN FUNCTION RETURN

std_logic_vector; To_X01Z (b : BIT_vector) std_ulogic_vector; To_X01Z (b : BIT) X01Z; To_UX01 (s : std_logic_vector) std_logic_vector; To_UX01 (s : std_ulogic_vector) std_ulogic_vector; To_UX01 (s : std_ulogic) UX01; To_UX01 (b : BIT_vector) std_logic_vector; To_UX01 (b : BIT_vector) std_ulogic_vector; To_UX01 (b : BIT) UX01;

-- edge detection FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;

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VHDL Tutorial : Annexures

FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; -- object contains FUNCTION Is_X (s : RETURN BOOLEAN; FUNCTION Is_X (s : RETURN BOOLEAN; FUNCTION Is_X (s : RETURN BOOLEAN; END std_logic_1164; an unknown std_ulogic_vector) std_logic_vector) std_ulogic)

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