Unit 1

Draw and Explain 80386 DX Architecture?

Ans:

Or
Basically, it has 5 functional units which are as follows:
· Bus Interface Unit
· Code Fetch Unit
· Instruction Decode Unit
· Execution Unit
· Memory Management Unit
1. Bus Interface Unit
1. The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as a 32-bit
address bus.
2. Whenever a need for instruction or a data fetch is generated by the system then the
BIU generates signals (according to the priority) for activating the data and address
bus in order to fetch the data from the desired address.
3. The BIU connects the peripheral devices through the memory unit and also controls
the interfacing of external buses with the coprocessors.
2. Code Prefetch Unit
1. This unit fetches the instructions stored in the memory by making use of system
buses.
2. Whenever the system generates a need for instruction then the code prefetch unit
fetches that instruction from the memory and stores it in a 16-byte prefetch queue.
3. To speed up the operation this unit fetches the instructions in advance and the
queue stores these instructions.
4. As this unit fetches one double word in a single access. So, in such a case, it is not
necessary that each time only a single instruction will be fetched, as the fetched
instruction can be parts of two different instructions.
3. Instruction Decode Unit
 1. We know that instructions in the memory are stored in the form of bits.
2. This unit decodes the instructions stored in the prefetch queue.
3. Basically the decoder changes the machine language code into assembly language
and transfers it to the processor for further execution.
4. Execution Unit
1. The decoded instructions are stored in the decoded instruction queue. These
instructions are provided to the execution unit in order to execute the instructions.
2. The execution unit controls the execution of the decoded instructions.
3. This unit has a 32-bit ALU, that performs the operation over 32-bit data in one cycle.
Also, it consists of 8 general purpose as well as 8 special purpose registers.These are
used for data handling and calculation of offset addresses.
5. Memory Management Unit
This unit has two separate units within it. These are
· Segmentation Unit and
· Paging Unit
Segmentation unit:
1. Segmentation unit has the ability to convert the logical address into the linear
address at the time of executing an instruction.
2. The segmentation unit compares the effective address for the length limit
specified in the segment descriptor.
3. The segmentation unit adds the segment base and effective address to
generate a linear address.
4. It gives 4 level protection to the data or code present in the memory. Every
information in the memory is assigned a privilege level from PL0 to PL3.
Here, PL0 holds the highest priority and PL3 holds the lowest priority.
Paging Unit:
1. The paging unit changes the linear address into a physical address.
2. The paging unit supports multitasking. This is so because the physical
memory is not required to hold the whole segment of any task.
3. Despite this, only that part of the segment which is needed to be currently
executed must be stored in that memory whose physical address is calculated
by the paging unit.
4. This resultantly reduces the memory requirement and hence this frees the
memory for other tasks. Thus by this we get an effective way for managing
the memory to support multitasking.
Enlist Features of 80386 and explain any two ?
Ans:
1. As it is a 32-bit microprocessor. Thus has a 32-bit ALU.
2. 80386 has a 32-bit data bus.
3. It holds an address bus of 32 bits.
4. It supports physical memory addressability of 4 GB and virtual memory
addressability of 64 TB.
5. 80386 supports a variety of operating clock frequencies, which are 16 MHz, 20 MHz,
25 MHz, and 33 MHz.
6. It offers a 3 stage pipeline: fetch, decode and execute. As it supports simultaneous
fetching, decoding, and execution inside the system.
7. Integrated Memory Management Unit
8. Segmentation and Paging support
9. 4 Levels of Protection
10. Fully Compatible with 80286

Draw Register set/ Register Organization of 80386 and explain their function?
Ans:
General Purpose Registers:
1. The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX, EBP,
ESP, ESI, and EDI. These registers are used interchangeably to contain the operands
of logical and arithmetic operations.
2. The low-order word of each of these eight registers has a separate name and can be
treated as a unit. This feature is useful for handling 16-bit data. The word registers
are named AX, BX, CX, DX, BP, SP, SI, and DI.
3. Each byte of the 16-bit registers further separate to handling characters and other
8-bit data items. The byte registers are named AH, BH, CH, and DH (high bytes); and
AL, BL, CL, and DL (low bytes).
Segment Registers
1. The segment registers CS, DS, SS, ES, FS, and GS are used to identify these six current
segments.
2. CS(code segment): The segment containing the currently executing sequence of
instructions is known as the current code segment
3. SS(Stack segment): All stack operations use the SS register to locate the stack.
Subroutine calls, parameters, and procedure activation records usually require that
a region of memory be allocated for a stack.
4. DS(Data segment): The DS, ES, FS, and GS registers allow the specification of four
data segments, each addressable by the currently executing program.
Flags Register:
1. The status flags of the EFLAGS register allow the results of one instruction to
influence later instructions.
2. The arithmetic instructions use OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String),
CMPS (Compare String), and LOOP instructions use ZF to signal that their operations
are complete.
3. There are instructions to set, clear, and complement CF before execution of an
arithmetic instruction.
Instruction Pointer:
1. The instruction pointer register (EIP) contains the offset address, relative to the
start of the current code segment, of the next sequential instruction to be executed.
2. The instruction pointer is not directly visible to the programmer; it is controlled
implicitly by control-transfer instructions, interrupts, and exceptions.
Explain Data Types of 80386?
Ans:

The fundamental data types of 80386 are,

Byte : 8 bits
Word : 2 contiguous bytes
Doubleword : 2 contiguous words
Bit : A single bit quantity.
Bit Field : A group of up to 32 contiguous bits, which spans a maximum of four bytes.
Bit String : A set of contiguous bits, on the Intel386 DX bit strings can be up to 4 gigabits
long.
Byte: A signed 8-bit quantity. (-128 through +127)
Unsigned Byte : An unsigned 8-bit quantity. (0 through 255)
Integer (Word) : A signed 16-bit quantity. (-32,768 through +32,767)
Unsigned Integer (Word) : An unsigned 16-bit quantity. (0 through 65535)
Long Integer (Double Word) : A signed 32-bit quantity. All operations assume a a 2's
31 31
complement representation. (-2 through +2 -1)
Signed Quad Word : A signed 64-bit quantity.
Unsigned Quad Word : An unsigned 64-bit quantity.
Offset : A 16 or 32-bit offset only quantity which indirectly references another memory
location.
Near Pointer : A 32-bit logical address. A near pointer is an offset within a segment. Near
pointers are used in either a flat or a segmented model of memory organization.
Far Pointer : A 48-bit logical address of two components : A 16-bit segment selector
component and a 32-bit offset component. Far pointers are used by applications
programmers only when systems designers choose a segmented memory organization.
Char : A byte representation of an ASCII Alphanumeric or control character.
String : A contiguous sequence of bytes, words or double words. A string may contain
between 1 byte and 4 GB.
BCD : A byte (unpacked) representation of decimal digits 0 - 9.
Packed BCD : A byte (packed) representation of two decimal digits 0 9
Floating Point : A signed 32-bit, 64-bit, or 80-bit real number representation. Floating
point numbers are supported by the intel i387 DX numeric coprocessor.

Explain Register Addressing Mode and Base index addressing mode with example?
Ans:
Register Addressing mode: In register addressing the operand is placed in one of 8 bit or
16 bit general purpose registers. The data is in the register that is specified by the
instruction.
Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX reg

Based Indexed Addressing: The operand’s offset is the sum of the content of a base
register BX or BP and an index register SI or DI.
Example: ADD AX, [BX+SI]

Describe the following addressing modes of 80386 with Example:

i) Index Addressing mode ii) Direct addressing mode

i) Index Addressing mode

In this mode, an index register's contents are added to a displacement
to form the effective address of the operand.
Example: MOV EBX, [ SI ] + 159DH

ii) Direct addressing mode

In this mode, the instruction is having the effective address of the operand. This effective
address is used as an 8, 16 or 32 displacement from the location specified by the current
value in the selected segment register is always OS.
Example: MOY EBX, [1590H]
Explain Real Mode, Protected Mode and Virtual Mode of 80386?
Ans:
Protected mode:
1. Protected mode is the natural 32-bit environment of the 80386 processor.
2. Memory Protection: Segmentation and paging for memory protection.
3. Privilege Levels: Four privilege levels (rings) for access control.
4. Multitasking: Hardware-supported task switching.
5. Enhanced Addressing: Access up to 4 GB of physical and 64 TB of virtual memory.
6. Enhanced Instruction Set: New instructions and addressing modes.
7. Real Mode Compatibility: Maintains compatibility with older software.
Real-address mode:
1. Real-address mode (often called just "real mode") is the mode of the processor
immediately after RESET.
2. In real mode the 80386 appears to programmers as a fast 8086 with some new
instructions.
3. Most applications of the 80386 will use real mode for initialization only.
Virtual 8086 mode:
1. Virtual 8086 mode (also called V86 mode) is a dynamic mode in the sense that the
processor can switch repeatedly and rapidly between V86 mode and protected
mode.
2. The CPU enters V86 mode from protected mode to execute an 8086 program, then
leaves V86 mode and enters protected mode to continue executing a native 80386
program.
3. The features that are available to applications programs in protected mode and to all
programs in V86 mode are the same.

Enlist and explain any two conditional and unconditional instructions?

Ans:
Unconditional Transfer Instructions
JMP, CALL, RET, INT and IRET instructions transfer control from one code segment location
to another.
1. JMP (Jump) unconditionally transfers control to the target location. JMP is a one-way
transfer of execution; it does not save a return address on the stack
2. CALL (Call Procedure) activates an out-of-line procedure, saving on the stack the
address of the instruction following the CALL for later use by a RET (Return)
 instruction. CALL places the current value of EIP on the stack. The RET instruction in
the called procedure uses this address to transfer control back to the calling program.

Conditional Transfer Instructions

The conditional transfer instructions are jumps that may or may not transfer control,
depending on the state of the CPU flags when the instruction executes.
1. Conditional jump instructions contain a displacement which is added to the EIP
register if the condition is true. The displacement may be a byte, a word, or a
doubleword. The displacement is signed; therefore, it can be used to jump forward
or backward.
Mnemonic Condition Tested "Jump If..."
JA/JNBE (CF or ZF) = 0 above/not below nor equal
JAE/JNB CF = 0 above or equal/not below

2. Conditional Loop Instructions

LOOPE (Loop While Equal) These instructions automatically decrement the ECX
register before testing ECX and ZF for the branch conditions.
If ECX is non-zero and ZF=1, the program branches to the target label specified in
the instruction. If LOOPE or LOOPZ finds that ECX=0 or ZF=0, control transfers to
the instruction immediately following the LOOPE or LOOPZ instruction.

Explain BT, BTS, BTR and BTC instructions ?

Ans:

1. BT: BT instruction stands for Bit Test, BT copies a bit from a given register to the
carry flag.

Example: BT EAX, 2

2. BTS: BTS (Bit Test and Set) BTS copies a bit from a given register to the carry flag,
but also sets the bit in the register,

3. BTR: BTR (Bit Test and Reset) BTR copies a bit from a given register to the carry flag
and resets it,

4. BTC: BTC (Bit Test and Complement) BTC copies a bit from a given register to the
carry flag and flips it.

Explain Loop Instruction with an example?

Ans.
The loop instructions cause the microprocessor to execute a series of instructions
repeatedly. Basically, the LOOP instructions are short jump instructions on a condition.
The LOOP instruction executes the group of instructions a number of times and it uses
relative addressing mode. The number of iterations will depend on the condition to be
satisfied. The CX register will perform the LOOP operation on the instructions to be
iterated.
For every execution of LOOP instruction, the CX is automatically decremented by one
without affecting flags and performs a short jump to the target address. This loop will
continue until the CX becomes zero. When CX = 0, the execution of the loop will stop and
the instructions after the LOOP will start execution.
Example
mov ECX,10
l1:
<loop body>
loop l1
Unit 2

Differentiate Memory Mapped IO and IO mapped IO?

Ans:

Memory Mapped IO IO Mapped IO

I/O devices are placed in the

Provides separate I/O space, distinct
memory address space of the
from physical memory.
processor.
Only 256 I/O addresses can be generated
access to 4 GB of memory. This
if the direct addressing method is used.
address space is shared between
Indirect addressing method 65536 range
system memory.
can be used.
Only I/O related instructions (IN, INS,
All memory related instructions can
OUT, and OUTS) are used to transfer data
be used to access I/O devices.
through the I/O ports.
Since memory address space is
Maximum number of I/O devices that
more than I/O address space, the
can be connected is less than that in
maximum number of I/O devices
memory mapped I/O.
can be connected is more.
Since more address lines are used
Comparatively less decoding hardware is
more decoding hardware is
required.
required.
More flexibility in using addressing Less flexibility in using addressing
modes. modes.

Explain Bit scan instructions : BSF and BSR in 80386

Ans:

BSF (Bit Scan Forward):

BSF searches the bits of the source operand (usually a register or memory location) from
the least significant bit (LSB) towards the most significant bit (MSB) for the first set bit (i.e.,
a bit with a value of 1).

Once it finds the first set bit, it stores the position of that bit (the bit number) into the
destination register.

If the source operand is 0, the result of BSF is undefined.

Explain Pipelining in detail?
Ans.
The 80386 possesses the ability of 3 stages pipelining thus performs fetching, decoding,
and execution simultaneously along with memory management and bus accessing. Thus all
these units operate parallelly. This pipelining technique leads to a reduction in overall
processing time thereby increasing the performance of the overall system.

Explain VM, PE bit with set and reset conditions?

Ans:
VM (Virtual 8086 Mode, bit 17)
When set, the VM flag indicates that the task is executing an 8086 program.

PE (Protection Enable, bit 0)

Setting PE causes the processor to begin executing in protected mode. Resetting PE returns
to real-address mode .

Draw and Explain Read or Write Cycle with pipelined address timing
Ans:
 ● The cycle 1 and cycle 2 in the diagram show non pipelined write and read cycles and
cycle 3 and cycle 4 in the diagram show pipelined write and read cycles,

● This diagram also shows how wait state can be avoided using pipelined bus cycles.

● In the pipelined bus cycle the address for the next bus cycle is sent during the T2 -
state of the current cycle. In 80386DX, NA (next address) signal initiates address
pipelining. The 80386DX samples NA signal at the beginning of phase 2 of any T
state in which ADS is not active, specifically.

Draw and Explain the functional pin diagram of 80386DX

Ans:

A31-A2 (Address Bus) Address lines A31-A2 are used as the upper 30 bits of the 32-bit
address bus. These lines can address any memory locations of 1 GB x 32 memory in the
80386 memory system. A1-A0 A1 and A0 are encoded to generate BE3, BE2, BE1 and BE0.
D31-D0 (Data Bus) The data bus D31-D0 are used to transfer data between the
microprocessor and memory and input/output devices.
BE3–BE0 (Bank Enable Signals) The memory system of 80386 can be observed as a
4-byte wide memory access mechanism. The four byte enable signals arc BE3, BE2, BE1 and
BE0. These signals are used to enable four banks. These signals are generated by the
microprocessor from address bits A1 and A0 and used to access 1 byte, 2 bytes or word and
4bytes or double word of data simultaneously.
Bus control signals
BS16 Bus size of 16 bits BS16 indicates the interfacing of 16-bit devices with the 32-bit
wide 80386 data bus.
N̅A̅ The N̅A̅ represents the Next Address input signal. When this signal is active low, it
allows address pipelining in the 80386 bus cycles.
R̅E̅A̅D̅Y̅ The R̅E̅A̅D̅Y̅ signal indicates that the previous bus cycle has been completed and
the bus is ready for the next bus cycle. This signal controls the number of WAIT states
inserted into the bus cycle. Usually, this signal is used for interfacing slow I/O devices with
CPU.

Bus status signals

M/I̅O̅ (Memory/Input/Output) The M/I̅O̅ pin is used to select the memory and I/O
related operations. When it is logic level ‘1’, memory devices will be selected. If it is logic
level ‘0’, I/O devices will be selected for data transfer. During I/O operation, the address bus
consists of a 16-bit I/O address.
W/R̅ (Write/Read) The W/R̅ signal is used to indicate the read and write bus cycles. When
W/R̅ =1, the current bus cycle is a write cycle. If W/R̅ = 0, the current bus cycle is a read
cycle.
D/C̅ (Data and Control) The D/C̅ output signal indicates whether the current bus cycle is
data cycle, i.e., memory and I/O read or write cycles, or the current bus cycle is a control
cycle, i.e., interrupt acknowledge, halt or code fetch operations.
A̅D̅S̅ (Address Data Strobe) This 80386 Pin Diagram issues a valid memory or I/O address
and the address bus and bus cycle pins W/R̅, D/C̅, M/I̅O̅ and BE3-BE0 are holding their
respective valid signals.
L̅O̅C̅K̅ When the L̅O̅C̅K̅ output pin is at logic level 0, the bus lock prevents the other bus
masters from gaining control of the system bus. This signal is most frequently used during
DMA accesses.

Coprocessor interface
P̅E̅R̅E̅Q̅ The Processor Extension Request (PEREQ) indicates that the 80387 arithmetic
coprocessor has data to transfer to the processor.
B̅U̅S̅Y̅ The BUSY input signal indicates that the math coprocessor is busy.
E̅R̅R̅O̅R̅ The Error input signal indicates that the math coprocessor has an error condition.

Interrupt interface
INTR The Interrupt Request (INTR) pin is used as a maskable interrupt input. This pin will
be masked using the IF of the flag register.
NMI The Non-maskable Interrupt (NMI) signal requests a nonmaskable interrupt just like
the 8086 microprocessor.
RESET When RESET pin is high, the processor suspends the current operation and
becomes reset. Therefore, the processor restarts the execution from the starting memory
location FFFFFFF0H

DMA Interface
HOLD The Hold request signal allows another bus master to request control of the local
bus. This signal is commonly used in DMA operation just like it did on the 8086
microprocessor.
HLDA The Hold Acknowledgement (HLDA) indicates that the 80386 processor has
surrendered control of its local bus to another bus master.